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8#include <linux/dma-mapping.h>
9#include <linux/platform_device.h>
10#include <linux/slab.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/delay.h>
14
15#include <sound/core.h>
16#include <sound/pcm.h>
17#include <sound/soc.h>
18#include <sound/tlv.h>
19
20#include "mt6351.h"
21
22
23#define RG_CLKSQ_EN_AUD_BIT (0)
24
25
26#define RG_AUDNCP_CK_PDN_BIT (12)
27#define RG_AUDIF_CK_PDN_BIT (13)
28#define RG_AUD_CK_PDN_BIT (14)
29#define RG_ZCD13M_CK_PDN_BIT (15)
30
31
32#define RG_AUDDACLPWRUP_VAUDP32_BIT (0)
33#define RG_AUDDACRPWRUP_VAUDP32_BIT (1)
34#define RG_AUD_DAC_PWR_UP_VA32_BIT (2)
35#define RG_AUD_DAC_PWL_UP_VA32_BIT (3)
36
37#define RG_AUDHSPWRUP_VAUDP32_BIT (4)
38
39#define RG_AUDHPLPWRUP_VAUDP32_BIT (5)
40#define RG_AUDHPRPWRUP_VAUDP32_BIT (6)
41
42#define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT (7)
43#define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK (0x3)
44
45#define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT (9)
46#define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK (0x3)
47
48#define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT (11)
49#define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK (0x3)
50
51#define RG_AUDHSSCDISABLE_VAUDP32 (13)
52#define RG_AUDHPLSCDISABLE_VAUDP32_BIT (14)
53#define RG_AUDHPRSCDISABLE_VAUDP32_BIT (15)
54
55
56#define RG_HSOUTPUTSTBENH_VAUDP32_BIT (8)
57
58
59#define RG_AUDLOLPWRUP_VAUDP32_BIT (2)
60
61#define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT (3)
62#define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK (0x3)
63
64#define RG_AUDLOLSCDISABLE_VAUDP32_BIT (5)
65#define RG_LOOUTPUTSTBENH_VAUDP32_BIT (9)
66
67
68#define RG_ABIDEC_RSVD0_VAUDP32_HPL_BIT (8)
69#define RG_ABIDEC_RSVD0_VAUDP32_HPR_BIT (9)
70#define RG_ABIDEC_RSVD0_VAUDP32_HS_BIT (10)
71#define RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT (11)
72
73
74#define RG_AUDIBIASPWRDN_VAUDP32_BIT (8)
75#define RG_RSTB_DECODER_VA32_BIT (9)
76#define RG_AUDGLB_PWRDN_VA32_BIT (12)
77
78#define RG_LCLDO_DEC_EN_VA32_BIT (13)
79#define RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT (15)
80
81#define RG_NVREG_EN_VAUDP32_BIT (8)
82
83#define RG_AUDGLB_LP2_VOW_EN_VA32 10
84
85
86#define RG_AFE_ON_BIT (0)
87
88
89#define RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT (0)
90
91
92#define UL_SRC_ON_TMP_CTL (0)
93
94
95#define RG_DL_SINE_ON_SFT (0)
96#define RG_DL_SINE_ON_MASK (0x1)
97
98#define RG_UL_SINE_ON_SFT (1)
99#define RG_UL_SINE_ON_MASK (0x1)
100
101
102#define AUD_TOP_PDN_RESERVED_BIT 0
103#define AUD_TOP_PWR_CLK_DIS_CTL_BIT 2
104#define AUD_TOP_PDN_ADC_CTL_BIT 5
105#define AUD_TOP_PDN_DAC_CTL_BIT 6
106#define AUD_TOP_PDN_AFE_CTL_BIT 7
107
108
109#define SGEN_C_MUTE_SW_CTL_BIT 6
110#define SGEN_C_DAC_EN_CTL_BIT 7
111
112
113#define RG_NCP_ON_BIT 0
114
115
116#define RG_VUSB33_EN 1
117#define RG_VUSB33_ON_CTRL 3
118
119
120#define RG_VA18_EN 1
121#define RG_VA18_ON_CTRL 3
122
123
124#define RG_AUDPREAMPLON 0
125#define RG_AUDPREAMPLDCCEN 1
126#define RG_AUDPREAMPLDCPRECHARGE 2
127
128#define RG_AUDPREAMPLINPUTSEL_SFT (4)
129#define RG_AUDPREAMPLINPUTSEL_MASK (0x3)
130
131#define RG_AUDADCLPWRUP 12
132
133#define RG_AUDADCLINPUTSEL_SFT (13)
134#define RG_AUDADCLINPUTSEL_MASK (0x3)
135
136
137#define RG_AUDPREAMPRON 0
138#define RG_AUDPREAMPRDCCEN 1
139#define RG_AUDPREAMPRDCPRECHARGE 2
140
141#define RG_AUDPREAMPRINPUTSEL_SFT (4)
142#define RG_AUDPREAMPRINPUTSEL_MASK (0x3)
143
144#define RG_AUDADCRPWRUP 12
145
146#define RG_AUDADCRINPUTSEL_SFT (13)
147#define RG_AUDADCRINPUTSEL_MASK (0x3)
148
149
150#define RG_AUDADCCLKRSTB 6
151
152
153#define RG_AUDPWDBMICBIAS0 0
154#define RG_AUDMICBIAS0VREF 4
155#define RG_AUDMICBIAS0LOWPEN 7
156
157#define RG_AUDPWDBMICBIAS2 8
158#define RG_AUDMICBIAS2VREF 12
159#define RG_AUDMICBIAS2LOWPEN 15
160
161
162#define RG_AUDPWDBMICBIAS1 0
163#define RG_AUDMICBIAS1DCSW1NEN 2
164#define RG_AUDMICBIAS1VREF 4
165#define RG_AUDMICBIAS1LOWPEN 7
166
167enum {
168 AUDIO_ANALOG_VOLUME_HSOUTL,
169 AUDIO_ANALOG_VOLUME_HSOUTR,
170 AUDIO_ANALOG_VOLUME_HPOUTL,
171 AUDIO_ANALOG_VOLUME_HPOUTR,
172 AUDIO_ANALOG_VOLUME_LINEOUTL,
173 AUDIO_ANALOG_VOLUME_LINEOUTR,
174 AUDIO_ANALOG_VOLUME_MICAMP1,
175 AUDIO_ANALOG_VOLUME_MICAMP2,
176 AUDIO_ANALOG_VOLUME_TYPE_MAX
177};
178
179
180enum {
181 SUPPLY_SUBSEQ_SETTING,
182 SUPPLY_SUBSEQ_ENABLE,
183 SUPPLY_SUBSEQ_MICBIAS,
184};
185
186#define REG_STRIDE 2
187
188struct mt6351_priv {
189 struct device *dev;
190 struct regmap *regmap;
191
192 unsigned int dl_rate;
193 unsigned int ul_rate;
194
195 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
196
197 int hp_en_counter;
198};
199
200static void set_hp_gain_zero(struct snd_soc_component *cmpnt)
201{
202 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
203 0x1f << 7, 0x8 << 7);
204 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2,
205 0x1f << 0, 0x8 << 0);
206}
207
208static unsigned int get_cap_reg_val(struct snd_soc_component *cmpnt,
209 unsigned int rate)
210{
211 switch (rate) {
212 case 8000:
213 return 0;
214 case 16000:
215 return 1;
216 case 32000:
217 return 2;
218 case 48000:
219 return 3;
220 case 96000:
221 return 4;
222 case 192000:
223 return 5;
224 default:
225 dev_warn(cmpnt->dev, "%s(), error rate %d, return 3",
226 __func__, rate);
227 return 3;
228 }
229}
230
231static unsigned int get_play_reg_val(struct snd_soc_component *cmpnt,
232 unsigned int rate)
233{
234 switch (rate) {
235 case 8000:
236 return 0;
237 case 11025:
238 return 1;
239 case 12000:
240 return 2;
241 case 16000:
242 return 3;
243 case 22050:
244 return 4;
245 case 24000:
246 return 5;
247 case 32000:
248 return 6;
249 case 44100:
250 return 7;
251 case 48000:
252 case 96000:
253 case 192000:
254 return 8;
255 default:
256 dev_warn(cmpnt->dev, "%s(), error rate %d, return 8",
257 __func__, rate);
258 return 8;
259 }
260}
261
262static int mt6351_codec_dai_hw_params(struct snd_pcm_substream *substream,
263 struct snd_pcm_hw_params *params,
264 struct snd_soc_dai *dai)
265{
266 struct snd_soc_component *cmpnt = dai->component;
267 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
268 unsigned int rate = params_rate(params);
269
270 dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n",
271 __func__, substream->stream, rate);
272
273 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
274 priv->dl_rate = rate;
275 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
276 priv->ul_rate = rate;
277
278 return 0;
279}
280
281static const struct snd_soc_dai_ops mt6351_codec_dai_ops = {
282 .hw_params = mt6351_codec_dai_hw_params,
283};
284
285#define MT6351_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
286 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
287 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
288 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
289 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
290 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
291
292static struct snd_soc_dai_driver mt6351_dai_driver[] = {
293 {
294 .name = "mt6351-snd-codec-aif1",
295 .playback = {
296 .stream_name = "AIF1 Playback",
297 .channels_min = 1,
298 .channels_max = 2,
299 .rates = SNDRV_PCM_RATE_8000_48000 |
300 SNDRV_PCM_RATE_96000 |
301 SNDRV_PCM_RATE_192000,
302 .formats = MT6351_FORMATS,
303 },
304 .capture = {
305 .stream_name = "AIF1 Capture",
306 .channels_min = 1,
307 .channels_max = 2,
308 .rates = SNDRV_PCM_RATE_8000 |
309 SNDRV_PCM_RATE_16000 |
310 SNDRV_PCM_RATE_32000 |
311 SNDRV_PCM_RATE_48000 |
312 SNDRV_PCM_RATE_96000 |
313 SNDRV_PCM_RATE_192000,
314 .formats = MT6351_FORMATS,
315 },
316 .ops = &mt6351_codec_dai_ops,
317 },
318};
319
320enum {
321 HP_GAIN_SET_ZERO,
322 HP_GAIN_RESTORE,
323};
324
325static void hp_gain_ramp_set(struct snd_soc_component *cmpnt, int hp_gain_ctl)
326{
327 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
328 int idx, old_idx, offset, reg_idx;
329
330 if (hp_gain_ctl == HP_GAIN_SET_ZERO) {
331 idx = 8;
332 old_idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
333 } else {
334 idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
335 old_idx = 8;
336 }
337 dev_dbg(priv->dev, "%s(), idx %d, old_idx %d\n",
338 __func__, idx, old_idx);
339
340 if (idx > old_idx)
341 offset = idx - old_idx;
342 else
343 offset = old_idx - idx;
344
345 reg_idx = old_idx;
346
347 while (offset > 0) {
348 reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1;
349
350
351 if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) {
352 regmap_update_bits(cmpnt->regmap,
353 MT6351_ZCD_CON2,
354 0xf9f,
355 (reg_idx << 7) | reg_idx);
356 usleep_range(100, 120);
357 }
358 offset--;
359 }
360}
361
362static void hp_zcd_enable(struct snd_soc_component *cmpnt)
363{
364
365
366 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 8, 0x1 << 8);
367 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 7, 0x0 << 7);
368
369
370 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 6, 0x1 << 6);
371
372 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x3 << 4, 0x0 << 4);
373 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 1, 0x5 << 1);
374 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 0, 0x1 << 0);
375}
376
377static void hp_zcd_disable(struct snd_soc_component *cmpnt)
378{
379 regmap_write(cmpnt->regmap, MT6351_ZCD_CON0, 0x0000);
380}
381
382static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
383static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
384
385static const struct snd_kcontrol_new mt6351_snd_controls[] = {
386
387 SOC_DOUBLE_TLV("Headphone Volume",
388 MT6351_ZCD_CON2, 0, 7, 0x12, 1,
389 playback_tlv),
390 SOC_DOUBLE_TLV("Lineout Volume",
391 MT6351_ZCD_CON1, 0, 7, 0x12, 1,
392 playback_tlv),
393 SOC_SINGLE_TLV("Handset Volume",
394 MT6351_ZCD_CON3, 0, 0x12, 1,
395 playback_tlv),
396
397 SOC_DOUBLE_R_TLV("PGA Volume",
398 MT6351_AUDENC_ANA_CON0, MT6351_AUDENC_ANA_CON1,
399 8, 4, 0,
400 pga_tlv),
401};
402
403
404
405
406static const char *const lo_in_mux_map[] = {
407 "Open", "Mute", "Playback", "Test Mode",
408};
409
410static int lo_in_mux_map_value[] = {
411 0x0, 0x1, 0x2, 0x3,
412};
413
414static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
415 MT6351_AUDDEC_ANA_CON3,
416 RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT,
417 RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK,
418 lo_in_mux_map,
419 lo_in_mux_map_value);
420
421static const struct snd_kcontrol_new lo_in_mux_control =
422 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
423
424
425static const char *const hp_in_mux_map[] = {
426 "Open", "LoudSPK Playback", "Audio Playback", "Test Mode",
427};
428
429static int hp_in_mux_map_value[] = {
430 0x0, 0x1, 0x2, 0x3,
431};
432
433static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
434 MT6351_AUDDEC_ANA_CON0,
435 RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT,
436 RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK,
437 hp_in_mux_map,
438 hp_in_mux_map_value);
439
440static const struct snd_kcontrol_new hpl_in_mux_control =
441 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
442
443static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
444 MT6351_AUDDEC_ANA_CON0,
445 RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT,
446 RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK,
447 hp_in_mux_map,
448 hp_in_mux_map_value);
449
450static const struct snd_kcontrol_new hpr_in_mux_control =
451 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
452
453
454static const char *const rcv_in_mux_map[] = {
455 "Open", "Mute", "Voice Playback", "Test Mode",
456};
457
458static int rcv_in_mux_map_value[] = {
459 0x0, 0x1, 0x2, 0x3,
460};
461
462static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
463 MT6351_AUDDEC_ANA_CON0,
464 RG_AUDHSMUXINPUTSEL_VAUDP32_SFT,
465 RG_AUDHSMUXINPUTSEL_VAUDP32_MASK,
466 rcv_in_mux_map,
467 rcv_in_mux_map_value);
468
469static const struct snd_kcontrol_new rcv_in_mux_control =
470 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
471
472
473static const char *const dac_in_mux_map[] = {
474 "Normal Path", "Sgen",
475};
476
477static int dac_in_mux_map_value[] = {
478 0x0, 0x1,
479};
480
481static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
482 MT6351_AFE_TOP_CON0,
483 RG_DL_SINE_ON_SFT,
484 RG_DL_SINE_ON_MASK,
485 dac_in_mux_map,
486 dac_in_mux_map_value);
487
488static const struct snd_kcontrol_new dac_in_mux_control =
489 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
490
491
492static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
493 MT6351_AFE_TOP_CON0,
494 RG_UL_SINE_ON_SFT,
495 RG_UL_SINE_ON_MASK,
496 dac_in_mux_map,
497 dac_in_mux_map_value);
498
499static const struct snd_kcontrol_new aif_out_mux_control =
500 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
501
502
503static const char *const adc_left_mux_map[] = {
504 "Idle", "AIN0", "Left Preamplifier", "Idle_1",
505};
506
507static int adc_left_mux_map_value[] = {
508 0x0, 0x1, 0x2, 0x3,
509};
510
511static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
512 MT6351_AUDENC_ANA_CON0,
513 RG_AUDADCLINPUTSEL_SFT,
514 RG_AUDADCLINPUTSEL_MASK,
515 adc_left_mux_map,
516 adc_left_mux_map_value);
517
518static const struct snd_kcontrol_new adc_left_mux_control =
519 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
520
521
522static const char *const adc_right_mux_map[] = {
523 "Idle", "AIN0", "Right Preamplifier", "Idle_1",
524};
525
526static int adc_right_mux_map_value[] = {
527 0x0, 0x1, 0x2, 0x3,
528};
529
530static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
531 MT6351_AUDENC_ANA_CON1,
532 RG_AUDADCRINPUTSEL_SFT,
533 RG_AUDADCRINPUTSEL_MASK,
534 adc_right_mux_map,
535 adc_right_mux_map_value);
536
537static const struct snd_kcontrol_new adc_right_mux_control =
538 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
539
540
541static const char *const pga_left_mux_map[] = {
542 "None", "AIN0", "AIN1", "AIN2",
543};
544
545static int pga_left_mux_map_value[] = {
546 0x0, 0x1, 0x2, 0x3,
547};
548
549static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
550 MT6351_AUDENC_ANA_CON0,
551 RG_AUDPREAMPLINPUTSEL_SFT,
552 RG_AUDPREAMPLINPUTSEL_MASK,
553 pga_left_mux_map,
554 pga_left_mux_map_value);
555
556static const struct snd_kcontrol_new pga_left_mux_control =
557 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
558
559
560static const char *const pga_right_mux_map[] = {
561 "None", "AIN0", "AIN3", "AIN2",
562};
563
564static int pga_right_mux_map_value[] = {
565 0x0, 0x1, 0x2, 0x3,
566};
567
568static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
569 MT6351_AUDENC_ANA_CON1,
570 RG_AUDPREAMPRINPUTSEL_SFT,
571 RG_AUDPREAMPRINPUTSEL_MASK,
572 pga_right_mux_map,
573 pga_right_mux_map_value);
574
575static const struct snd_kcontrol_new pga_right_mux_control =
576 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
577
578static int mt_reg_set_clr_event(struct snd_soc_dapm_widget *w,
579 struct snd_kcontrol *kcontrol,
580 int event)
581{
582 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
583
584 switch (event) {
585 case SND_SOC_DAPM_POST_PMU:
586 if (w->on_val) {
587
588 regmap_update_bits(cmpnt->regmap,
589 w->reg + REG_STRIDE,
590 0x1 << w->shift,
591 0x1 << w->shift);
592 } else {
593
594 regmap_update_bits(cmpnt->regmap,
595 w->reg + REG_STRIDE * 2,
596 0x1 << w->shift,
597 0x1 << w->shift);
598 }
599 break;
600 case SND_SOC_DAPM_PRE_PMD:
601 if (w->off_val) {
602
603 regmap_update_bits(cmpnt->regmap,
604 w->reg + REG_STRIDE,
605 0x1 << w->shift,
606 0x1 << w->shift);
607 } else {
608
609 regmap_update_bits(cmpnt->regmap,
610 w->reg + REG_STRIDE * 2,
611 0x1 << w->shift,
612 0x1 << w->shift);
613 }
614 break;
615 default:
616 break;
617 }
618
619 return 0;
620}
621
622static int mt_ncp_event(struct snd_soc_dapm_widget *w,
623 struct snd_kcontrol *kcontrol,
624 int event)
625{
626 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
627
628 switch (event) {
629 case SND_SOC_DAPM_PRE_PMU:
630 regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG1,
631 0xffff, 0x1515);
632
633 regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG0,
634 0xfffe, 0x8C00);
635 break;
636 case SND_SOC_DAPM_POST_PMU:
637 usleep_range(250, 270);
638 break;
639 default:
640 break;
641 }
642
643 return 0;
644}
645
646static int mt_sgen_event(struct snd_soc_dapm_widget *w,
647 struct snd_kcontrol *kcontrol,
648 int event)
649{
650 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
651
652 switch (event) {
653 case SND_SOC_DAPM_PRE_PMU:
654 regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG0,
655 0xffef, 0x0008);
656 regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG1,
657 0xffff, 0x0101);
658 break;
659 default:
660 break;
661 }
662
663 return 0;
664}
665
666static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
667 struct snd_kcontrol *kcontrol,
668 int event)
669{
670 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
671 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
672
673 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
674 __func__, event, priv->dl_rate);
675
676 switch (event) {
677 case SND_SOC_DAPM_PRE_PMU:
678
679 regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
680 0xffff, 0x0006);
681
682 regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON0,
683 0xffff, 0xC3A1);
684
685 regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
686 0xffff, 0x0003);
687
688 regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2,
689 0xffff, 0x000B);
690
691 regmap_update_bits(cmpnt->regmap, MT6351_AFE_DL_SDM_CON1,
692 0xffff, 0x001E);
693
694 regmap_write(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG0,
695 (get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
696 0x330);
697 regmap_write(cmpnt->regmap, MT6351_AFE_DL_SRC2_CON0_H,
698 (get_play_reg_val(cmpnt, priv->dl_rate) << 12) |
699 0x300);
700
701 regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
702 0x8000, 0x8000);
703 break;
704 default:
705 break;
706 }
707
708 return 0;
709}
710
711static int mt_hp_event(struct snd_soc_dapm_widget *w,
712 struct snd_kcontrol *kcontrol,
713 int event)
714{
715 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
716 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
717 int reg;
718
719 dev_dbg(priv->dev, "%s(), event 0x%x, hp_en_counter %d\n",
720 __func__, event, priv->hp_en_counter);
721
722 switch (event) {
723 case SND_SOC_DAPM_PRE_PMU:
724 priv->hp_en_counter++;
725 if (priv->hp_en_counter > 1)
726 break;
727 else if (priv->hp_en_counter <= 0)
728 dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
729 __func__,
730 priv->hp_en_counter);
731
732 hp_zcd_disable(cmpnt);
733
734
735 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
736 0x0700, 0x0700);
737
738
739 regmap_read(cmpnt->regmap, MT6351_ZCD_CON2, ®);
740 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = reg & 0x1f;
741 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = (reg >> 7) & 0x1f;
742
743
744 regmap_update_bits(cmpnt->regmap,
745 MT6351_ZCD_CON2, 0xffff, 0x0F9F);
746
747 regmap_update_bits(cmpnt->regmap,
748 MT6351_ZCD_CON3, 0xffff, 0x001F);
749
750 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON2,
751 0x0001, 0x0001);
752
753 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
754 0xffff, 0x2000);
755
756 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
757 0xffff, 0x2100);
758
759 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
760 0x0010, 0xE090);
761
762 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
763 0xffff, 0x2140);
764
765 usleep_range(50, 60);
766
767
768 set_hp_gain_zero(cmpnt);
769
770
771 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
772 0xffff, 0x2100);
773
774 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1,
775 0xffff, 0x2000);
776
777 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
778 0x0010, 0xF4EF);
779
780
781
782 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6,
783 0x0700, 0x0300);
784
785
786
787 hp_zcd_enable(cmpnt);
788
789
790 hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
791
792 break;
793 case SND_SOC_DAPM_PRE_PMD:
794 priv->hp_en_counter--;
795 if (priv->hp_en_counter > 0)
796 break;
797 else if (priv->hp_en_counter < 0)
798 dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
799 __func__,
800 priv->hp_en_counter);
801
802
803 hp_zcd_disable(cmpnt);
804
805
806 hp_gain_ramp_set(cmpnt, HP_GAIN_SET_ZERO);
807
808 set_hp_gain_zero(cmpnt);
809 break;
810 case SND_SOC_DAPM_POST_PMD:
811 if (priv->hp_en_counter > 0)
812 break;
813 else if (priv->hp_en_counter < 0)
814 dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n",
815 __func__,
816 priv->hp_en_counter);
817
818
819 regmap_update_bits(cmpnt->regmap,
820 MT6351_AUDDEC_ANA_CON6,
821 0x0700,
822 0x0000);
823
824 regmap_update_bits(cmpnt->regmap,
825 MT6351_AUDDEC_ANA_CON2,
826 0x0001,
827 0x0000);
828
829
830 hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE);
831 break;
832 default:
833 break;
834 }
835
836 return 0;
837}
838
839static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
840 struct snd_kcontrol *kcontrol,
841 int event)
842{
843 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
844 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
845
846 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
847 __func__, event, priv->ul_rate);
848
849 switch (event) {
850 case SND_SOC_DAPM_PRE_PMU:
851
852 regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
853 0xffff, 0x2062);
854
855 regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
856 0xffff, 0x2060);
857
858 regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0,
859 0xffff, 0x2061);
860
861
862 regmap_update_bits(cmpnt->regmap, MT6351_AFE_UL_SRC_CON0_H,
863 0x000E,
864 get_cap_reg_val(cmpnt, priv->ul_rate) << 1);
865
866
867 if (priv->ul_rate <= 48000) {
868
869 regmap_update_bits(cmpnt->regmap,
870 MT6351_AFE_HPANC_CFG0,
871 0x1 << 1,
872 0x1 << 1);
873
874 regmap_update_bits(cmpnt->regmap,
875 MT6351_AFE_HPANC_CFG0,
876 0x1 << 0,
877 0x0 << 0);
878 }
879 break;
880 case SND_SOC_DAPM_PRE_PMD:
881
882 if (priv->ul_rate <= 48000) {
883
884 regmap_update_bits(cmpnt->regmap,
885 MT6351_AFE_HPANC_CFG0,
886 0x1 << 1,
887 0x0 << 1);
888
889 regmap_update_bits(cmpnt->regmap,
890 MT6351_AFE_HPANC_CFG0,
891 0x1 << 0,
892 0x1 << 0);
893 }
894 break;
895 default:
896 break;
897 }
898
899 return 0;
900}
901
902static int mt_adc_clkgen_event(struct snd_soc_dapm_widget *w,
903 struct snd_kcontrol *kcontrol,
904 int event)
905{
906 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
907
908 switch (event) {
909 case SND_SOC_DAPM_PRE_PMU:
910
911 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
912 0x3 << 4, 0x0);
913 break;
914 case SND_SOC_DAPM_POST_PMU:
915
916 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3,
917 0x3 << 2, 0x0);
918 break;
919 default:
920 break;
921 }
922 return 0;
923}
924
925static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
926 struct snd_kcontrol *kcontrol,
927 int event)
928{
929 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
930
931 switch (event) {
932 case SND_SOC_DAPM_PRE_PMU:
933
934 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
935 0x3 << RG_AUDPREAMPLDCPRECHARGE,
936 0x1 << RG_AUDPREAMPLDCPRECHARGE);
937
938 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
939 0x3 << RG_AUDPREAMPLDCCEN,
940 0x1 << RG_AUDPREAMPLDCCEN);
941 break;
942 case SND_SOC_DAPM_POST_PMU:
943 usleep_range(100, 120);
944
945 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0,
946 0x3 << RG_AUDPREAMPLDCPRECHARGE,
947 0x0 << RG_AUDPREAMPLDCPRECHARGE);
948 break;
949 default:
950 break;
951 }
952 return 0;
953}
954
955static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
956 struct snd_kcontrol *kcontrol,
957 int event)
958{
959 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
960
961 switch (event) {
962 case SND_SOC_DAPM_PRE_PMU:
963
964 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
965 0x3 << RG_AUDPREAMPRDCPRECHARGE,
966 0x1 << RG_AUDPREAMPRDCPRECHARGE);
967
968 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
969 0x3 << RG_AUDPREAMPRDCCEN,
970 0x1 << RG_AUDPREAMPRDCCEN);
971 break;
972 case SND_SOC_DAPM_POST_PMU:
973 usleep_range(100, 120);
974
975 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1,
976 0x3 << RG_AUDPREAMPRDCPRECHARGE,
977 0x0 << RG_AUDPREAMPRDCPRECHARGE);
978 break;
979 default:
980 break;
981 }
982 return 0;
983}
984
985static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,
986 struct snd_kcontrol *kcontrol,
987 int event)
988{
989 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
990
991 switch (event) {
992 case SND_SOC_DAPM_PRE_PMU:
993
994 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
995 0x3 << RG_AUDMICBIAS0LOWPEN, 0x0);
996
997 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
998 0x7 << RG_AUDMICBIAS0VREF,
999 0x2 << RG_AUDMICBIAS0VREF);
1000 break;
1001 case SND_SOC_DAPM_POST_PMD:
1002
1003 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
1004 0x7 << RG_AUDMICBIAS0VREF,
1005 0x0 << RG_AUDMICBIAS0VREF);
1006 break;
1007 default:
1008 break;
1009 }
1010 return 0;
1011}
1012
1013static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,
1014 struct snd_kcontrol *kcontrol,
1015 int event)
1016{
1017 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1018
1019 switch (event) {
1020 case SND_SOC_DAPM_PRE_PMU:
1021
1022 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
1023 0x3 << RG_AUDMICBIAS1LOWPEN, 0x0);
1024
1025 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
1026 0x7 << RG_AUDMICBIAS1VREF,
1027 0x7 << RG_AUDMICBIAS1VREF);
1028 break;
1029 case SND_SOC_DAPM_POST_PMD:
1030
1031 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10,
1032 0x7 << RG_AUDMICBIAS1VREF,
1033 0x0 << RG_AUDMICBIAS1VREF);
1034 break;
1035 default:
1036 break;
1037 }
1038 return 0;
1039}
1040
1041static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,
1042 struct snd_kcontrol *kcontrol,
1043 int event)
1044{
1045 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1046
1047 switch (event) {
1048 case SND_SOC_DAPM_PRE_PMU:
1049
1050 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
1051 0x3 << RG_AUDMICBIAS2LOWPEN, 0x0);
1052
1053 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
1054 0x7 << RG_AUDMICBIAS2VREF,
1055 0x2 << RG_AUDMICBIAS2VREF);
1056 break;
1057 case SND_SOC_DAPM_POST_PMD:
1058
1059 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9,
1060 0x7 << RG_AUDMICBIAS2VREF,
1061 0x0 << RG_AUDMICBIAS2VREF);
1062 break;
1063 default:
1064 break;
1065 }
1066 return 0;
1067}
1068
1069
1070static const struct snd_kcontrol_new mt_lineout_control =
1071 SOC_DAPM_SINGLE("Switch", MT6351_AUDDEC_ANA_CON3,
1072 RG_AUDLOLPWRUP_VAUDP32_BIT, 1, 0);
1073
1074
1075static const struct snd_soc_dapm_widget mt6351_dapm_widgets[] = {
1076
1077 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_AFE_CTL", MT6351_AUDIO_TOP_CON0,
1078 AUD_TOP_PDN_AFE_CTL_BIT, 1, NULL, 0),
1079 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_DAC_CTL", MT6351_AUDIO_TOP_CON0,
1080 AUD_TOP_PDN_DAC_CTL_BIT, 1, NULL, 0),
1081 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_ADC_CTL", MT6351_AUDIO_TOP_CON0,
1082 AUD_TOP_PDN_ADC_CTL_BIT, 1, NULL, 0),
1083 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PWR_CLK", MT6351_AUDIO_TOP_CON0,
1084 AUD_TOP_PWR_CLK_DIS_CTL_BIT, 1, NULL, 0),
1085 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PDN_RESERVED", MT6351_AUDIO_TOP_CON0,
1086 AUD_TOP_PDN_RESERVED_BIT, 1, NULL, 0),
1087
1088 SND_SOC_DAPM_SUPPLY("NCP", MT6351_AFE_NCP_CFG0,
1089 RG_NCP_ON_BIT, 0,
1090 mt_ncp_event,
1091 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1092
1093 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
1094 0, 0, NULL, 0),
1095
1096
1097 SND_SOC_DAPM_SUPPLY("AUDGLB", MT6351_AUDDEC_ANA_CON9,
1098 RG_AUDGLB_PWRDN_VA32_BIT, 1, NULL, 0),
1099 SND_SOC_DAPM_SUPPLY("CLKSQ Audio", MT6351_TOP_CLKSQ,
1100 RG_CLKSQ_EN_AUD_BIT, 0,
1101 mt_reg_set_clr_event,
1102 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1103 SND_SOC_DAPM_SUPPLY("ZCD13M_CK", MT6351_TOP_CKPDN_CON0,
1104 RG_ZCD13M_CK_PDN_BIT, 1,
1105 mt_reg_set_clr_event,
1106 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1107 SND_SOC_DAPM_SUPPLY("AUD_CK", MT6351_TOP_CKPDN_CON0,
1108 RG_AUD_CK_PDN_BIT, 1,
1109 mt_reg_set_clr_event,
1110 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1111 SND_SOC_DAPM_SUPPLY("AUDIF_CK", MT6351_TOP_CKPDN_CON0,
1112 RG_AUDIF_CK_PDN_BIT, 1,
1113 mt_reg_set_clr_event,
1114 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1115 SND_SOC_DAPM_SUPPLY("AUDNCP_CK", MT6351_TOP_CKPDN_CON0,
1116 RG_AUDNCP_CK_PDN_BIT, 1,
1117 mt_reg_set_clr_event,
1118 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1119
1120 SND_SOC_DAPM_SUPPLY("AFE_ON", MT6351_AFE_UL_DL_CON0, RG_AFE_ON_BIT, 0,
1121 NULL, 0),
1122
1123
1124 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
1125 MT6351_AFE_DL_SRC2_CON0_L,
1126 RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0,
1127 mt_aif_in_event, SND_SOC_DAPM_PRE_PMU),
1128
1129
1130 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
1131 0, 0, NULL, 0),
1132 SND_SOC_DAPM_SUPPLY("NV Regulator", MT6351_AUDDEC_ANA_CON10,
1133 RG_NVREG_EN_VAUDP32_BIT, 0, NULL, 0),
1134 SND_SOC_DAPM_SUPPLY("AUD_CLK", MT6351_AUDDEC_ANA_CON9,
1135 RG_RSTB_DECODER_VA32_BIT, 0, NULL, 0),
1136 SND_SOC_DAPM_SUPPLY("IBIST", MT6351_AUDDEC_ANA_CON9,
1137 RG_AUDIBIASPWRDN_VAUDP32_BIT, 1, NULL, 0),
1138 SND_SOC_DAPM_SUPPLY("LDO", MT6351_AUDDEC_ANA_CON9,
1139 RG_LCLDO_DEC_EN_VA32_BIT, 0, NULL, 0),
1140 SND_SOC_DAPM_SUPPLY("LDO_REMOTE_SENSE", MT6351_AUDDEC_ANA_CON9,
1141 RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT, 0, NULL, 0),
1142
1143
1144 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
1145
1146 SND_SOC_DAPM_DAC("DACL", NULL, MT6351_AUDDEC_ANA_CON0,
1147 RG_AUDDACLPWRUP_VAUDP32_BIT, 0),
1148 SND_SOC_DAPM_SUPPLY("DACL_BIASGEN", MT6351_AUDDEC_ANA_CON0,
1149 RG_AUD_DAC_PWL_UP_VA32_BIT, 0, NULL, 0),
1150
1151 SND_SOC_DAPM_DAC("DACR", NULL, MT6351_AUDDEC_ANA_CON0,
1152 RG_AUDDACRPWRUP_VAUDP32_BIT, 0),
1153 SND_SOC_DAPM_SUPPLY("DACR_BIASGEN", MT6351_AUDDEC_ANA_CON0,
1154 RG_AUD_DAC_PWR_UP_VA32_BIT, 0, NULL, 0),
1155
1156 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
1157
1158 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6351_AUDDEC_ANA_CON3,
1159 RG_LOOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
1160 SND_SOC_DAPM_SUPPLY("LOL Bias Gen", MT6351_AUDDEC_ANA_CON6,
1161 RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT, 0, NULL, 0),
1162
1163 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6351_AUDDEC_ANA_CON3,
1164 RG_AUDLOLPWRUP_VAUDP32_BIT, 0, NULL, 0),
1165
1166
1167 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_in_mux_control),
1168 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_in_mux_control),
1169
1170 SND_SOC_DAPM_OUT_DRV_E("HPL Power", MT6351_AUDDEC_ANA_CON0,
1171 RG_AUDHPLPWRUP_VAUDP32_BIT, 0, NULL, 0,
1172 mt_hp_event,
1173 SND_SOC_DAPM_PRE_PMU |
1174 SND_SOC_DAPM_PRE_PMD |
1175 SND_SOC_DAPM_POST_PMD),
1176 SND_SOC_DAPM_OUT_DRV_E("HPR Power", MT6351_AUDDEC_ANA_CON0,
1177 RG_AUDHPRPWRUP_VAUDP32_BIT, 0, NULL, 0,
1178 mt_hp_event,
1179 SND_SOC_DAPM_PRE_PMU |
1180 SND_SOC_DAPM_PRE_PMD |
1181 SND_SOC_DAPM_POST_PMD),
1182
1183
1184 SND_SOC_DAPM_MUX("RCV Mux", SND_SOC_NOPM, 0, 0, &rcv_in_mux_control),
1185
1186 SND_SOC_DAPM_SUPPLY("RCV Stability Enh", MT6351_AUDDEC_ANA_CON1,
1187 RG_HSOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
1188 SND_SOC_DAPM_SUPPLY("RCV Bias Gen", MT6351_AUDDEC_ANA_CON6,
1189 RG_ABIDEC_RSVD0_VAUDP32_HS_BIT, 0, NULL, 0),
1190
1191 SND_SOC_DAPM_OUT_DRV("RCV Buffer", MT6351_AUDDEC_ANA_CON0,
1192 RG_AUDHSPWRUP_VAUDP32_BIT, 0, NULL, 0),
1193
1194
1195 SND_SOC_DAPM_OUTPUT("Receiver"),
1196 SND_SOC_DAPM_OUTPUT("Headphone L"),
1197 SND_SOC_DAPM_OUTPUT("Headphone R"),
1198 SND_SOC_DAPM_OUTPUT("LINEOUT L"),
1199
1200
1201 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6351_AFE_SGEN_CFG0,
1202 SGEN_C_DAC_EN_CTL_BIT, 0, NULL, 0),
1203 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6351_AFE_SGEN_CFG0,
1204 SGEN_C_MUTE_SW_CTL_BIT, 1,
1205 mt_sgen_event, SND_SOC_DAPM_PRE_PMU),
1206 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6351_AFE_DL_SRC2_CON0_L,
1207 RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, NULL, 0),
1208
1209 SND_SOC_DAPM_INPUT("SGEN DL"),
1210
1211
1212 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
1213 MT6351_AFE_UL_SRC_CON0_L,
1214 UL_SRC_ON_TMP_CTL, 0,
1215 mt_aif_out_event,
1216 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1217
1218 SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO", SUPPLY_SUBSEQ_ENABLE,
1219 MT6351_LDO_VUSB33_CON0, RG_VUSB33_EN, 0,
1220 NULL, 0),
1221 SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
1222 MT6351_LDO_VUSB33_CON0, RG_VUSB33_ON_CTRL, 1,
1223 NULL, 0),
1224
1225 SND_SOC_DAPM_SUPPLY_S("VA18_LDO", SUPPLY_SUBSEQ_ENABLE,
1226 MT6351_LDO_VA18_CON0, RG_VA18_EN, 0, NULL, 0),
1227 SND_SOC_DAPM_SUPPLY_S("VA18_LDO_CTRL", SUPPLY_SUBSEQ_SETTING,
1228 MT6351_LDO_VA18_CON0, RG_VA18_ON_CTRL, 1,
1229 NULL, 0),
1230
1231 SND_SOC_DAPM_SUPPLY_S("ADC CLKGEN", SUPPLY_SUBSEQ_ENABLE,
1232 MT6351_AUDENC_ANA_CON3, RG_AUDADCCLKRSTB, 0,
1233 mt_adc_clkgen_event,
1234 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1235
1236
1237 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
1238 &aif_out_mux_control),
1239
1240 SND_SOC_DAPM_MUX("ADC L Mux", SND_SOC_NOPM, 0, 0,
1241 &adc_left_mux_control),
1242 SND_SOC_DAPM_MUX("ADC R Mux", SND_SOC_NOPM, 0, 0,
1243 &adc_right_mux_control),
1244
1245 SND_SOC_DAPM_ADC("ADC L", NULL,
1246 MT6351_AUDENC_ANA_CON0, RG_AUDADCLPWRUP, 0),
1247 SND_SOC_DAPM_ADC("ADC R", NULL,
1248 MT6351_AUDENC_ANA_CON1, RG_AUDADCRPWRUP, 0),
1249
1250 SND_SOC_DAPM_MUX("PGA L Mux", SND_SOC_NOPM, 0, 0,
1251 &pga_left_mux_control),
1252 SND_SOC_DAPM_MUX("PGA R Mux", SND_SOC_NOPM, 0, 0,
1253 &pga_right_mux_control),
1254
1255 SND_SOC_DAPM_PGA_E("PGA L", MT6351_AUDENC_ANA_CON0, RG_AUDPREAMPLON, 0,
1256 NULL, 0,
1257 mt_pga_left_event,
1258 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1259 SND_SOC_DAPM_PGA_E("PGA R", MT6351_AUDENC_ANA_CON1, RG_AUDPREAMPRON, 0,
1260 NULL, 0,
1261 mt_pga_right_event,
1262 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1263
1264
1265 SND_SOC_DAPM_SUPPLY_S("Mic Bias 0", SUPPLY_SUBSEQ_MICBIAS,
1266 MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS0, 0,
1267 mt_mic_bias_0_event,
1268 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1269
1270 SND_SOC_DAPM_SUPPLY_S("Mic Bias 2", SUPPLY_SUBSEQ_MICBIAS,
1271 MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS2, 0,
1272 mt_mic_bias_2_event,
1273 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1274
1275 SND_SOC_DAPM_SUPPLY_S("Mic Bias 1", SUPPLY_SUBSEQ_MICBIAS,
1276 MT6351_AUDENC_ANA_CON10, RG_AUDPWDBMICBIAS1, 0,
1277 mt_mic_bias_1_event,
1278 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1279 SND_SOC_DAPM_SUPPLY_S("Mic Bias 1 DCC pull high", SUPPLY_SUBSEQ_MICBIAS,
1280 MT6351_AUDENC_ANA_CON10,
1281 RG_AUDMICBIAS1DCSW1NEN, 0,
1282 NULL, 0),
1283
1284
1285 SND_SOC_DAPM_INPUT("AIN0"),
1286 SND_SOC_DAPM_INPUT("AIN1"),
1287 SND_SOC_DAPM_INPUT("AIN2"),
1288 SND_SOC_DAPM_INPUT("AIN3"),
1289};
1290
1291static const struct snd_soc_dapm_route mt6351_dapm_routes[] = {
1292
1293 {"AIF1TX", NULL, "AIF Out Mux"},
1294 {"AIF1TX", NULL, "VUSB33_LDO"},
1295 {"VUSB33_LDO", NULL, "VUSB33_LDO_CTRL"},
1296 {"AIF1TX", NULL, "VA18_LDO"},
1297 {"VA18_LDO", NULL, "VA18_LDO_CTRL"},
1298
1299 {"AIF1TX", NULL, "AUDGLB"},
1300 {"AIF1TX", NULL, "CLKSQ Audio"},
1301
1302 {"AIF1TX", NULL, "AFE_ON"},
1303
1304 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
1305 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
1306 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
1307 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
1308
1309 {"AIF Out Mux", "Normal Path", "ADC L"},
1310 {"AIF Out Mux", "Normal Path", "ADC R"},
1311
1312 {"ADC L", NULL, "ADC L Mux"},
1313 {"ADC L", NULL, "AUD_CK"},
1314 {"ADC L", NULL, "AUDIF_CK"},
1315 {"ADC L", NULL, "ADC CLKGEN"},
1316 {"ADC R", NULL, "ADC R Mux"},
1317 {"ADC R", NULL, "AUD_CK"},
1318 {"ADC R", NULL, "AUDIF_CK"},
1319 {"ADC R", NULL, "ADC CLKGEN"},
1320
1321 {"ADC L Mux", "AIN0", "AIN0"},
1322 {"ADC L Mux", "Left Preamplifier", "PGA L"},
1323
1324 {"ADC R Mux", "AIN0", "AIN0"},
1325 {"ADC R Mux", "Right Preamplifier", "PGA R"},
1326
1327 {"PGA L", NULL, "PGA L Mux"},
1328 {"PGA R", NULL, "PGA R Mux"},
1329
1330 {"PGA L Mux", "AIN0", "AIN0"},
1331 {"PGA L Mux", "AIN1", "AIN1"},
1332 {"PGA L Mux", "AIN2", "AIN2"},
1333
1334 {"PGA R Mux", "AIN0", "AIN0"},
1335 {"PGA R Mux", "AIN3", "AIN3"},
1336 {"PGA R Mux", "AIN2", "AIN2"},
1337
1338 {"AIN0", NULL, "Mic Bias 0"},
1339 {"AIN2", NULL, "Mic Bias 2"},
1340
1341 {"AIN1", NULL, "Mic Bias 1"},
1342 {"AIN1", NULL, "Mic Bias 1 DCC pull high"},
1343
1344
1345 {"DL Power Supply", NULL, "AUDGLB"},
1346 {"DL Power Supply", NULL, "CLKSQ Audio"},
1347 {"DL Power Supply", NULL, "ZCD13M_CK"},
1348 {"DL Power Supply", NULL, "AUD_CK"},
1349 {"DL Power Supply", NULL, "AUDIF_CK"},
1350 {"DL Power Supply", NULL, "AUDNCP_CK"},
1351
1352 {"DL Power Supply", NULL, "NV Regulator"},
1353 {"DL Power Supply", NULL, "AUD_CLK"},
1354 {"DL Power Supply", NULL, "IBIST"},
1355 {"DL Power Supply", NULL, "LDO"},
1356 {"LDO", NULL, "LDO_REMOTE_SENSE"},
1357
1358
1359 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
1360 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
1361 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
1362 {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"},
1363 {"DL Digital Clock", NULL, "NCP"},
1364 {"DL Digital Clock", NULL, "AFE_ON"},
1365
1366 {"AIF_RX", NULL, "DL Digital Clock"},
1367
1368
1369 {"DAC In Mux", "Normal Path", "AIF_RX"},
1370
1371 {"DAC In Mux", "Sgen", "SGEN DL"},
1372 {"SGEN DL", NULL, "SGEN DL SRC"},
1373 {"SGEN DL", NULL, "SGEN MUTE"},
1374 {"SGEN DL", NULL, "SGEN DL Enable"},
1375 {"SGEN DL", NULL, "DL Digital Clock"},
1376
1377 {"DACL", NULL, "DAC In Mux"},
1378 {"DACL", NULL, "DL Power Supply"},
1379 {"DACL", NULL, "DACL_BIASGEN"},
1380
1381 {"DACR", NULL, "DAC In Mux"},
1382 {"DACR", NULL, "DL Power Supply"},
1383 {"DACR", NULL, "DACR_BIASGEN"},
1384
1385 {"LOL Mux", "Playback", "DACL"},
1386
1387 {"LOL Buffer", NULL, "LOL Mux"},
1388 {"LOL Buffer", NULL, "LO Stability Enh"},
1389 {"LOL Buffer", NULL, "LOL Bias Gen"},
1390
1391 {"LINEOUT L", NULL, "LOL Buffer"},
1392
1393
1394 {"HPL Mux", "Audio Playback", "DACL"},
1395 {"HPR Mux", "Audio Playback", "DACR"},
1396
1397 {"HPL Mux", "LoudSPK Playback", "DACL"},
1398 {"HPR Mux", "LoudSPK Playback", "DACR"},
1399
1400 {"HPL Power", NULL, "HPL Mux"},
1401 {"HPR Power", NULL, "HPR Mux"},
1402
1403 {"Headphone L", NULL, "HPL Power"},
1404 {"Headphone R", NULL, "HPR Power"},
1405
1406
1407 {"RCV Mux", "Voice Playback", "DACL"},
1408
1409 {"RCV Buffer", NULL, "RCV Mux"},
1410 {"RCV Buffer", NULL, "RCV Stability Enh"},
1411 {"RCV Buffer", NULL, "RCV Bias Gen"},
1412
1413 {"Receiver", NULL, "RCV Buffer"},
1414};
1415
1416static int mt6351_codec_init_reg(struct snd_soc_component *cmpnt)
1417{
1418 int ret = 0;
1419
1420
1421 regmap_update_bits(cmpnt->regmap, MT6351_TOP_CLKSQ, 0x0001, 0x0);
1422
1423 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON9,
1424 0x1000, 0x1000);
1425
1426 regmap_update_bits(cmpnt->regmap, MT6351_TOP_CKPDN_CON0_SET,
1427 0x3800, 0x3800);
1428
1429 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0,
1430 0xe000, 0xe000);
1431
1432 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON3,
1433 0x20, 0x20);
1434
1435 regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2,
1436 0x8000, 0x8000);
1437 return ret;
1438}
1439
1440static int mt6351_codec_probe(struct snd_soc_component *cmpnt)
1441{
1442 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1443
1444 snd_soc_component_init_regmap(cmpnt, priv->regmap);
1445
1446 mt6351_codec_init_reg(cmpnt);
1447 return 0;
1448}
1449
1450static const struct snd_soc_component_driver mt6351_soc_component_driver = {
1451 .probe = mt6351_codec_probe,
1452 .controls = mt6351_snd_controls,
1453 .num_controls = ARRAY_SIZE(mt6351_snd_controls),
1454 .dapm_widgets = mt6351_dapm_widgets,
1455 .num_dapm_widgets = ARRAY_SIZE(mt6351_dapm_widgets),
1456 .dapm_routes = mt6351_dapm_routes,
1457 .num_dapm_routes = ARRAY_SIZE(mt6351_dapm_routes),
1458};
1459
1460static int mt6351_codec_driver_probe(struct platform_device *pdev)
1461{
1462 struct mt6351_priv *priv;
1463
1464 priv = devm_kzalloc(&pdev->dev,
1465 sizeof(struct mt6351_priv),
1466 GFP_KERNEL);
1467 if (!priv)
1468 return -ENOMEM;
1469
1470 dev_set_drvdata(&pdev->dev, priv);
1471
1472 priv->dev = &pdev->dev;
1473
1474 priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
1475 if (!priv->regmap)
1476 return -ENODEV;
1477
1478 dev_dbg(priv->dev, "%s(), dev name %s\n",
1479 __func__, dev_name(&pdev->dev));
1480
1481 return devm_snd_soc_register_component(&pdev->dev,
1482 &mt6351_soc_component_driver,
1483 mt6351_dai_driver,
1484 ARRAY_SIZE(mt6351_dai_driver));
1485}
1486
1487static const struct of_device_id mt6351_of_match[] = {
1488 {.compatible = "mediatek,mt6351-sound",},
1489 {}
1490};
1491
1492static struct platform_driver mt6351_codec_driver = {
1493 .driver = {
1494 .name = "mt6351-sound",
1495 .of_match_table = mt6351_of_match,
1496 },
1497 .probe = mt6351_codec_driver_probe,
1498};
1499
1500module_platform_driver(mt6351_codec_driver)
1501
1502
1503MODULE_DESCRIPTION("MT6351 ALSA SoC codec driver");
1504MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
1505MODULE_LICENSE("GPL v2");
1506
