1
2
3#ifndef __Q6AFE_H__
4#define __Q6AFE_H__
5
6#include <dt-bindings/sound/qcom,q6afe.h>
7
8#define AFE_PORT_MAX 105
9
10#define MSM_AFE_PORT_TYPE_RX 0
11#define MSM_AFE_PORT_TYPE_TX 1
12#define AFE_MAX_PORTS AFE_PORT_MAX
13
14#define Q6AFE_MAX_MI2S_LINES 4
15
16#define AFE_MAX_CHAN_COUNT 8
17#define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8
18
19#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
20#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
21
22#define LPAIF_DIG_CLK 1
23#define LPAIF_BIT_CLK 2
24#define LPAIF_OSR_CLK 3
25
26
27#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
28
29#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
30
31#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
32
33#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
34
35#define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
36
37#define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
38
39#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
40
41#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
42
43#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
44
45#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
46
47#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
48
49
50#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
51
52#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
53
54#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
55
56#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
57
58#define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
59
60#define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
61
62#define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
63
64#define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
65
66#define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
67
68#define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
69
70#define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
71
72
73#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
74
75
76#define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200
77
78#define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201
79
80#define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202
81
82#define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203
83
84#define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204
85
86#define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205
87
88#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206
89
90#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207
91
92#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208
93
94#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209
95
96#define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A
97
98
99#define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200
100
101#define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201
102
103#define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202
104
105#define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203
106
107#define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204
108
109#define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205
110
111#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206
112
113#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207
114
115#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208
116
117#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209
118
119#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A
120
121
122#define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300
123
124#define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301
125
126#define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302
127
128#define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304
129
130#define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303
131
132#define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305
133
134#define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306
135
136
137#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0
138
139#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
140
141#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
142
143#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
144
145#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
146
147#define Q6AFE_CMAP_INVALID 0xFFFF
148
149struct q6afe_hdmi_cfg {
150 u16 datatype;
151 u16 channel_allocation;
152 u32 sample_rate;
153 u16 bit_width;
154};
155
156struct q6afe_slim_cfg {
157 u32 sample_rate;
158 u16 bit_width;
159 u16 data_format;
160 u16 num_channels;
161 u8 ch_mapping[AFE_MAX_CHAN_COUNT];
162};
163
164struct q6afe_i2s_cfg {
165 u32 sample_rate;
166 u16 bit_width;
167 u16 data_format;
168 u16 num_channels;
169 u32 sd_line_mask;
170 int fmt;
171};
172
173struct q6afe_tdm_cfg {
174 u16 num_channels;
175 u32 sample_rate;
176 u16 bit_width;
177 u16 data_format;
178 u16 sync_mode;
179 u16 sync_src;
180 u16 nslots_per_frame;
181 u16 slot_width;
182 u16 slot_mask;
183 u32 data_align_type;
184 u16 ch_mapping[AFE_MAX_CHAN_COUNT];
185};
186
187struct q6afe_port_config {
188 struct q6afe_hdmi_cfg hdmi;
189 struct q6afe_slim_cfg slim;
190 struct q6afe_i2s_cfg i2s_cfg;
191 struct q6afe_tdm_cfg tdm;
192};
193
194struct q6afe_port;
195
196struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id);
197int q6afe_port_start(struct q6afe_port *port);
198int q6afe_port_stop(struct q6afe_port *port);
199void q6afe_port_put(struct q6afe_port *port);
200int q6afe_get_port_id(int index);
201void q6afe_hdmi_port_prepare(struct q6afe_port *port,
202 struct q6afe_hdmi_cfg *cfg);
203void q6afe_slim_port_prepare(struct q6afe_port *port,
204 struct q6afe_slim_cfg *cfg);
205int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
206void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);
207
208int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
209 int clk_src, int clk_root,
210 unsigned int freq, int dir);
211#endif
212