LXR linux/arch/arc/kernel/mcip.c

   1/*
   2 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
   3 *
   4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11#include <linux/smp.h>
  12#include <linux/irq.h>
  13#include <linux/spinlock.h>
  14#include <asm/mcip.h>
  15
  16static char smp_cpuinfo_buf[128];
  17static int idu_detected;
  18
  19static DEFINE_RAW_SPINLOCK(mcip_lock);
  20
  21/*
  22 * Any SMP specific init any CPU does when it comes up.
  23 * Here we setup the CPU to enable Inter-Processor-Interrupts
  24 * Called for each CPU
  25 * -Master      : init_IRQ()
  26 * -Other(s)    : start_kernel_secondary()
  27 */
  28void mcip_init_smp(unsigned int cpu)
  29{
  30        smp_ipi_irq_setup(cpu, IPI_IRQ);
  31}
  32
  33static void mcip_ipi_send(int cpu)
  34{
  35        unsigned long flags;
  36        int ipi_was_pending;
  37
  38        /*
  39         * NOTE: We must spin here if the other cpu hasn't yet
  40         * serviced a previous message. This can burn lots
  41         * of time, but we MUST follows this protocol or
  42         * ipi messages can be lost!!!
  43         * Also, we must release the lock in this loop because
  44         * the other side may get to this same loop and not
  45         * be able to ack -- thus causing deadlock.
  46         */
  47
  48        do {
  49                raw_spin_lock_irqsave(&mcip_lock, flags);
  50                __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
  51                ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
  52                if (ipi_was_pending == 0)
  53                        break; /* break out but keep lock */
  54                raw_spin_unlock_irqrestore(&mcip_lock, flags);
  55        } while (1);
  56
  57        __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
  58        raw_spin_unlock_irqrestore(&mcip_lock, flags);
  59
  60#ifdef CONFIG_ARC_IPI_DBG
  61        if (ipi_was_pending)
  62                pr_info("IPI ACK delayed from cpu %d\n", cpu);
  63#endif
  64}
  65
  66static void mcip_ipi_clear(int irq)
  67{
  68        unsigned int cpu, c;
  69        unsigned long flags;
  70        unsigned int __maybe_unused copy;
  71
  72        raw_spin_lock_irqsave(&mcip_lock, flags);
  73
  74        /* Who sent the IPI */
  75        __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
  76
  77        copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK);       /* 1,2,4,8... */
  78
  79        /*
  80         * In rare case, multiple concurrent IPIs sent to same target can
  81         * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
  82         * "vectored" (multiple bits sets) as opposed to typical single bit
  83         */
  84        do {
  85                c = __ffs(cpu);                 /* 0,1,2,3 */
  86                __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
  87                cpu &= ~(1U << c);
  88        } while (cpu);
  89
  90        raw_spin_unlock_irqrestore(&mcip_lock, flags);
  91
  92#ifdef CONFIG_ARC_IPI_DBG
  93        if (c != __ffs(copy))
  94                pr_info("IPIs from %x coalesced to %x\n",
  95                        copy, raw_smp_processor_id());
  96#endif
  97}
  98
  99volatile int wake_flag;
 100
 101static void mcip_wakeup_cpu(int cpu, unsigned long pc)
 102{
 103        BUG_ON(cpu == 0);
 104        wake_flag = cpu;
 105}
 106
 107void arc_platform_smp_wait_to_boot(int cpu)
 108{
 109        while (wake_flag != cpu)
 110                ;
 111
 112        wake_flag = 0;
 113        __asm__ __volatile__("j @first_lines_of_secondary       \n");
 114}
 115
 116struct plat_smp_ops plat_smp_ops = {
 117        .info           = smp_cpuinfo_buf,
 118        .cpu_kick       = mcip_wakeup_cpu,
 119        .ipi_send       = mcip_ipi_send,
 120        .ipi_clear      = mcip_ipi_clear,
 121};
 122
 123void mcip_init_early_smp(void)
 124{
 125#define IS_AVAIL1(var, str)    ((var) ? str : "")
 126
 127        struct mcip_bcr {
 128#ifdef CONFIG_CPU_BIG_ENDIAN
 129                unsigned int pad3:8,
 130                             idu:1, llm:1, num_cores:6,
 131                             iocoh:1,  grtc:1, dbg:1, pad2:1,
 132                             msg:1, sem:1, ipi:1, pad:1,
 133                             ver:8;
 134#else
 135                unsigned int ver:8,
 136                             pad:1, ipi:1, sem:1, msg:1,
 137                             pad2:1, dbg:1, grtc:1, iocoh:1,
 138                             num_cores:6, llm:1, idu:1,
 139                             pad3:8;
 140#endif
 141        } mp;
 142
 143        READ_BCR(ARC_REG_MCIP_BCR, mp);
 144
 145        sprintf(smp_cpuinfo_buf,
 146                "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
 147                mp.ver, mp.num_cores,
 148                IS_AVAIL1(mp.ipi, "IPI "),
 149                IS_AVAIL1(mp.idu, "IDU "),
 150                IS_AVAIL1(mp.dbg, "DEBUG "),
 151                IS_AVAIL1(mp.grtc, "GRTC"));
 152
 153        idu_detected = mp.idu;
 154
 155        if (mp.dbg) {
 156                __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
 157                __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
 158        }
 159
 160        if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
 161                panic("kernel trying to use non-existent GRTC\n");
 162}
 163
 164/***************************************************************************
 165 * ARCv2 Interrupt Distribution Unit (IDU)
 166 *
 167 * Connects external "COMMON" IRQs to core intc, providing:
 168 *  -dynamic routing (IRQ affinity)
 169 *  -load balancing (Round Robin interrupt distribution)
 170 *  -1:N distribution
 171 *
 172 * It physically resides in the MCIP hw block
 173 */
 174
 175#include <linux/irqchip.h>
 176#include <linux/of.h>
 177#include <linux/of_irq.h>
 178
 179/*
 180 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
 181 */
 182static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
 183{
 184        __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
 185}
 186
 187static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
 188                           unsigned int distr)
 189{
 190        union {
 191                unsigned int word;
 192                struct {
 193                        unsigned int distr:2, pad:2, lvl:1, pad2:27;
 194                };
 195        } data;
 196
 197        data.distr = distr;
 198        data.lvl = lvl;
 199        __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
 200}
 201
 202static void idu_irq_mask(struct irq_data *data)
 203{
 204        unsigned long flags;
 205
 206        raw_spin_lock_irqsave(&mcip_lock, flags);
 207        __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
 208        raw_spin_unlock_irqrestore(&mcip_lock, flags);
 209}
 210
 211static void idu_irq_unmask(struct irq_data *data)
 212{
 213        unsigned long flags;
 214
 215        raw_spin_lock_irqsave(&mcip_lock, flags);
 216        __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
 217        raw_spin_unlock_irqrestore(&mcip_lock, flags);
 218}
 219
 220#ifdef CONFIG_SMP
 221static int
 222idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
 223                     bool force)
 224{
 225        unsigned long flags;
 226        cpumask_t online;
 227
 228        /* errout if no online cpu per @cpumask */
 229        if (!cpumask_and(&online, cpumask, cpu_online_mask))
 230                return -EINVAL;
 231
 232        raw_spin_lock_irqsave(&mcip_lock, flags);
 233
 234        idu_set_dest(data->hwirq, cpumask_bits(&online)[0]);
 235        idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
 236
 237        raw_spin_unlock_irqrestore(&mcip_lock, flags);
 238
 239        return IRQ_SET_MASK_OK;
 240}
 241#endif
 242
 243static struct irq_chip idu_irq_chip = {
 244        .name                   = "MCIP IDU Intc",
 245        .irq_mask               = idu_irq_mask,
 246        .irq_unmask             = idu_irq_unmask,
 247#ifdef CONFIG_SMP
 248        .irq_set_affinity       = idu_irq_set_affinity,
 249#endif
 250
 251};
 252
 253static int idu_first_irq;
 254
 255static void idu_cascade_isr(unsigned int core_irq, struct irq_desc *desc)
 256{
 257        struct irq_domain *domain = irq_desc_get_handler_data(desc);
 258        unsigned int idu_irq;
 259
 260        idu_irq = core_irq - idu_first_irq;
 261        generic_handle_irq(irq_find_mapping(domain, idu_irq));
 262}
 263
 264static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
 265{
 266        irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
 267        irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
 268
 269        return 0;
 270}
 271
 272static int idu_irq_xlate(struct irq_domain *d, struct device_node *n,
 273                         const u32 *intspec, unsigned int intsize,
 274                         irq_hw_number_t *out_hwirq, unsigned int *out_type)
 275{
 276        irq_hw_number_t hwirq = *out_hwirq = intspec[0];
 277        int distri = intspec[1];
 278        unsigned long flags;
 279
 280        *out_type = IRQ_TYPE_NONE;
 281
 282        /* XXX: validate distribution scheme again online cpu mask */
 283        if (distri == 0) {
 284                /* 0 - Round Robin to all cpus, otherwise 1 bit per core */
 285                raw_spin_lock_irqsave(&mcip_lock, flags);
 286                idu_set_dest(hwirq, BIT(num_online_cpus()) - 1);
 287                idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
 288                raw_spin_unlock_irqrestore(&mcip_lock, flags);
 289        } else {
 290                /*
 291                 * DEST based distribution for Level Triggered intr can only
 292                 * have 1 CPU, so generalize it to always contain 1 cpu
 293                 */
 294                int cpu = ffs(distri);
 295
 296                if (cpu != fls(distri))
 297                        pr_warn("IDU irq %lx distri mode set to cpu %x\n",
 298                                hwirq, cpu);
 299
 300                raw_spin_lock_irqsave(&mcip_lock, flags);
 301                idu_set_dest(hwirq, cpu);
 302                idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST);
 303                raw_spin_unlock_irqrestore(&mcip_lock, flags);
 304        }
 305
 306        return 0;
 307}
 308
 309static const struct irq_domain_ops idu_irq_ops = {
 310        .xlate  = idu_irq_xlate,
 311        .map    = idu_irq_map,
 312};
 313
 314/*
 315 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
 316 * [24, 23+C]: If C > 0 then "C" common IRQs
 317 * [24+C, N]: Not statically assigned, private-per-core
 318 */
 319
 320
 321static int __init
 322idu_of_init(struct device_node *intc, struct device_node *parent)
 323{
 324        struct irq_domain *domain;
 325        /* Read IDU BCR to confirm nr_irqs */
 326        int nr_irqs = of_irq_count(intc);
 327        int i, irq;
 328
 329        if (!idu_detected)
 330                panic("IDU not detected, but DeviceTree using it");
 331
 332        pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
 333
 334        domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
 335
 336        /* Parent interrupts (core-intc) are already mapped */
 337
 338        for (i = 0; i < nr_irqs; i++) {
 339                /*
 340                 * Return parent uplink IRQs (towards core intc) 24,25,.....
 341                 * this step has been done before already
 342                 * however we need it to get the parent virq and set IDU handler
 343                 * as first level isr
 344                 */
 345                irq = irq_of_parse_and_map(intc, i);
 346                if (!i)
 347                        idu_first_irq = irq;
 348
 349                irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain);
 350        }
 351
 352        __mcip_cmd(CMD_IDU_ENABLE, 0);
 353
 354        return 0;
 355}
 356IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);
 357