LXR linux/arch/arm/mach-imx/common.h

   1/*
   2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
   3 */
   4
   5/*
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11#ifndef __ASM_ARCH_MXC_COMMON_H__
  12#define __ASM_ARCH_MXC_COMMON_H__
  13
  14#include <linux/reboot.h>
  15
  16struct irq_data;
  17struct platform_device;
  18struct pt_regs;
  19struct clk;
  20struct device_node;
  21enum mxc_cpu_pwr_mode;
  22struct of_device_id;
  23
  24void mx1_map_io(void);
  25void mx21_map_io(void);
  26void mx27_map_io(void);
  27void mx31_map_io(void);
  28void mx35_map_io(void);
  29void imx1_init_early(void);
  30void imx21_init_early(void);
  31void imx27_init_early(void);
  32void imx31_init_early(void);
  33void imx35_init_early(void);
  34void mxc_init_irq(void __iomem *);
  35void tzic_init_irq(void);
  36void mx1_init_irq(void);
  37void mx21_init_irq(void);
  38void mx27_init_irq(void);
  39void mx31_init_irq(void);
  40void mx35_init_irq(void);
  41void imx1_soc_init(void);
  42void imx21_soc_init(void);
  43void imx27_soc_init(void);
  44void imx31_soc_init(void);
  45void imx35_soc_init(void);
  46void epit_timer_init(void __iomem *base, int irq);
  47int mx1_clocks_init(unsigned long fref);
  48int mx21_clocks_init(unsigned long lref, unsigned long fref);
  49int mx27_clocks_init(unsigned long fref);
  50int mx31_clocks_init(unsigned long fref);
  51int mx35_clocks_init(void);
  52int mx31_clocks_init_dt(void);
  53struct platform_device *mxc_register_gpio(char *name, int id,
  54        resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
  55void mxc_set_cpu_type(unsigned int type);
  56void mxc_restart(enum reboot_mode, const char *);
  57void mxc_arch_reset_init(void __iomem *);
  58void imx_set_aips(void __iomem *);
  59void imx_aips_allow_unprivileged_access(const char *compat);
  60int mxc_device_init(void);
  61void imx_set_soc_revision(unsigned int rev);
  62void imx_init_revision_from_anatop(void);
  63struct device *imx_soc_device_init(void);
  64void imx6_enable_rbc(bool enable);
  65void imx_gpc_check_dt(void);
  66void imx_gpc_set_arm_power_in_lpm(bool power_off);
  67void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
  68void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
  69
  70enum mxc_cpu_pwr_mode {
  71        WAIT_CLOCKED,           /* wfi only */
  72        WAIT_UNCLOCKED,         /* WAIT */
  73        WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
  74        STOP_POWER_ON,          /* just STOP */
  75        STOP_POWER_OFF,         /* STOP + SRPG */
  76};
  77
  78enum mx3_cpu_pwr_mode {
  79        MX3_RUN,
  80        MX3_WAIT,
  81        MX3_DOZE,
  82        MX3_SLEEP,
  83};
  84
  85void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
  86
  87void imx_enable_cpu(int cpu, bool enable);
  88void imx_set_cpu_jump(int cpu, void *jump_addr);
  89u32 imx_get_cpu_arg(int cpu);
  90void imx_set_cpu_arg(int cpu, u32 arg);
  91#ifdef CONFIG_SMP
  92void v7_secondary_startup(void);
  93void imx_scu_map_io(void);
  94void imx_smp_prepare(void);
  95#else
  96static inline void imx_scu_map_io(void) {}
  97static inline void imx_smp_prepare(void) {}
  98#endif
  99void imx_src_init(void);
 100void imx_gpc_pre_suspend(bool arm_power_off);
 101void imx_gpc_post_resume(void);
 102void imx_gpc_mask_all(void);
 103void imx_gpc_restore_all(void);
 104void imx_gpc_hwirq_mask(unsigned int hwirq);
 105void imx_gpc_hwirq_unmask(unsigned int hwirq);
 106void imx_anatop_init(void);
 107void imx_anatop_pre_suspend(void);
 108void imx_anatop_post_resume(void);
 109int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
 110void imx6q_set_int_mem_clk_lpm(bool enable);
 111void imx6sl_set_wait_clk(bool enter);
 112int imx_mmdc_get_ddr_type(void);
 113
 114void imx_cpu_die(unsigned int cpu);
 115int imx_cpu_kill(unsigned int cpu);
 116
 117#ifdef CONFIG_SUSPEND
 118void v7_cpu_resume(void);
 119void imx53_suspend(void __iomem *ocram_vbase);
 120extern const u32 imx53_suspend_sz;
 121void imx6_suspend(void __iomem *ocram_vbase);
 122#else
 123static inline void v7_cpu_resume(void) {}
 124static inline void imx53_suspend(void __iomem *ocram_vbase) {}
 125static const u32 imx53_suspend_sz;
 126static inline void imx6_suspend(void __iomem *ocram_vbase) {}
 127#endif
 128
 129void imx6_pm_ccm_init(const char *ccm_compat);
 130void imx6q_pm_init(void);
 131void imx6dl_pm_init(void);
 132void imx6sl_pm_init(void);
 133void imx6sx_pm_init(void);
 134
 135#ifdef CONFIG_PM
 136void imx51_pm_init(void);
 137void imx53_pm_init(void);
 138#else
 139static inline void imx51_pm_init(void) {}
 140static inline void imx53_pm_init(void) {}
 141#endif
 142
 143#ifdef CONFIG_NEON
 144int mx51_neon_fixup(void);
 145#else
 146static inline int mx51_neon_fixup(void) { return 0; }
 147#endif
 148
 149#ifdef CONFIG_CACHE_L2X0
 150void imx_init_l2cache(void);
 151#else
 152static inline void imx_init_l2cache(void) {}
 153#endif
 154
 155extern struct smp_operations imx_smp_ops;
 156extern struct smp_operations ls1021a_smp_ops;
 157
 158#endif
 159