LXR linux/arch/arm/mach-spear/spear3xx.c

   1/*
   2 * arch/arm/mach-spear3xx/spear3xx.c
   3 *
   4 * SPEAr3XX machines common source file
   5 *
   6 * Copyright (C) 2009-2012 ST Microelectronics
   7 * Viresh Kumar <vireshk@kernel.org>
   8 *
   9 * This file is licensed under the terms of the GNU General Public
  10 * License version 2. This program is licensed "as is" without any
  11 * warranty of any kind, whether express or implied.
  12 */
  13
  14#define pr_fmt(fmt) "SPEAr3xx: " fmt
  15
  16#include <linux/amba/pl022.h>
  17#include <linux/amba/pl080.h>
  18#include <linux/clk.h>
  19#include <linux/io.h>
  20#include <asm/mach/map.h>
  21#include "pl080.h"
  22#include "generic.h"
  23#include <mach/spear.h>
  24#include <mach/misc_regs.h>
  25
  26/* ssp device registration */
  27struct pl022_ssp_controller pl022_plat_data = {
  28        .bus_id = 0,
  29        .enable_dma = 1,
  30        .dma_filter = pl08x_filter_id,
  31        .dma_tx_param = "ssp0_tx",
  32        .dma_rx_param = "ssp0_rx",
  33        /*
  34         * This is number of spi devices that can be connected to spi. There are
  35         * two type of chipselects on which slave devices can work. One is chip
  36         * select provided by spi masters other is controlled through external
  37         * gpio's. We can't use chipselect provided from spi master (because as
  38         * soon as FIFO becomes empty, CS is disabled and transfer ends). So
  39         * this number now depends on number of gpios available for spi. each
  40         * slave on each master requires a separate gpio pin.
  41         */
  42        .num_chipselect = 2,
  43};
  44
  45/* dmac device registration */
  46struct pl08x_platform_data pl080_plat_data = {
  47        .memcpy_channel = {
  48                .bus_id = "memcpy",
  49                .cctl_memcpy =
  50                        (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
  51                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
  52                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
  53                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
  54                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
  55                        PL080_CONTROL_PROT_SYS),
  56        },
  57        .lli_buses = PL08X_AHB1,
  58        .mem_buses = PL08X_AHB1,
  59        .get_xfer_signal = pl080_get_signal,
  60        .put_xfer_signal = pl080_put_signal,
  61};
  62
  63/*
  64 * Following will create 16MB static virtual/physical mappings
  65 * PHYSICAL             VIRTUAL
  66 * 0xD0000000           0xFD000000
  67 * 0xFC000000           0xFC000000
  68 */
  69struct map_desc spear3xx_io_desc[] __initdata = {
  70        {
  71                .virtual        = (unsigned long)VA_SPEAR_ICM1_2_BASE,
  72                .pfn            = __phys_to_pfn(SPEAR_ICM1_2_BASE),
  73                .length         = SZ_16M,
  74                .type           = MT_DEVICE
  75        }, {
  76                .virtual        = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
  77                .pfn            = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
  78                .length         = SZ_16M,
  79                .type           = MT_DEVICE
  80        },
  81};
  82
  83/* This will create static memory mapping for selected devices */
  84void __init spear3xx_map_io(void)
  85{
  86        iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
  87}
  88
  89void __init spear3xx_timer_init(void)
  90{
  91        char pclk_name[] = "pll3_clk";
  92        struct clk *gpt_clk, *pclk;
  93
  94        spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE);
  95
  96        /* get the system timer clock */
  97        gpt_clk = clk_get_sys("gpt0", NULL);
  98        if (IS_ERR(gpt_clk)) {
  99                pr_err("%s:couldn't get clk for gpt\n", __func__);
 100                BUG();
 101        }
 102
 103        /* get the suitable parent clock for timer*/
 104        pclk = clk_get(NULL, pclk_name);
 105        if (IS_ERR(pclk)) {
 106                pr_err("%s:couldn't get %s as parent for gpt\n",
 107                                __func__, pclk_name);
 108                BUG();
 109        }
 110
 111        clk_set_parent(gpt_clk, pclk);
 112        clk_put(gpt_clk);
 113        clk_put(pclk);
 114
 115        spear_setup_of_timer();
 116}
 117