1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36#include <linux/device.h>
37#include <linux/platform_device.h>
38#include <linux/mtd/mtd.h>
39#include <linux/mtd/partitions.h>
40#include <linux/mtd/physmap.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/plat-ram.h>
43#include <linux/spi/spi.h>
44#include <linux/spi/flash.h>
45#include <linux/irq.h>
46#include <linux/interrupt.h>
47#include <linux/gpio.h>
48#include <linux/jiffies.h>
49#include <linux/i2c-pca-platform.h>
50#include <linux/delay.h>
51#include <linux/io.h>
52#include <asm/dma.h>
53#include <asm/bfin5xx_spi.h>
54#include <asm/portmux.h>
55#include <asm/dpmc.h>
56#include <asm/cacheflush.h>
57#include <linux/i2c.h>
58
59
60
61
62const char bfin_board_name[] = "Acvilon board";
63
64#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
65#include <linux/usb/isp1760.h>
66static struct resource bfin_isp1760_resources[] = {
67 [0] = {
68 .start = 0x20000000,
69 .end = 0x20000000 + 0x000fffff,
70 .flags = IORESOURCE_MEM,
71 },
72 [1] = {
73 .start = IRQ_PF15,
74 .end = IRQ_PF15,
75 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
76 },
77};
78
79static struct isp1760_platform_data isp1760_priv = {
80 .is_isp1761 = 0,
81 .port1_disable = 0,
82 .bus_width_16 = 1,
83 .port1_otg = 0,
84 .analog_oc = 0,
85 .dack_polarity_high = 0,
86 .dreq_polarity_high = 0,
87};
88
89static struct platform_device bfin_isp1760_device = {
90 .name = "isp1760-hcd",
91 .id = 0,
92 .dev = {
93 .platform_data = &isp1760_priv,
94 },
95 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
96 .resource = bfin_isp1760_resources,
97};
98#endif
99
100static struct resource bfin_i2c_pca_resources[] = {
101 {
102 .name = "pca9564-regs",
103 .start = 0x2C000000,
104 .end = 0x2C000000 + 16,
105 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
106 }, {
107
108 .start = IRQ_PF8,
109 .end = IRQ_PF8,
110 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
111 },
112};
113
114struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
115 .gpio = -1,
116 .i2c_clock_speed = 330000,
117 .timeout = HZ,
118};
119
120
121static struct platform_device bfin_i2c_pca_device = {
122 .name = "i2c-pca-platform",
123 .id = 0,
124 .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
125 .resource = bfin_i2c_pca_resources,
126 .dev = {
127 .platform_data = &pca9564_platform_data,
128 }
129};
130
131
132static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
133 {
134 I2C_BOARD_INFO("ds1339", 0x68),
135 },
136 {
137 I2C_BOARD_INFO("tcn75", 0x49),
138 },
139};
140
141#if IS_ENABLED(CONFIG_MTD_PLATRAM)
142static struct platdata_mtd_ram mtd_ram_data = {
143 .mapname = "rootfs(RAM)",
144 .bankwidth = 4,
145};
146
147static struct resource mtd_ram_resource = {
148 .start = 0x4000000,
149 .end = 0x5ffffff,
150 .flags = IORESOURCE_MEM,
151};
152
153static struct platform_device mtd_ram_device = {
154 .name = "mtd-ram",
155 .id = 0,
156 .dev = {
157 .platform_data = &mtd_ram_data,
158 },
159 .num_resources = 1,
160 .resource = &mtd_ram_resource,
161};
162#endif
163
164#if IS_ENABLED(CONFIG_SMSC911X)
165#include <linux/smsc911x.h>
166static struct resource smsc911x_resources[] = {
167 {
168 .name = "smsc911x-memory",
169 .start = 0x28000000,
170 .end = 0x28000000 + 0xFF,
171 .flags = IORESOURCE_MEM,
172 },
173 {
174 .start = IRQ_PF7,
175 .end = IRQ_PF7,
176 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
177 },
178};
179
180static struct smsc911x_platform_config smsc911x_config = {
181 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
182 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
183 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
184 .phy_interface = PHY_INTERFACE_MODE_MII,
185};
186
187static struct platform_device smsc911x_device = {
188 .name = "smsc911x",
189 .id = 0,
190 .num_resources = ARRAY_SIZE(smsc911x_resources),
191 .resource = smsc911x_resources,
192 .dev = {
193 .platform_data = &smsc911x_config,
194 },
195};
196#endif
197
198#if IS_ENABLED(CONFIG_SERIAL_BFIN)
199#ifdef CONFIG_SERIAL_BFIN_UART0
200static struct resource bfin_uart0_resources[] = {
201 {
202 .start = BFIN_UART_THR,
203 .end = BFIN_UART_GCTL + 2,
204 .flags = IORESOURCE_MEM,
205 },
206 {
207 .start = IRQ_UART_TX,
208 .end = IRQ_UART_TX,
209 .flags = IORESOURCE_IRQ,
210 },
211 {
212 .start = IRQ_UART_RX,
213 .end = IRQ_UART_RX,
214 .flags = IORESOURCE_IRQ,
215 },
216 {
217 .start = IRQ_UART_ERROR,
218 .end = IRQ_UART_ERROR,
219 .flags = IORESOURCE_IRQ,
220 },
221 {
222 .start = CH_UART_TX,
223 .end = CH_UART_TX,
224 .flags = IORESOURCE_DMA,
225 },
226 {
227 .start = CH_UART_RX,
228 .end = CH_UART_RX,
229 .flags = IORESOURCE_DMA,
230 },
231};
232
233static unsigned short bfin_uart0_peripherals[] = {
234 P_UART0_TX, P_UART0_RX, 0
235};
236
237static struct platform_device bfin_uart0_device = {
238 .name = "bfin-uart",
239 .id = 0,
240 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
241 .resource = bfin_uart0_resources,
242 .dev = {
243
244 .platform_data = &bfin_uart0_peripherals,
245 },
246};
247#endif
248#endif
249
250#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
251
252static struct mtd_partition bfin_plat_nand_partitions[] = {
253 {
254 .name = "params(nand)",
255 .size = 32 * 1024 * 1024,
256 .offset = 0,
257 }, {
258 .name = "userfs(nand)",
259 .size = MTDPART_SIZ_FULL,
260 .offset = MTDPART_OFS_APPEND,
261 },
262};
263
264#define BFIN_NAND_PLAT_CLE 2
265#define BFIN_NAND_PLAT_ALE 3
266
267static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
268 unsigned int ctrl)
269{
270 struct nand_chip *this = mtd->priv;
271
272 if (cmd == NAND_CMD_NONE)
273 return;
274
275 if (ctrl & NAND_CLE)
276 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
277 else
278 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
279}
280
281#define BFIN_NAND_PLAT_READY GPIO_PF10
282static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
283{
284 return gpio_get_value(BFIN_NAND_PLAT_READY);
285}
286
287static struct platform_nand_data bfin_plat_nand_data = {
288 .chip = {
289 .nr_chips = 1,
290 .chip_delay = 30,
291 .partitions = bfin_plat_nand_partitions,
292 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
293 },
294 .ctrl = {
295 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
296 .dev_ready = bfin_plat_nand_dev_ready,
297 },
298};
299
300#define MAX(x, y) (x > y ? x : y)
301static struct resource bfin_plat_nand_resources = {
302 .start = 0x24000000,
303 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
304 .flags = IORESOURCE_MEM,
305};
306
307static struct platform_device bfin_async_nand_device = {
308 .name = "gen_nand",
309 .id = -1,
310 .num_resources = 1,
311 .resource = &bfin_plat_nand_resources,
312 .dev = {
313 .platform_data = &bfin_plat_nand_data,
314 },
315};
316
317static void bfin_plat_nand_init(void)
318{
319 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
320}
321#else
322static void bfin_plat_nand_init(void)
323{
324}
325#endif
326
327#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
328static struct mtd_partition bfin_spi_dataflash_partitions[] = {
329 {
330 .name = "bootloader",
331 .size = 0x4200,
332 .offset = 0,
333 .mask_flags = MTD_CAP_ROM},
334 {
335 .name = "u-boot",
336 .size = 0x42000,
337 .offset = MTDPART_OFS_APPEND,
338 },
339 {
340 .name = "u-boot(params)",
341 .size = 0x4200,
342 .offset = MTDPART_OFS_APPEND,
343 },
344 {
345 .name = "kernel",
346 .size = 0x294000,
347 .offset = MTDPART_OFS_APPEND,
348 },
349 {
350 .name = "params",
351 .size = 0x42000,
352 .offset = MTDPART_OFS_APPEND,
353 },
354 {
355 .name = "rootfs",
356 .size = MTDPART_SIZ_FULL,
357 .offset = MTDPART_OFS_APPEND,
358 }
359};
360
361static struct flash_platform_data bfin_spi_dataflash_data = {
362 .name = "SPI Dataflash",
363 .parts = bfin_spi_dataflash_partitions,
364 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
365};
366
367
368static struct bfin5xx_spi_chip data_flash_chip_info = {
369 .enable_dma = 0,
370};
371#endif
372
373#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
374
375static struct resource bfin_spi0_resource[] = {
376 [0] = {
377 .start = SPI0_REGBASE,
378 .end = SPI0_REGBASE + 0xFF,
379 .flags = IORESOURCE_MEM,
380 },
381 [1] = {
382 .start = CH_SPI,
383 .end = CH_SPI,
384 .flags = IORESOURCE_DMA,
385 },
386 [2] = {
387 .start = IRQ_SPI,
388 .end = IRQ_SPI,
389 .flags = IORESOURCE_IRQ,
390 },
391};
392
393
394static struct bfin5xx_spi_master bfin_spi0_info = {
395 .num_chipselect = 8,
396 .enable_dma = 1,
397 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
398};
399
400static struct platform_device bfin_spi0_device = {
401 .name = "bfin-spi",
402 .id = 0,
403 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
404 .resource = bfin_spi0_resource,
405 .dev = {
406 .platform_data = &bfin_spi0_info,
407 },
408};
409#endif
410
411static struct spi_board_info bfin_spi_board_info[] __initdata = {
412#if IS_ENABLED(CONFIG_SPI_SPIDEV)
413 {
414 .modalias = "spidev",
415 .max_speed_hz = 3125000,
416 .bus_num = 0,
417 .chip_select = 3,
418 },
419#endif
420#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
421 {
422 .modalias = "mtd_dataflash",
423 .max_speed_hz = 33250000,
424 .bus_num = 0,
425 .chip_select = 2,
426 .platform_data = &bfin_spi_dataflash_data,
427 .controller_data = &data_flash_chip_info,
428 .mode = SPI_MODE_3,
429 },
430#endif
431};
432
433static struct resource bfin_gpios_resources = {
434 .start = 31,
435
436 .end = 32,
437 .flags = IORESOURCE_IRQ,
438};
439
440static struct platform_device bfin_gpios_device = {
441 .name = "simple-gpio",
442 .id = -1,
443 .num_resources = 1,
444 .resource = &bfin_gpios_resources,
445};
446
447static const unsigned int cclk_vlev_datasheet[] = {
448 VRPAIR(VLEV_085, 250000000),
449 VRPAIR(VLEV_090, 300000000),
450 VRPAIR(VLEV_095, 313000000),
451 VRPAIR(VLEV_100, 350000000),
452 VRPAIR(VLEV_105, 400000000),
453 VRPAIR(VLEV_110, 444000000),
454 VRPAIR(VLEV_115, 450000000),
455 VRPAIR(VLEV_120, 475000000),
456 VRPAIR(VLEV_125, 500000000),
457 VRPAIR(VLEV_130, 600000000),
458};
459
460static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
461 .tuple_tab = cclk_vlev_datasheet,
462 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
463 .vr_settling_time = 25 ,
464};
465
466static struct platform_device bfin_dpmc = {
467 .name = "bfin dpmc",
468 .dev = {
469 .platform_data = &bfin_dmpc_vreg_data,
470 },
471};
472
473static struct platform_device *acvilon_devices[] __initdata = {
474 &bfin_dpmc,
475
476#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
477 &bfin_spi0_device,
478#endif
479
480#if IS_ENABLED(CONFIG_SERIAL_BFIN)
481#ifdef CONFIG_SERIAL_BFIN_UART0
482 &bfin_uart0_device,
483#endif
484#endif
485
486 &bfin_gpios_device,
487
488#if IS_ENABLED(CONFIG_SMSC911X)
489 &smsc911x_device,
490#endif
491
492 &bfin_i2c_pca_device,
493
494#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
495 &bfin_async_nand_device,
496#endif
497
498#if IS_ENABLED(CONFIG_MTD_PLATRAM)
499 &mtd_ram_device,
500#endif
501
502};
503
504static int __init acvilon_init(void)
505{
506 int ret;
507
508 printk(KERN_INFO "%s(): registering device resources\n", __func__);
509
510 bfin_plat_nand_init();
511 ret =
512 platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
513 if (ret < 0)
514 return ret;
515
516 i2c_register_board_info(0, acvilon_i2c_devs,
517 ARRAY_SIZE(acvilon_i2c_devs));
518
519 bfin_write_FIO0_FLAG_C(1 << 14);
520 msleep(5);
521 bfin_write_FIO0_FLAG_S(1 << 14);
522
523 spi_register_board_info(bfin_spi_board_info,
524 ARRAY_SIZE(bfin_spi_board_info));
525 return 0;
526}
527
528arch_initcall(acvilon_init);
529
530static struct platform_device *acvilon_early_devices[] __initdata = {
531#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
532#ifdef CONFIG_SERIAL_BFIN_UART0
533 &bfin_uart0_device,
534#endif
535#endif
536};
537
538void __init native_machine_early_platform_add_devices(void)
539{
540 printk(KERN_INFO "register early platform devices\n");
541 early_platform_add_devices(acvilon_early_devices,
542 ARRAY_SIZE(acvilon_early_devices));
543}
544
