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29#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/of_platform.h>
32#include <linux/module.h>
33#include <linux/io.h>
34#include <linux/delay.h>
35#include <asm/soc.h>
36#include <asm/dscr.h>
37
38#define MAX_DEVSTATE_IDS 32
39#define MAX_DEVCTL_REGS 8
40#define MAX_DEVSTAT_REGS 8
41#define MAX_LOCKED_REGS 4
42#define MAX_SOC_EMACS 2
43
44struct rmii_reset_reg {
45 u32 reg;
46 u32 mask;
47};
48
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52
53struct locked_reg {
54 u32 reg;
55 u32 lockreg;
56 u32 key;
57};
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64
65
66struct devstate_ctl_reg {
67 u32 reg;
68 u8 start_id;
69 u8 num_ids;
70 u8 enable_only;
71 u8 enable;
72 u8 disable;
73 u8 shift;
74 u8 nbits;
75};
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84
85struct devstate_stat_reg {
86 u32 reg;
87 u8 start_id;
88 u8 num_ids;
89 u8 enable;
90 u8 disable;
91 u8 shift;
92 u8 nbits;
93};
94
95struct devstate_info {
96 struct devstate_ctl_reg *ctl;
97 struct devstate_stat_reg *stat;
98};
99
100
101struct dscr_ops {
102 void (*init)(struct device_node *node);
103};
104
105struct dscr_regs {
106 spinlock_t lock;
107 void __iomem *base;
108 u32 kick_reg[2];
109 u32 kick_key[2];
110 struct locked_reg locked[MAX_LOCKED_REGS];
111 struct devstate_info devstate_info[MAX_DEVSTATE_IDS];
112 struct rmii_reset_reg rmii_resets[MAX_SOC_EMACS];
113 struct devstate_ctl_reg devctl[MAX_DEVCTL_REGS];
114 struct devstate_stat_reg devstat[MAX_DEVSTAT_REGS];
115};
116
117static struct dscr_regs dscr;
118
119static struct locked_reg *find_locked_reg(u32 reg)
120{
121 int i;
122
123 for (i = 0; i < MAX_LOCKED_REGS; i++)
124 if (dscr.locked[i].key && reg == dscr.locked[i].reg)
125 return &dscr.locked[i];
126 return NULL;
127}
128
129
130
131
132static void dscr_write_locked1(u32 reg, u32 val,
133 u32 lock, u32 key)
134{
135 void __iomem *reg_addr = dscr.base + reg;
136 void __iomem *lock_addr = dscr.base + lock;
137
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142
143
144 asm volatile ("b .s2 0f\n"
145 "nop 5\n"
146 " .align 5\n"
147 "0:\n"
148 "stw .D1T2 %3,*%2\n"
149 "stw .D1T2 %1,*%0\n"
150 :
151 : "a"(reg_addr), "b"(val), "a"(lock_addr), "b"(key)
152 );
153
154
155 soc_writel(0, lock_addr);
156}
157
158
159
160
161static void dscr_write_locked2(u32 reg, u32 val,
162 u32 lock0, u32 key0,
163 u32 lock1, u32 key1)
164{
165 soc_writel(key0, dscr.base + lock0);
166 soc_writel(key1, dscr.base + lock1);
167 soc_writel(val, dscr.base + reg);
168 soc_writel(0, dscr.base + lock0);
169 soc_writel(0, dscr.base + lock1);
170}
171
172static void dscr_write(u32 reg, u32 val)
173{
174 struct locked_reg *lock;
175
176 lock = find_locked_reg(reg);
177 if (lock)
178 dscr_write_locked1(reg, val, lock->lockreg, lock->key);
179 else if (dscr.kick_key[0])
180 dscr_write_locked2(reg, val, dscr.kick_reg[0], dscr.kick_key[0],
181 dscr.kick_reg[1], dscr.kick_key[1]);
182 else
183 soc_writel(val, dscr.base + reg);
184}
185
186
187
188
189
190void dscr_set_devstate(int id, enum dscr_devstate_t state)
191{
192 struct devstate_ctl_reg *ctl;
193 struct devstate_stat_reg *stat;
194 struct devstate_info *info;
195 u32 ctl_val, val;
196 int ctl_shift, ctl_mask;
197 unsigned long flags;
198
199 if (!dscr.base)
200 return;
201
202 if (id < 0 || id >= MAX_DEVSTATE_IDS)
203 return;
204
205 info = &dscr.devstate_info[id];
206 ctl = info->ctl;
207 stat = info->stat;
208
209 if (ctl == NULL)
210 return;
211
212 ctl_shift = ctl->shift + ctl->nbits * (id - ctl->start_id);
213 ctl_mask = ((1 << ctl->nbits) - 1) << ctl_shift;
214
215 switch (state) {
216 case DSCR_DEVSTATE_ENABLED:
217 ctl_val = ctl->enable << ctl_shift;
218 break;
219 case DSCR_DEVSTATE_DISABLED:
220 if (ctl->enable_only)
221 return;
222 ctl_val = ctl->disable << ctl_shift;
223 break;
224 default:
225 return;
226 }
227
228 spin_lock_irqsave(&dscr.lock, flags);
229
230 val = soc_readl(dscr.base + ctl->reg);
231 val &= ~ctl_mask;
232 val |= ctl_val;
233
234 dscr_write(ctl->reg, val);
235
236 spin_unlock_irqrestore(&dscr.lock, flags);
237
238 if (!stat)
239 return;
240
241 ctl_shift = stat->shift + stat->nbits * (id - stat->start_id);
242
243 if (state == DSCR_DEVSTATE_ENABLED)
244 ctl_val = stat->enable;
245 else
246 ctl_val = stat->disable;
247
248 do {
249 val = soc_readl(dscr.base + stat->reg);
250 val >>= ctl_shift;
251 val &= ((1 << stat->nbits) - 1);
252 } while (val != ctl_val);
253}
254EXPORT_SYMBOL(dscr_set_devstate);
255
256
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258
259void dscr_rmii_reset(int id, int assert)
260{
261 struct rmii_reset_reg *r;
262 unsigned long flags;
263 u32 val;
264
265 if (id < 0 || id >= MAX_SOC_EMACS)
266 return;
267
268 r = &dscr.rmii_resets[id];
269 if (r->mask == 0)
270 return;
271
272 spin_lock_irqsave(&dscr.lock, flags);
273
274 val = soc_readl(dscr.base + r->reg);
275 if (assert)
276 dscr_write(r->reg, val | r->mask);
277 else
278 dscr_write(r->reg, val & ~(r->mask));
279
280 spin_unlock_irqrestore(&dscr.lock, flags);
281}
282EXPORT_SYMBOL(dscr_rmii_reset);
283
284static void __init dscr_parse_devstat(struct device_node *node,
285 void __iomem *base)
286{
287 u32 val;
288 int err;
289
290 err = of_property_read_u32_array(node, "ti,dscr-devstat", &val, 1);
291 if (!err)
292 c6x_devstat = soc_readl(base + val);
293 printk(KERN_INFO "DEVSTAT: %08x\n", c6x_devstat);
294}
295
296static void __init dscr_parse_silicon_rev(struct device_node *node,
297 void __iomem *base)
298{
299 u32 vals[3];
300 int err;
301
302 err = of_property_read_u32_array(node, "ti,dscr-silicon-rev", vals, 3);
303 if (!err) {
304 c6x_silicon_rev = soc_readl(base + vals[0]);
305 c6x_silicon_rev >>= vals[1];
306 c6x_silicon_rev &= vals[2];
307 }
308}
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327static void __init dscr_parse_mac_fuse(struct device_node *node,
328 void __iomem *base)
329{
330 u32 vals[10], fuse;
331 int f, i, j, err;
332
333 err = of_property_read_u32_array(node, "ti,dscr-mac-fuse-regs",
334 vals, 10);
335 if (err)
336 return;
337
338 for (f = 0; f < 2; f++) {
339 fuse = soc_readl(base + vals[f * 5]);
340 for (j = (f * 5) + 1, i = 24; i >= 0; i -= 8, j++)
341 if (vals[j] && vals[j] <= 6)
342 c6x_fuse_mac[vals[j] - 1] = fuse >> i;
343 }
344}
345
346static void __init dscr_parse_rmii_resets(struct device_node *node,
347 void __iomem *base)
348{
349 const __be32 *p;
350 int i, size;
351
352
353 p = of_get_property(node, "ti,dscr-rmii-resets", &size);
354 if (p) {
355
356 size /= (sizeof(*p) * 2);
357 if (size > MAX_SOC_EMACS)
358 size = MAX_SOC_EMACS;
359
360 for (i = 0; i < size; i++) {
361 dscr.rmii_resets[i].reg = be32_to_cpup(p++);
362 dscr.rmii_resets[i].mask = be32_to_cpup(p++);
363 }
364 }
365}
366
367
368static void __init dscr_parse_privperm(struct device_node *node,
369 void __iomem *base)
370{
371 u32 vals[2];
372 int err;
373
374 err = of_property_read_u32_array(node, "ti,dscr-privperm", vals, 2);
375 if (err)
376 return;
377 dscr_write(vals[0], vals[1]);
378}
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396static void __init dscr_parse_locked_regs(struct device_node *node,
397 void __iomem *base)
398{
399 struct locked_reg *r;
400 const __be32 *p;
401 int i, size;
402
403 p = of_get_property(node, "ti,dscr-locked-regs", &size);
404 if (p) {
405
406 size /= (sizeof(*p) * 3);
407 if (size > MAX_LOCKED_REGS)
408 size = MAX_LOCKED_REGS;
409
410 for (i = 0; i < size; i++) {
411 r = &dscr.locked[i];
412
413 r->reg = be32_to_cpup(p++);
414 r->lockreg = be32_to_cpup(p++);
415 r->key = be32_to_cpup(p++);
416 }
417 }
418}
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431static void __init dscr_parse_kick_regs(struct device_node *node,
432 void __iomem *base)
433{
434 u32 vals[4];
435 int err;
436
437 err = of_property_read_u32_array(node, "ti,dscr-kick-regs", vals, 4);
438 if (!err) {
439 dscr.kick_reg[0] = vals[0];
440 dscr.kick_key[0] = vals[1];
441 dscr.kick_reg[1] = vals[2];
442 dscr.kick_key[1] = vals[3];
443 }
444}
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469static void __init dscr_parse_devstate_ctl_regs(struct device_node *node,
470 void __iomem *base)
471{
472 struct devstate_ctl_reg *r;
473 const __be32 *p;
474 int i, j, size;
475
476 p = of_get_property(node, "ti,dscr-devstate-ctl-regs", &size);
477 if (p) {
478
479 size /= (sizeof(*p) * 7);
480 if (size > MAX_DEVCTL_REGS)
481 size = MAX_DEVCTL_REGS;
482
483 for (i = 0; i < size; i++) {
484 r = &dscr.devctl[i];
485
486 r->start_id = be32_to_cpup(p++);
487 r->num_ids = be32_to_cpup(p++);
488 r->reg = be32_to_cpup(p++);
489 r->enable = be32_to_cpup(p++);
490 r->disable = be32_to_cpup(p++);
491 if (r->disable == 0xffffffff)
492 r->enable_only = 1;
493 r->shift = be32_to_cpup(p++);
494 r->nbits = be32_to_cpup(p++);
495
496 for (j = r->start_id;
497 j < (r->start_id + r->num_ids);
498 j++)
499 dscr.devstate_info[j].ctl = r;
500 }
501 }
502}
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525static void __init dscr_parse_devstate_stat_regs(struct device_node *node,
526 void __iomem *base)
527{
528 struct devstate_stat_reg *r;
529 const __be32 *p;
530 int i, j, size;
531
532 p = of_get_property(node, "ti,dscr-devstate-stat-regs", &size);
533 if (p) {
534
535 size /= (sizeof(*p) * 7);
536 if (size > MAX_DEVSTAT_REGS)
537 size = MAX_DEVSTAT_REGS;
538
539 for (i = 0; i < size; i++) {
540 r = &dscr.devstat[i];
541
542 r->start_id = be32_to_cpup(p++);
543 r->num_ids = be32_to_cpup(p++);
544 r->reg = be32_to_cpup(p++);
545 r->enable = be32_to_cpup(p++);
546 r->disable = be32_to_cpup(p++);
547 r->shift = be32_to_cpup(p++);
548 r->nbits = be32_to_cpup(p++);
549
550 for (j = r->start_id;
551 j < (r->start_id + r->num_ids);
552 j++)
553 dscr.devstate_info[j].stat = r;
554 }
555 }
556}
557
558static struct of_device_id dscr_ids[] __initdata = {
559 { .compatible = "ti,c64x+dscr" },
560 {}
561};
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569
570void __init dscr_probe(void)
571{
572 struct device_node *node;
573 void __iomem *base;
574
575 spin_lock_init(&dscr.lock);
576
577 node = of_find_matching_node(NULL, dscr_ids);
578 if (!node)
579 return;
580
581 base = of_iomap(node, 0);
582 if (!base) {
583 of_node_put(node);
584 return;
585 }
586
587 dscr.base = base;
588
589 dscr_parse_devstat(node, base);
590 dscr_parse_silicon_rev(node, base);
591 dscr_parse_mac_fuse(node, base);
592 dscr_parse_rmii_resets(node, base);
593 dscr_parse_locked_regs(node, base);
594 dscr_parse_kick_regs(node, base);
595 dscr_parse_devstate_ctl_regs(node, base);
596 dscr_parse_devstate_stat_regs(node, base);
597 dscr_parse_privperm(node, base);
598}
599