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28#ifndef __CVMX_H__
29#define __CVMX_H__
30
31#include <linux/kernel.h>
32#include <linux/string.h>
33
34enum cvmx_mips_space {
35 CVMX_MIPS_SPACE_XKSEG = 3LL,
36 CVMX_MIPS_SPACE_XKPHYS = 2LL,
37 CVMX_MIPS_SPACE_XSSEG = 1LL,
38 CVMX_MIPS_SPACE_XUSEG = 0LL
39};
40
41
42#define CVMX_MIPS32_SPACE_KSEG0 1l
43#define CVMX_ADD_SEG32(segment, add) \
44 (((int32_t)segment << 31) | (int32_t)(add))
45
46#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
47
48
49#define CVMX_ADD_SEG(segment, add) \
50 ((((uint64_t)segment) << 62) | (add))
51#ifndef CVMX_ADD_IO_SEG
52#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
53#endif
54
55#include <asm/octeon/cvmx-asm.h>
56#include <asm/octeon/cvmx-packet.h>
57#include <asm/octeon/cvmx-sysinfo.h>
58
59#include <asm/octeon/cvmx-ciu-defs.h>
60#include <asm/octeon/cvmx-gpio-defs.h>
61#include <asm/octeon/cvmx-iob-defs.h>
62#include <asm/octeon/cvmx-ipd-defs.h>
63#include <asm/octeon/cvmx-l2c-defs.h>
64#include <asm/octeon/cvmx-l2d-defs.h>
65#include <asm/octeon/cvmx-l2t-defs.h>
66#include <asm/octeon/cvmx-led-defs.h>
67#include <asm/octeon/cvmx-mio-defs.h>
68#include <asm/octeon/cvmx-pow-defs.h>
69
70#include <asm/octeon/cvmx-bootinfo.h>
71#include <asm/octeon/cvmx-bootmem.h>
72#include <asm/octeon/cvmx-l2c.h>
73
74#ifndef CVMX_ENABLE_DEBUG_PRINTS
75#define CVMX_ENABLE_DEBUG_PRINTS 1
76#endif
77
78#if CVMX_ENABLE_DEBUG_PRINTS
79#define cvmx_dprintf printk
80#else
81#define cvmx_dprintf(...) {}
82#endif
83
84#define CVMX_MAX_CORES (16)
85#define CVMX_CACHE_LINE_SIZE (128)
86#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1)
87#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
88#define CAST64(v) ((long long)(long)(v))
89#define CASTPTR(type, v) ((type *)(long)(v))
90
91
92
93
94
95static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
96static inline uint32_t cvmx_get_proc_id(void)
97{
98 uint32_t id;
99 asm("mfc0 %0, $15,0" : "=r"(id));
100 return id;
101}
102
103
104#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
105#define CVMX_TMP_STR2(x) #x
106
107
108
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110
111
112 static inline uint64_t cvmx_build_mask(uint64_t bits)
113{
114 return ~((~0x0ull) << bits);
115}
116
117
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122
123
124static inline uint64_t cvmx_build_io_address(uint64_t major_did,
125 uint64_t sub_did)
126{
127 return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
128}
129
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146
147static inline uint64_t cvmx_build_bits(uint64_t high_bit,
148 uint64_t low_bit, uint64_t value)
149{
150 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
151}
152
153
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159
160
161static inline uint64_t cvmx_ptr_to_phys(void *ptr)
162{
163 if (sizeof(void *) == 8) {
164
165
166
167
168
169
170
171
172 if ((CAST64(ptr) >> 62) == 3)
173 return CAST64(ptr) & cvmx_build_mask(30);
174 else
175 return CAST64(ptr) & cvmx_build_mask(40);
176 } else {
177 return (long)(ptr) & 0x1fffffff;
178 }
179}
180
181
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183
184
185
186
187
188
189static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
190{
191 if (sizeof(void *) == 8) {
192
193 return CASTPTR(void,
194 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
195 physical_address));
196 } else {
197 return CASTPTR(void,
198 CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
199 physical_address));
200 }
201}
202
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209
210#define CVMX_BUILD_WRITE64(TYPE, ST) \
211static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
212{ \
213 *CASTPTR(volatile TYPE##_t, addr) = val; \
214}
215
216
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221
222
223
224#define CVMX_BUILD_READ64(TYPE, LT) \
225static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
226{ \
227 return *CASTPTR(volatile TYPE##_t, addr); \
228}
229
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236
237CVMX_BUILD_WRITE64(int64, "sd");
238CVMX_BUILD_WRITE64(int32, "sw");
239CVMX_BUILD_WRITE64(int16, "sh");
240CVMX_BUILD_WRITE64(int8, "sb");
241CVMX_BUILD_WRITE64(uint64, "sd");
242CVMX_BUILD_WRITE64(uint32, "sw");
243CVMX_BUILD_WRITE64(uint16, "sh");
244CVMX_BUILD_WRITE64(uint8, "sb");
245#define cvmx_write64 cvmx_write64_uint64
246
247
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249
250
251
252
253CVMX_BUILD_READ64(int64, "ld");
254CVMX_BUILD_READ64(int32, "lw");
255CVMX_BUILD_READ64(int16, "lh");
256CVMX_BUILD_READ64(int8, "lb");
257CVMX_BUILD_READ64(uint64, "ld");
258CVMX_BUILD_READ64(uint32, "lw");
259CVMX_BUILD_READ64(uint16, "lhu");
260CVMX_BUILD_READ64(uint8, "lbu");
261#define cvmx_read64 cvmx_read64_uint64
262
263
264static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
265{
266 cvmx_write64(csr_addr, val);
267
268
269
270
271
272
273
274 if (((csr_addr >> 40) & 0x7ffff) == (0x118))
275 cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
276}
277
278static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
279{
280 cvmx_write64(io_addr, val);
281
282}
283
284static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
285{
286 uint64_t val = cvmx_read64(csr_addr);
287 return val;
288}
289
290
291static inline void cvmx_send_single(uint64_t data)
292{
293 const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
294 cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
295}
296
297static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
298{
299 union {
300 uint64_t u64;
301 struct {
302 uint64_t scraddr:8;
303 uint64_t len:8;
304 uint64_t addr:48;
305 } s;
306 } addr;
307 addr.u64 = csr_addr;
308 addr.s.scraddr = scraddr >> 3;
309 addr.s.len = 1;
310 cvmx_send_single(addr.u64);
311}
312
313
314static inline int cvmx_octeon_is_pass1(void)
315{
316#if OCTEON_IS_COMMON_BINARY()
317 return 0;
318#else
319
320#if OCTEON_IS_MODEL(OCTEON_CN38XX)
321 return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
322#else
323 return 0;
324#endif
325#endif
326}
327
328static inline unsigned int cvmx_get_core_num(void)
329{
330 unsigned int core_num;
331 CVMX_RDHWRNV(core_num, 0);
332 return core_num;
333}
334
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341
342
343static inline uint32_t cvmx_pop(uint32_t val)
344{
345 uint32_t pop;
346 CVMX_POP(pop, val);
347 return pop;
348}
349
350
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353
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355
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357
358static inline int cvmx_dpop(uint64_t val)
359{
360 int pop;
361 CVMX_DPOP(pop, val);
362 return pop;
363}
364
365
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368
369
370
371static inline uint64_t cvmx_get_cycle(void)
372{
373 uint64_t cycle;
374 CVMX_RDHWR(cycle, 31);
375 return cycle;
376}
377
378
379
380
381
382static inline void cvmx_wait(uint64_t cycles)
383{
384 uint64_t done = cvmx_get_cycle() + cycles;
385
386 while (cvmx_get_cycle() < done)
387 ;
388}
389
390
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396
397static inline uint64_t cvmx_get_cycle_global(void)
398{
399 if (cvmx_octeon_is_pass1())
400 return 0;
401 else
402 return cvmx_read64(CVMX_IPD_CLK_COUNT);
403}
404
405
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411
412
413
414#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
415 ( \
416{ \
417 int result; \
418 do { \
419 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
420 cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
421 type c; \
422 while (1) { \
423 c.u64 = cvmx_read_csr(address); \
424 if ((c.s.field) op(value)) { \
425 result = 0; \
426 break; \
427 } else if (cvmx_get_cycle() > done) { \
428 result = -1; \
429 break; \
430 } else \
431 cvmx_wait(100); \
432 } \
433 } while (0); \
434 result; \
435})
436
437
438
439
440static inline uint32_t cvmx_octeon_num_cores(void)
441{
442 uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
443 return cvmx_pop(ciu_fuse);
444}
445
446#endif
447