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17#include <linux/kernel.h>
18#include <linux/export.h>
19#include <linux/init.h>
20#include <linux/ctype.h>
21#include <linux/string.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/nand.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26#include <linux/gpio_keys.h>
27#include <linux/input.h>
28#include <linux/serial_8250.h>
29
30#include <asm/bootinfo.h>
31
32#include <asm/mach-rc32434/rc32434.h>
33#include <asm/mach-rc32434/dma.h>
34#include <asm/mach-rc32434/dma_v.h>
35#include <asm/mach-rc32434/eth.h>
36#include <asm/mach-rc32434/rb.h>
37#include <asm/mach-rc32434/integ.h>
38#include <asm/mach-rc32434/gpio.h>
39#include <asm/mach-rc32434/irq.h>
40
41#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
42#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
43
44extern unsigned int idt_cpu_freq;
45
46static struct mpmc_device dev3;
47
48void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
49{
50 unsigned long flags;
51
52 spin_lock_irqsave(&dev3.lock, flags);
53
54 dev3.state = (dev3.state | or_mask) & ~nand_mask;
55 writeb(dev3.state, dev3.base);
56
57 spin_unlock_irqrestore(&dev3.lock, flags);
58}
59EXPORT_SYMBOL(set_latch_u5);
60
61unsigned char get_latch_u5(void)
62{
63 return dev3.state;
64}
65EXPORT_SYMBOL(get_latch_u5);
66
67static struct resource korina_dev0_res[] = {
68 {
69 .name = "korina_regs",
70 .start = ETH0_BASE_ADDR,
71 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
72 .flags = IORESOURCE_MEM,
73 }, {
74 .name = "korina_rx",
75 .start = ETH0_DMA_RX_IRQ,
76 .end = ETH0_DMA_RX_IRQ,
77 .flags = IORESOURCE_IRQ
78 }, {
79 .name = "korina_tx",
80 .start = ETH0_DMA_TX_IRQ,
81 .end = ETH0_DMA_TX_IRQ,
82 .flags = IORESOURCE_IRQ
83 }, {
84 .name = "korina_ovr",
85 .start = ETH0_RX_OVR_IRQ,
86 .end = ETH0_RX_OVR_IRQ,
87 .flags = IORESOURCE_IRQ
88 }, {
89 .name = "korina_und",
90 .start = ETH0_TX_UND_IRQ,
91 .end = ETH0_TX_UND_IRQ,
92 .flags = IORESOURCE_IRQ
93 }, {
94 .name = "korina_dma_rx",
95 .start = ETH0_RX_DMA_ADDR,
96 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
97 .flags = IORESOURCE_MEM,
98 }, {
99 .name = "korina_dma_tx",
100 .start = ETH0_TX_DMA_ADDR,
101 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
102 .flags = IORESOURCE_MEM,
103 }
104};
105
106static struct korina_device korina_dev0_data = {
107 .name = "korina0",
108 .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
109};
110
111static struct platform_device korina_dev0 = {
112 .id = -1,
113 .name = "korina",
114 .resource = korina_dev0_res,
115 .num_resources = ARRAY_SIZE(korina_dev0_res),
116};
117
118static struct resource cf_slot0_res[] = {
119 {
120 .name = "cf_membase",
121 .flags = IORESOURCE_MEM
122 }, {
123 .name = "cf_irq",
124 .start = (8 + 4 * 32 + CF_GPIO_NUM),
125 .end = (8 + 4 * 32 + CF_GPIO_NUM),
126 .flags = IORESOURCE_IRQ
127 }
128};
129
130static struct cf_device cf_slot0_data = {
131 .gpio_pin = CF_GPIO_NUM
132};
133
134static struct platform_device cf_slot0 = {
135 .id = -1,
136 .name = "pata-rb532-cf",
137 .dev.platform_data = &cf_slot0_data,
138 .resource = cf_slot0_res,
139 .num_resources = ARRAY_SIZE(cf_slot0_res),
140};
141
142
143static int rb532_dev_ready(struct mtd_info *mtd)
144{
145 return gpio_get_value(GPIO_RDY);
146}
147
148static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
149{
150 struct nand_chip *chip = mtd->priv;
151 unsigned char orbits, nandbits;
152
153 if (ctrl & NAND_CTRL_CHANGE) {
154 orbits = (ctrl & NAND_CLE) << 1;
155 orbits |= (ctrl & NAND_ALE) >> 1;
156
157 nandbits = (~ctrl & NAND_CLE) << 1;
158 nandbits |= (~ctrl & NAND_ALE) >> 1;
159
160 set_latch_u5(orbits, nandbits);
161 }
162 if (cmd != NAND_CMD_NONE)
163 writeb(cmd, chip->IO_ADDR_W);
164}
165
166static struct resource nand_slot0_res[] = {
167 [0] = {
168 .name = "nand_membase",
169 .flags = IORESOURCE_MEM
170 }
171};
172
173static struct platform_nand_data rb532_nand_data = {
174 .ctrl.dev_ready = rb532_dev_ready,
175 .ctrl.cmd_ctrl = rb532_cmd_ctrl,
176};
177
178static struct platform_device nand_slot0 = {
179 .name = "gen_nand",
180 .id = -1,
181 .resource = nand_slot0_res,
182 .num_resources = ARRAY_SIZE(nand_slot0_res),
183 .dev.platform_data = &rb532_nand_data,
184};
185
186static struct mtd_partition rb532_partition_info[] = {
187 {
188 .name = "Routerboard NAND boot",
189 .offset = 0,
190 .size = 4 * 1024 * 1024,
191 }, {
192 .name = "rootfs",
193 .offset = MTDPART_OFS_NXTBLK,
194 .size = MTDPART_SIZ_FULL,
195 }
196};
197
198static struct platform_device rb532_led = {
199 .name = "rb532-led",
200 .id = -1,
201};
202
203static struct platform_device rb532_button = {
204 .name = "rb532-button",
205 .id = -1,
206};
207
208static struct resource rb532_wdt_res[] = {
209 {
210 .name = "rb532_wdt_res",
211 .start = INTEG0_BASE_ADDR,
212 .end = INTEG0_BASE_ADDR + sizeof(struct integ),
213 .flags = IORESOURCE_MEM,
214 }
215};
216
217static struct platform_device rb532_wdt = {
218 .name = "rc32434_wdt",
219 .id = -1,
220 .resource = rb532_wdt_res,
221 .num_resources = ARRAY_SIZE(rb532_wdt_res),
222};
223
224static struct plat_serial8250_port rb532_uart_res[] = {
225 {
226 .type = PORT_16550A,
227 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
228 .irq = UART0_IRQ,
229 .regshift = 2,
230 .iotype = UPIO_MEM,
231 .flags = UPF_BOOT_AUTOCONF,
232 },
233 {
234 .flags = 0,
235 }
236};
237
238static struct platform_device rb532_uart = {
239 .name = "serial8250",
240 .id = PLAT8250_DEV_PLATFORM,
241 .dev.platform_data = &rb532_uart_res,
242};
243
244static struct platform_device *rb532_devs[] = {
245 &korina_dev0,
246 &nand_slot0,
247 &cf_slot0,
248 &rb532_led,
249 &rb532_button,
250 &rb532_uart,
251 &rb532_wdt
252};
253
254
255#define NAND_CHIP_DELAY 25
256
257static void __init rb532_nand_setup(void)
258{
259 switch (mips_machtype) {
260 case MACH_MIKROTIK_RB532A:
261 set_latch_u5(LO_FOFF | LO_CEX,
262 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
263 break;
264 default:
265 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
266 LO_ULED | LO_ALE | LO_CLE);
267 break;
268 }
269
270
271 rb532_nand_data.chip.nr_chips = 1;
272 rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
273 rb532_nand_data.chip.partitions = rb532_partition_info;
274 rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
275}
276
277
278static int __init plat_setup_devices(void)
279{
280
281 if (!readl(IDT434_REG_BASE + DEV1MASK))
282 rb532_devs[2] = NULL;
283 else {
284 cf_slot0_res[0].start =
285 readl(IDT434_REG_BASE + DEV1BASE);
286 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
287 }
288
289
290 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
291 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
292
293
294 dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
295
296 if (!dev3.base) {
297 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
298 return -ENXIO;
299 }
300
301
302 rb532_nand_setup();
303
304
305 rb532_uart_res[0].uartclk = idt_cpu_freq;
306
307 dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
308
309 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
310}
311
312static int __init setup_kmac(char *s)
313{
314 printk(KERN_INFO "korina mac = %s\n", s);
315 if (!mac_pton(s, korina_dev0_data.mac)) {
316 printk(KERN_ERR "Invalid mac\n");
317 return -EINVAL;
318 }
319 return 0;
320}
321
322__setup("kmac=", setup_kmac);
323
324arch_initcall(plat_setup_devices);
325
