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13#include <linux/bsearch.h>
14#include <linux/device.h>
15#include <linux/export.h>
16#include <linux/slab.h>
17#include <linux/sort.h>
18
19#include "trace.h"
20#include "internal.h"
21
22static const struct regcache_ops *cache_types[] = {
23 ®cache_rbtree_ops,
24 ®cache_lzo_ops,
25 ®cache_flat_ops,
26};
27
28static int regcache_hw_init(struct regmap *map)
29{
30 int i, j;
31 int ret;
32 int count;
33 unsigned int val;
34 void *tmp_buf;
35
36 if (!map->num_reg_defaults_raw)
37 return -EINVAL;
38
39
40 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
41 if (!regmap_volatile(map, i * map->reg_stride))
42 count++;
43
44
45 if (!count) {
46 map->cache_bypass = true;
47 return 0;
48 }
49
50 map->num_reg_defaults = count;
51 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
52 GFP_KERNEL);
53 if (!map->reg_defaults)
54 return -ENOMEM;
55
56 if (!map->reg_defaults_raw) {
57 u32 cache_bypass = map->cache_bypass;
58 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
59
60
61 map->cache_bypass = 1;
62 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
63 if (!tmp_buf) {
64 ret = -ENOMEM;
65 goto err_free;
66 }
67 ret = regmap_raw_read(map, 0, tmp_buf,
68 map->num_reg_defaults_raw);
69 map->cache_bypass = cache_bypass;
70 if (ret < 0)
71 goto err_cache_free;
72
73 map->reg_defaults_raw = tmp_buf;
74 map->cache_free = 1;
75 }
76
77
78 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
79 if (regmap_volatile(map, i * map->reg_stride))
80 continue;
81 val = regcache_get_val(map, map->reg_defaults_raw, i);
82 map->reg_defaults[j].reg = i * map->reg_stride;
83 map->reg_defaults[j].def = val;
84 j++;
85 }
86
87 return 0;
88
89err_cache_free:
90 kfree(tmp_buf);
91err_free:
92 kfree(map->reg_defaults);
93
94 return ret;
95}
96
97int regcache_init(struct regmap *map, const struct regmap_config *config)
98{
99 int ret;
100 int i;
101 void *tmp_buf;
102
103 for (i = 0; i < config->num_reg_defaults; i++)
104 if (config->reg_defaults[i].reg % map->reg_stride)
105 return -EINVAL;
106
107 if (map->cache_type == REGCACHE_NONE) {
108 map->cache_bypass = true;
109 return 0;
110 }
111
112 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
113 if (cache_types[i]->type == map->cache_type)
114 break;
115
116 if (i == ARRAY_SIZE(cache_types)) {
117 dev_err(map->dev, "Could not match compress type: %d\n",
118 map->cache_type);
119 return -EINVAL;
120 }
121
122 map->num_reg_defaults = config->num_reg_defaults;
123 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
124 map->reg_defaults_raw = config->reg_defaults_raw;
125 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
126 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
127
128 map->cache = NULL;
129 map->cache_ops = cache_types[i];
130
131 if (!map->cache_ops->read ||
132 !map->cache_ops->write ||
133 !map->cache_ops->name)
134 return -EINVAL;
135
136
137
138
139
140 if (config->reg_defaults) {
141 if (!map->num_reg_defaults)
142 return -EINVAL;
143 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
144 sizeof(struct reg_default), GFP_KERNEL);
145 if (!tmp_buf)
146 return -ENOMEM;
147 map->reg_defaults = tmp_buf;
148 } else if (map->num_reg_defaults_raw) {
149
150
151
152
153 ret = regcache_hw_init(map);
154 if (ret < 0)
155 return ret;
156 if (map->cache_bypass)
157 return 0;
158 }
159
160 if (!map->max_register)
161 map->max_register = map->num_reg_defaults_raw;
162
163 if (map->cache_ops->init) {
164 dev_dbg(map->dev, "Initializing %s cache\n",
165 map->cache_ops->name);
166 ret = map->cache_ops->init(map);
167 if (ret)
168 goto err_free;
169 }
170 return 0;
171
172err_free:
173 kfree(map->reg_defaults);
174 if (map->cache_free)
175 kfree(map->reg_defaults_raw);
176
177 return ret;
178}
179
180void regcache_exit(struct regmap *map)
181{
182 if (map->cache_type == REGCACHE_NONE)
183 return;
184
185 BUG_ON(!map->cache_ops);
186
187 kfree(map->reg_defaults);
188 if (map->cache_free)
189 kfree(map->reg_defaults_raw);
190
191 if (map->cache_ops->exit) {
192 dev_dbg(map->dev, "Destroying %s cache\n",
193 map->cache_ops->name);
194 map->cache_ops->exit(map);
195 }
196}
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206
207int regcache_read(struct regmap *map,
208 unsigned int reg, unsigned int *value)
209{
210 int ret;
211
212 if (map->cache_type == REGCACHE_NONE)
213 return -ENOSYS;
214
215 BUG_ON(!map->cache_ops);
216
217 if (!regmap_volatile(map, reg)) {
218 ret = map->cache_ops->read(map, reg, value);
219
220 if (ret == 0)
221 trace_regmap_reg_read_cache(map, reg, *value);
222
223 return ret;
224 }
225
226 return -EINVAL;
227}
228
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237
238int regcache_write(struct regmap *map,
239 unsigned int reg, unsigned int value)
240{
241 if (map->cache_type == REGCACHE_NONE)
242 return 0;
243
244 BUG_ON(!map->cache_ops);
245
246 if (!regmap_volatile(map, reg))
247 return map->cache_ops->write(map, reg, value);
248
249 return 0;
250}
251
252static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
253 unsigned int val)
254{
255 int ret;
256
257
258 if (!map->no_sync_defaults)
259 return true;
260
261
262 ret = regcache_lookup_reg(map, reg);
263 if (ret >= 0 && val == map->reg_defaults[ret].def)
264 return false;
265 return true;
266}
267
268static int regcache_default_sync(struct regmap *map, unsigned int min,
269 unsigned int max)
270{
271 unsigned int reg;
272
273 for (reg = min; reg <= max; reg += map->reg_stride) {
274 unsigned int val;
275 int ret;
276
277 if (regmap_volatile(map, reg) ||
278 !regmap_writeable(map, reg))
279 continue;
280
281 ret = regcache_read(map, reg, &val);
282 if (ret)
283 return ret;
284
285 if (!regcache_reg_needs_sync(map, reg, val))
286 continue;
287
288 map->cache_bypass = 1;
289 ret = _regmap_write(map, reg, val);
290 map->cache_bypass = 0;
291 if (ret) {
292 dev_err(map->dev, "Unable to sync register %#x. %d\n",
293 reg, ret);
294 return ret;
295 }
296 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
297 }
298
299 return 0;
300}
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311
312
313int regcache_sync(struct regmap *map)
314{
315 int ret = 0;
316 unsigned int i;
317 const char *name;
318 unsigned int bypass;
319
320 BUG_ON(!map->cache_ops);
321
322 map->lock(map->lock_arg);
323
324 bypass = map->cache_bypass;
325 dev_dbg(map->dev, "Syncing %s cache\n",
326 map->cache_ops->name);
327 name = map->cache_ops->name;
328 trace_regcache_sync(map, name, "start");
329
330 if (!map->cache_dirty)
331 goto out;
332
333 map->async = true;
334
335
336 map->cache_bypass = 1;
337 for (i = 0; i < map->patch_regs; i++) {
338 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
339 if (ret != 0) {
340 dev_err(map->dev, "Failed to write %x = %x: %d\n",
341 map->patch[i].reg, map->patch[i].def, ret);
342 goto out;
343 }
344 }
345 map->cache_bypass = 0;
346
347 if (map->cache_ops->sync)
348 ret = map->cache_ops->sync(map, 0, map->max_register);
349 else
350 ret = regcache_default_sync(map, 0, map->max_register);
351
352 if (ret == 0)
353 map->cache_dirty = false;
354
355out:
356
357 map->async = false;
358 map->cache_bypass = bypass;
359 map->no_sync_defaults = false;
360 map->unlock(map->lock_arg);
361
362 regmap_async_complete(map);
363
364 trace_regcache_sync(map, name, "stop");
365
366 return ret;
367}
368EXPORT_SYMBOL_GPL(regcache_sync);
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381
382int regcache_sync_region(struct regmap *map, unsigned int min,
383 unsigned int max)
384{
385 int ret = 0;
386 const char *name;
387 unsigned int bypass;
388
389 BUG_ON(!map->cache_ops);
390
391 map->lock(map->lock_arg);
392
393
394 bypass = map->cache_bypass;
395
396 name = map->cache_ops->name;
397 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
398
399 trace_regcache_sync(map, name, "start region");
400
401 if (!map->cache_dirty)
402 goto out;
403
404 map->async = true;
405
406 if (map->cache_ops->sync)
407 ret = map->cache_ops->sync(map, min, max);
408 else
409 ret = regcache_default_sync(map, min, max);
410
411out:
412
413 map->cache_bypass = bypass;
414 map->async = false;
415 map->no_sync_defaults = false;
416 map->unlock(map->lock_arg);
417
418 regmap_async_complete(map);
419
420 trace_regcache_sync(map, name, "stop region");
421
422 return ret;
423}
424EXPORT_SYMBOL_GPL(regcache_sync_region);
425
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436
437int regcache_drop_region(struct regmap *map, unsigned int min,
438 unsigned int max)
439{
440 int ret = 0;
441
442 if (!map->cache_ops || !map->cache_ops->drop)
443 return -EINVAL;
444
445 map->lock(map->lock_arg);
446
447 trace_regcache_drop_region(map, min, max);
448
449 ret = map->cache_ops->drop(map, min, max);
450
451 map->unlock(map->lock_arg);
452
453 return ret;
454}
455EXPORT_SYMBOL_GPL(regcache_drop_region);
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468
469void regcache_cache_only(struct regmap *map, bool enable)
470{
471 map->lock(map->lock_arg);
472 WARN_ON(map->cache_bypass && enable);
473 map->cache_only = enable;
474 trace_regmap_cache_only(map, enable);
475 map->unlock(map->lock_arg);
476}
477EXPORT_SYMBOL_GPL(regcache_cache_only);
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491
492void regcache_mark_dirty(struct regmap *map)
493{
494 map->lock(map->lock_arg);
495 map->cache_dirty = true;
496 map->no_sync_defaults = true;
497 map->unlock(map->lock_arg);
498}
499EXPORT_SYMBOL_GPL(regcache_mark_dirty);
500
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511
512void regcache_cache_bypass(struct regmap *map, bool enable)
513{
514 map->lock(map->lock_arg);
515 WARN_ON(map->cache_only && enable);
516 map->cache_bypass = enable;
517 trace_regmap_cache_bypass(map, enable);
518 map->unlock(map->lock_arg);
519}
520EXPORT_SYMBOL_GPL(regcache_cache_bypass);
521
522bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
523 unsigned int val)
524{
525 if (regcache_get_val(map, base, idx) == val)
526 return true;
527
528
529 if (map->format.format_val) {
530 map->format.format_val(base + (map->cache_word_size * idx),
531 val, 0);
532 return false;
533 }
534
535 switch (map->cache_word_size) {
536 case 1: {
537 u8 *cache = base;
538 cache[idx] = val;
539 break;
540 }
541 case 2: {
542 u16 *cache = base;
543 cache[idx] = val;
544 break;
545 }
546 case 4: {
547 u32 *cache = base;
548 cache[idx] = val;
549 break;
550 }
551 default:
552 BUG();
553 }
554 return false;
555}
556
557unsigned int regcache_get_val(struct regmap *map, const void *base,
558 unsigned int idx)
559{
560 if (!base)
561 return -EINVAL;
562
563
564 if (map->format.parse_val)
565 return map->format.parse_val(regcache_get_val_addr(map, base,
566 idx));
567
568 switch (map->cache_word_size) {
569 case 1: {
570 const u8 *cache = base;
571 return cache[idx];
572 }
573 case 2: {
574 const u16 *cache = base;
575 return cache[idx];
576 }
577 case 4: {
578 const u32 *cache = base;
579 return cache[idx];
580 }
581 default:
582 BUG();
583 }
584
585 return -1;
586}
587
588static int regcache_default_cmp(const void *a, const void *b)
589{
590 const struct reg_default *_a = a;
591 const struct reg_default *_b = b;
592
593 return _a->reg - _b->reg;
594}
595
596int regcache_lookup_reg(struct regmap *map, unsigned int reg)
597{
598 struct reg_default key;
599 struct reg_default *r;
600
601 key.reg = reg;
602 key.def = 0;
603
604 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
605 sizeof(struct reg_default), regcache_default_cmp);
606
607 if (r)
608 return r - map->reg_defaults;
609 else
610 return -ENOENT;
611}
612
613static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
614{
615 if (!cache_present)
616 return true;
617
618 return test_bit(idx, cache_present);
619}
620
621static int regcache_sync_block_single(struct regmap *map, void *block,
622 unsigned long *cache_present,
623 unsigned int block_base,
624 unsigned int start, unsigned int end)
625{
626 unsigned int i, regtmp, val;
627 int ret;
628
629 for (i = start; i < end; i++) {
630 regtmp = block_base + (i * map->reg_stride);
631
632 if (!regcache_reg_present(cache_present, i) ||
633 !regmap_writeable(map, regtmp))
634 continue;
635
636 val = regcache_get_val(map, block, i);
637 if (!regcache_reg_needs_sync(map, regtmp, val))
638 continue;
639
640 map->cache_bypass = 1;
641
642 ret = _regmap_write(map, regtmp, val);
643
644 map->cache_bypass = 0;
645 if (ret != 0) {
646 dev_err(map->dev, "Unable to sync register %#x. %d\n",
647 regtmp, ret);
648 return ret;
649 }
650 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
651 regtmp, val);
652 }
653
654 return 0;
655}
656
657static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
658 unsigned int base, unsigned int cur)
659{
660 size_t val_bytes = map->format.val_bytes;
661 int ret, count;
662
663 if (*data == NULL)
664 return 0;
665
666 count = (cur - base) / map->reg_stride;
667
668 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
669 count * val_bytes, count, base, cur - map->reg_stride);
670
671 map->cache_bypass = 1;
672
673 ret = _regmap_raw_write(map, base, *data, count * val_bytes);
674 if (ret)
675 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
676 base, cur - map->reg_stride, ret);
677
678 map->cache_bypass = 0;
679
680 *data = NULL;
681
682 return ret;
683}
684
685static int regcache_sync_block_raw(struct regmap *map, void *block,
686 unsigned long *cache_present,
687 unsigned int block_base, unsigned int start,
688 unsigned int end)
689{
690 unsigned int i, val;
691 unsigned int regtmp = 0;
692 unsigned int base = 0;
693 const void *data = NULL;
694 int ret;
695
696 for (i = start; i < end; i++) {
697 regtmp = block_base + (i * map->reg_stride);
698
699 if (!regcache_reg_present(cache_present, i) ||
700 !regmap_writeable(map, regtmp)) {
701 ret = regcache_sync_block_raw_flush(map, &data,
702 base, regtmp);
703 if (ret != 0)
704 return ret;
705 continue;
706 }
707
708 val = regcache_get_val(map, block, i);
709 if (!regcache_reg_needs_sync(map, regtmp, val)) {
710 ret = regcache_sync_block_raw_flush(map, &data,
711 base, regtmp);
712 if (ret != 0)
713 return ret;
714 continue;
715 }
716
717 if (!data) {
718 data = regcache_get_val_addr(map, block, i);
719 base = regtmp;
720 }
721 }
722
723 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
724 map->reg_stride);
725}
726
727int regcache_sync_block(struct regmap *map, void *block,
728 unsigned long *cache_present,
729 unsigned int block_base, unsigned int start,
730 unsigned int end)
731{
732 if (regmap_can_raw_write(map) && !map->use_single_rw)
733 return regcache_sync_block_raw(map, block, cache_present,
734 block_base, start, end);
735 else
736 return regcache_sync_block_single(map, block, cache_present,
737 block_base, start, end);
738}
739