1
2
3
4
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 bool "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT
15 help
16 EDAC is designed to report errors in the core system.
17 These are low-level errors that are reported in the CPU or
18 supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 If this code is reporting problems on your system, please
23 see the EDAC project web pages for more information at:
24
25 <http://bluesmoke.sourceforge.net/>
26
27 and:
28
29 <http://buttersideup.com/edacwiki>
30
31 There is also a mailing list for the EDAC project, which can
32 be found via the sourceforge page.
33
34if EDAC
35
36config EDAC_LEGACY_SYSFS
37 bool "EDAC legacy sysfs"
38 default y
39 help
40 Enable the compatibility sysfs nodes.
41 Use 'Y' if your edac utilities aren't ported to work with the newer
42 structures.
43
44config EDAC_DEBUG
45 bool "Debugging"
46 help
47 This turns on debugging information for the entire EDAC subsystem.
48 You do so by inserting edac_module with "edac_debug_level=x." Valid
49 levels are 0-4 (from low to high) and by default it is set to 2.
50 Usually you should select 'N' here.
51
52config EDAC_DECODE_MCE
53 tristate "Decode MCEs in human-readable form (only on AMD for now)"
54 depends on CPU_SUP_AMD && X86_MCE_AMD
55 default y
56 ---help---
57 Enable this option if you want to decode Machine Check Exceptions
58 occurring on your machine in human-readable form.
59
60 You should definitely say Y here in case you want to decode MCEs
61 which occur really early upon boot, before the module infrastructure
62 has been initialized.
63
64config EDAC_MCE_INJ
65 tristate "Simple MCE injection interface"
66 depends on EDAC_DECODE_MCE && DEBUG_FS
67 default n
68 help
69 This is a simple debugfs interface to inject MCEs and test different
70 aspects of the MCE handling code.
71
72 WARNING: Do not even assume this interface is staying stable!
73
74config EDAC_MM_EDAC
75 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
76 select RAS
77 help
78 Some systems are able to detect and correct errors in main
79 memory. EDAC can report statistics on memory error
80 detection and correction (EDAC - or commonly referred to ECC
81 errors). EDAC will also try to decode where these errors
82 occurred so that a particular failing memory module can be
83 replaced. If unsure, select 'Y'.
84
85config EDAC_GHES
86 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
87 depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
88 default y
89 help
90 Not all machines support hardware-driven error report. Some of those
91 provide a BIOS-driven error report mechanism via ACPI, using the
92 APEI/GHES driver. By enabling this option, the error reports provided
93 by GHES are sent to userspace via the EDAC API.
94
95 When this option is enabled, it will disable the hardware-driven
96 mechanisms, if a GHES BIOS is detected, entering into the
97 "Firmware First" mode.
98
99 It should be noticed that keeping both GHES and a hardware-driven
100 error mechanism won't work well, as BIOS will race with OS, while
101 reading the error registers. So, if you want to not use "Firmware
102 first" GHES error mechanism, you should disable GHES either at
103 compilation time or by passing "ghes.disable=1" Kernel parameter
104 at boot time.
105
106 In doubt, say 'Y'.
107
108config EDAC_AMD64
109 tristate "AMD64 (Opteron, Athlon64)"
110 depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE
111 help
112 Support for error detection and correction of DRAM ECC errors on
113 the AMD64 families (>= K8) of memory controllers.
114
115config EDAC_AMD64_ERROR_INJECTION
116 bool "Sysfs HW Error injection facilities"
117 depends on EDAC_AMD64
118 help
119 Recent Opterons (Family 10h and later) provide for Memory Error
120 Injection into the ECC detection circuits. The amd64_edac module
121 allows the operator/user to inject Uncorrectable and Correctable
122 errors into DRAM.
123
124 When enabled, in each of the respective memory controller directories
125 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
126
127 - inject_section (0..3, 16-byte section of 64-byte cacheline),
128 - inject_word (0..8, 16-bit word of 16-byte section),
129 - inject_ecc_vector (hex ecc vector: select bits of inject word)
130
131 In addition, there are two control files, inject_read and inject_write,
132 which trigger the DRAM ECC Read and Write respectively.
133
134config EDAC_AMD76X
135 tristate "AMD 76x (760, 762, 768)"
136 depends on EDAC_MM_EDAC && PCI && X86_32
137 help
138 Support for error detection and correction on the AMD 76x
139 series of chipsets used with the Athlon processor.
140
141config EDAC_E7XXX
142 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
143 depends on EDAC_MM_EDAC && PCI && X86_32
144 help
145 Support for error detection and correction on the Intel
146 E7205, E7500, E7501 and E7505 server chipsets.
147
148config EDAC_E752X
149 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
150 depends on EDAC_MM_EDAC && PCI && X86
151 help
152 Support for error detection and correction on the Intel
153 E7520, E7525, E7320 server chipsets.
154
155config EDAC_I82443BXGX
156 tristate "Intel 82443BX/GX (440BX/GX)"
157 depends on EDAC_MM_EDAC && PCI && X86_32
158 depends on BROKEN
159 help
160 Support for error detection and correction on the Intel
161 82443BX/GX memory controllers (440BX/GX chipsets).
162
163config EDAC_I82875P
164 tristate "Intel 82875p (D82875P, E7210)"
165 depends on EDAC_MM_EDAC && PCI && X86_32
166 help
167 Support for error detection and correction on the Intel
168 DP82785P and E7210 server chipsets.
169
170config EDAC_I82975X
171 tristate "Intel 82975x (D82975x)"
172 depends on EDAC_MM_EDAC && PCI && X86
173 help
174 Support for error detection and correction on the Intel
175 DP82975x server chipsets.
176
177config EDAC_I3000
178 tristate "Intel 3000/3010"
179 depends on EDAC_MM_EDAC && PCI && X86
180 help
181 Support for error detection and correction on the Intel
182 3000 and 3010 server chipsets.
183
184config EDAC_I3200
185 tristate "Intel 3200"
186 depends on EDAC_MM_EDAC && PCI && X86
187 help
188 Support for error detection and correction on the Intel
189 3200 and 3210 server chipsets.
190
191config EDAC_IE31200
192 tristate "Intel e312xx"
193 depends on EDAC_MM_EDAC && PCI && X86
194 help
195 Support for error detection and correction on the Intel
196 E3-1200 based DRAM controllers.
197
198config EDAC_X38
199 tristate "Intel X38"
200 depends on EDAC_MM_EDAC && PCI && X86
201 help
202 Support for error detection and correction on the Intel
203 X38 server chipsets.
204
205config EDAC_I5400
206 tristate "Intel 5400 (Seaburg) chipsets"
207 depends on EDAC_MM_EDAC && PCI && X86
208 help
209 Support for error detection and correction the Intel
210 i5400 MCH chipset (Seaburg).
211
212config EDAC_I7CORE
213 tristate "Intel i7 Core (Nehalem) processors"
214 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
215 help
216 Support for error detection and correction the Intel
217 i7 Core (Nehalem) Integrated Memory Controller that exists on
218 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
219 and Xeon 55xx processors.
220
221config EDAC_I82860
222 tristate "Intel 82860"
223 depends on EDAC_MM_EDAC && PCI && X86_32
224 help
225 Support for error detection and correction on the Intel
226 82860 chipset.
227
228config EDAC_R82600
229 tristate "Radisys 82600 embedded chipset"
230 depends on EDAC_MM_EDAC && PCI && X86_32
231 help
232 Support for error detection and correction on the Radisys
233 82600 embedded chipset.
234
235config EDAC_I5000
236 tristate "Intel Greencreek/Blackford chipset"
237 depends on EDAC_MM_EDAC && X86 && PCI
238 help
239 Support for error detection and correction the Intel
240 Greekcreek/Blackford chipsets.
241
242config EDAC_I5100
243 tristate "Intel San Clemente MCH"
244 depends on EDAC_MM_EDAC && X86 && PCI
245 help
246 Support for error detection and correction the Intel
247 San Clemente MCH.
248
249config EDAC_I7300
250 tristate "Intel Clarksboro MCH"
251 depends on EDAC_MM_EDAC && X86 && PCI
252 help
253 Support for error detection and correction the Intel
254 Clarksboro MCH (Intel 7300 chipset).
255
256config EDAC_SBRIDGE
257 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
258 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
259 depends on PCI_MMCONFIG
260 help
261 Support for error detection and correction the Intel
262 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
263
264config EDAC_MPC85XX
265 tristate "Freescale MPC83xx / MPC85xx"
266 depends on EDAC_MM_EDAC && FSL_SOC
267 help
268 Support for error detection and correction on the Freescale
269 MPC8349, MPC8560, MPC8540, MPC8548, T4240
270
271config EDAC_MV64X60
272 tristate "Marvell MV64x60"
273 depends on EDAC_MM_EDAC && MV64X60
274 help
275 Support for error detection and correction on the Marvell
276 MV64360 and MV64460 chipsets.
277
278config EDAC_PASEMI
279 tristate "PA Semi PWRficient"
280 depends on EDAC_MM_EDAC && PCI
281 depends on PPC_PASEMI
282 help
283 Support for error detection and correction on PA Semi
284 PWRficient.
285
286config EDAC_CELL
287 tristate "Cell Broadband Engine memory controller"
288 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
289 help
290 Support for error detection and correction on the
291 Cell Broadband Engine internal memory controller
292 on platform without a hypervisor
293
294config EDAC_PPC4XX
295 tristate "PPC4xx IBM DDR2 Memory Controller"
296 depends on EDAC_MM_EDAC && 4xx
297 help
298 This enables support for EDAC on the ECC memory used
299 with the IBM DDR2 memory controller found in various
300 PowerPC 4xx embedded processors such as the 405EX[r],
301 440SP, 440SPe, 460EX, 460GT and 460SX.
302
303config EDAC_AMD8131
304 tristate "AMD8131 HyperTransport PCI-X Tunnel"
305 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
306 help
307 Support for error detection and correction on the
308 AMD8131 HyperTransport PCI-X Tunnel chip.
309 Note, add more Kconfig dependency if it's adopted
310 on some machine other than Maple.
311
312config EDAC_AMD8111
313 tristate "AMD8111 HyperTransport I/O Hub"
314 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
315 help
316 Support for error detection and correction on the
317 AMD8111 HyperTransport I/O Hub chip.
318 Note, add more Kconfig dependency if it's adopted
319 on some machine other than Maple.
320
321config EDAC_CPC925
322 tristate "IBM CPC925 Memory Controller (PPC970FX)"
323 depends on EDAC_MM_EDAC && PPC64
324 help
325 Support for error detection and correction on the
326 IBM CPC925 Bridge and Memory Controller, which is
327 a companion chip to the PowerPC 970 family of
328 processors.
329
330config EDAC_TILE
331 tristate "Tilera Memory Controller"
332 depends on EDAC_MM_EDAC && TILE
333 default y
334 help
335 Support for error detection and correction on the
336 Tilera memory controller.
337
338config EDAC_HIGHBANK_MC
339 tristate "Highbank Memory Controller"
340 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
341 help
342 Support for error detection and correction on the
343 Calxeda Highbank memory controller.
344
345config EDAC_HIGHBANK_L2
346 tristate "Highbank L2 Cache"
347 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
348 help
349 Support for error detection and correction on the
350 Calxeda Highbank memory controller.
351
352config EDAC_OCTEON_PC
353 tristate "Cavium Octeon Primary Caches"
354 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
355 help
356 Support for error detection and correction on the primary caches of
357 the cnMIPS cores of Cavium Octeon family SOCs.
358
359config EDAC_OCTEON_L2C
360 tristate "Cavium Octeon Secondary Caches (L2C)"
361 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
362 help
363 Support for error detection and correction on the
364 Cavium Octeon family of SOCs.
365
366config EDAC_OCTEON_LMC
367 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
368 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
369 help
370 Support for error detection and correction on the
371 Cavium Octeon family of SOCs.
372
373config EDAC_OCTEON_PCI
374 tristate "Cavium Octeon PCI Controller"
375 depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
376 help
377 Support for error detection and correction on the
378 Cavium Octeon family of SOCs.
379
380config EDAC_ALTERA_MC
381 bool "Altera SDRAM Memory Controller EDAC"
382 depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
383 help
384 Support for error detection and correction on the
385 Altera SDRAM memory controller. Note that the
386 preloader must initialize the SDRAM before loading
387 the kernel.
388
389config EDAC_SYNOPSYS
390 tristate "Synopsys DDR Memory Controller"
391 depends on EDAC_MM_EDAC && ARCH_ZYNQ
392 help
393 Support for error detection and correction on the Synopsys DDR
394 memory controller.
395
396config EDAC_XGENE
397 tristate "APM X-Gene SoC"
398 depends on EDAC_MM_EDAC && (ARM64 || COMPILE_TEST)
399 help
400 Support for error detection and correction on the
401 APM X-Gene family of SOCs.
402
403endif
404
