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23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/pci.h>
26#include <linux/pci_ids.h>
27#include <linux/edac.h>
28#include <linux/delay.h>
29#include <linux/mmzone.h>
30#include <linux/debugfs.h>
31
32#include "edac_core.h"
33
34
35
36
37#define I5100_MC 0x40
38#define I5100_MC_SCRBEN_MASK (1 << 7)
39#define I5100_MC_SCRBDONE_MASK (1 << 4)
40#define I5100_MS 0x44
41#define I5100_SPDDATA 0x48
42#define I5100_SPDCMD 0x4c
43#define I5100_TOLM 0x6c
44#define I5100_MIR0 0x80
45#define I5100_MIR1 0x84
46#define I5100_AMIR_0 0x8c
47#define I5100_AMIR_1 0x90
48#define I5100_FERR_NF_MEM 0xa0
49#define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)
50#define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)
51#define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)
52#define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)
53#define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)
54#define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)
55#define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)
56#define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)
57#define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)
58#define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)
59#define I5100_FERR_NF_MEM_ANY_MASK \
60 (I5100_FERR_NF_MEM_M16ERR_MASK | \
61 I5100_FERR_NF_MEM_M15ERR_MASK | \
62 I5100_FERR_NF_MEM_M14ERR_MASK | \
63 I5100_FERR_NF_MEM_M12ERR_MASK | \
64 I5100_FERR_NF_MEM_M11ERR_MASK | \
65 I5100_FERR_NF_MEM_M10ERR_MASK | \
66 I5100_FERR_NF_MEM_M6ERR_MASK | \
67 I5100_FERR_NF_MEM_M5ERR_MASK | \
68 I5100_FERR_NF_MEM_M4ERR_MASK | \
69 I5100_FERR_NF_MEM_M1ERR_MASK)
70#define I5100_NERR_NF_MEM 0xa4
71#define I5100_EMASK_MEM 0xa8
72#define I5100_MEM0EINJMSK0 0x200
73#define I5100_MEM1EINJMSK0 0x208
74#define I5100_MEMXEINJMSK0_EINJEN (1 << 27)
75#define I5100_MEM0EINJMSK1 0x204
76#define I5100_MEM1EINJMSK1 0x206
77
78
79#define I5100_DINJ0 0x9a
80
81
82#define I5100_MTR_0 0x154
83#define I5100_DMIR 0x15c
84#define I5100_VALIDLOG 0x18c
85#define I5100_NRECMEMA 0x190
86#define I5100_NRECMEMB 0x194
87#define I5100_REDMEMA 0x198
88#define I5100_REDMEMB 0x19c
89#define I5100_RECMEMA 0x1a0
90#define I5100_RECMEMB 0x1a4
91#define I5100_MTR_4 0x1b0
92
93
94
95static inline u32 i5100_mc_scrben(u32 mc)
96{
97 return mc >> 7 & 1;
98}
99
100static inline u32 i5100_mc_errdeten(u32 mc)
101{
102 return mc >> 5 & 1;
103}
104
105static inline u32 i5100_mc_scrbdone(u32 mc)
106{
107 return mc >> 4 & 1;
108}
109
110static inline u16 i5100_spddata_rdo(u16 a)
111{
112 return a >> 15 & 1;
113}
114
115static inline u16 i5100_spddata_sbe(u16 a)
116{
117 return a >> 13 & 1;
118}
119
120static inline u16 i5100_spddata_busy(u16 a)
121{
122 return a >> 12 & 1;
123}
124
125static inline u16 i5100_spddata_data(u16 a)
126{
127 return a & ((1 << 8) - 1);
128}
129
130static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
131 u32 data, u32 cmd)
132{
133 return ((dti & ((1 << 4) - 1)) << 28) |
134 ((ckovrd & 1) << 27) |
135 ((sa & ((1 << 3) - 1)) << 24) |
136 ((ba & ((1 << 8) - 1)) << 16) |
137 ((data & ((1 << 8) - 1)) << 8) |
138 (cmd & 1);
139}
140
141static inline u16 i5100_tolm_tolm(u16 a)
142{
143 return a >> 12 & ((1 << 4) - 1);
144}
145
146static inline u16 i5100_mir_limit(u16 a)
147{
148 return a >> 4 & ((1 << 12) - 1);
149}
150
151static inline u16 i5100_mir_way1(u16 a)
152{
153 return a >> 1 & 1;
154}
155
156static inline u16 i5100_mir_way0(u16 a)
157{
158 return a & 1;
159}
160
161static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
162{
163 return a >> 28 & 1;
164}
165
166static inline u32 i5100_ferr_nf_mem_any(u32 a)
167{
168 return a & I5100_FERR_NF_MEM_ANY_MASK;
169}
170
171static inline u32 i5100_nerr_nf_mem_any(u32 a)
172{
173 return i5100_ferr_nf_mem_any(a);
174}
175
176static inline u32 i5100_dmir_limit(u32 a)
177{
178 return a >> 16 & ((1 << 11) - 1);
179}
180
181static inline u32 i5100_dmir_rank(u32 a, u32 i)
182{
183 return a >> (4 * i) & ((1 << 2) - 1);
184}
185
186static inline u16 i5100_mtr_present(u16 a)
187{
188 return a >> 10 & 1;
189}
190
191static inline u16 i5100_mtr_ethrottle(u16 a)
192{
193 return a >> 9 & 1;
194}
195
196static inline u16 i5100_mtr_width(u16 a)
197{
198 return a >> 8 & 1;
199}
200
201static inline u16 i5100_mtr_numbank(u16 a)
202{
203 return a >> 6 & 1;
204}
205
206static inline u16 i5100_mtr_numrow(u16 a)
207{
208 return a >> 2 & ((1 << 2) - 1);
209}
210
211static inline u16 i5100_mtr_numcol(u16 a)
212{
213 return a & ((1 << 2) - 1);
214}
215
216
217static inline u32 i5100_validlog_redmemvalid(u32 a)
218{
219 return a >> 2 & 1;
220}
221
222static inline u32 i5100_validlog_recmemvalid(u32 a)
223{
224 return a >> 1 & 1;
225}
226
227static inline u32 i5100_validlog_nrecmemvalid(u32 a)
228{
229 return a & 1;
230}
231
232static inline u32 i5100_nrecmema_merr(u32 a)
233{
234 return a >> 15 & ((1 << 5) - 1);
235}
236
237static inline u32 i5100_nrecmema_bank(u32 a)
238{
239 return a >> 12 & ((1 << 3) - 1);
240}
241
242static inline u32 i5100_nrecmema_rank(u32 a)
243{
244 return a >> 8 & ((1 << 3) - 1);
245}
246
247static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
248{
249 return a & ((1 << 8) - 1);
250}
251
252static inline u32 i5100_nrecmemb_cas(u32 a)
253{
254 return a >> 16 & ((1 << 13) - 1);
255}
256
257static inline u32 i5100_nrecmemb_ras(u32 a)
258{
259 return a & ((1 << 16) - 1);
260}
261
262static inline u32 i5100_redmemb_ecc_locator(u32 a)
263{
264 return a & ((1 << 18) - 1);
265}
266
267static inline u32 i5100_recmema_merr(u32 a)
268{
269 return i5100_nrecmema_merr(a);
270}
271
272static inline u32 i5100_recmema_bank(u32 a)
273{
274 return i5100_nrecmema_bank(a);
275}
276
277static inline u32 i5100_recmema_rank(u32 a)
278{
279 return i5100_nrecmema_rank(a);
280}
281
282static inline u32 i5100_recmemb_cas(u32 a)
283{
284 return i5100_nrecmemb_cas(a);
285}
286
287static inline u32 i5100_recmemb_ras(u32 a)
288{
289 return i5100_nrecmemb_ras(a);
290}
291
292
293#define I5100_MAX_RANKS_PER_CHAN 6
294#define I5100_CHANNELS 2
295#define I5100_MAX_RANKS_PER_DIMM 4
296#define I5100_DIMM_ADDR_LINES (6 - 3)
297#define I5100_MAX_DIMM_SLOTS_PER_CHAN 4
298#define I5100_MAX_RANK_INTERLEAVE 4
299#define I5100_MAX_DMIRS 5
300#define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)
301
302struct i5100_priv {
303
304 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
305
306
307
308
309
310
311
312
313
314 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
315
316
317 struct {
318 u64 limit;
319 unsigned way[2];
320 } mir[I5100_CHANNELS];
321
322
323 unsigned amir[I5100_CHANNELS];
324
325
326 struct {
327 unsigned rank[I5100_MAX_RANK_INTERLEAVE];
328 u64 limit;
329 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
330
331
332 struct {
333 unsigned present;
334 unsigned ethrottle;
335 unsigned width;
336 unsigned numbank;
337 unsigned numrow;
338 unsigned numcol;
339 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
340
341 u64 tolm;
342 unsigned ranksperchan;
343
344 struct pci_dev *mc;
345 struct pci_dev *einj;
346 struct pci_dev *ch0mm;
347 struct pci_dev *ch1mm;
348
349 struct delayed_work i5100_scrubbing;
350 int scrub_enable;
351
352
353 u8 inject_channel;
354 u8 inject_hlinesel;
355 u8 inject_deviceptr1;
356 u8 inject_deviceptr2;
357 u16 inject_eccmask1;
358 u16 inject_eccmask2;
359
360 struct dentry *debugfs;
361};
362
363static struct dentry *i5100_debugfs;
364
365
366static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
367 int chan, int rank)
368{
369 const struct i5100_priv *priv = mci->pvt_info;
370 int i;
371
372 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
373 int j;
374 const int numrank = priv->dimm_numrank[chan][i];
375
376 for (j = 0; j < numrank; j++)
377 if (priv->dimm_csmap[i][j] == rank)
378 return i * 2 + chan;
379 }
380
381 return -1;
382}
383
384static const char *i5100_err_msg(unsigned err)
385{
386 static const char *merrs[] = {
387 "unknown",
388 "uncorrectable data ECC on replay",
389 "unknown",
390 "unknown",
391 "aliased uncorrectable demand data ECC",
392 "aliased uncorrectable spare-copy data ECC",
393 "aliased uncorrectable patrol data ECC",
394 "unknown",
395 "unknown",
396 "unknown",
397 "non-aliased uncorrectable demand data ECC",
398 "non-aliased uncorrectable spare-copy data ECC",
399 "non-aliased uncorrectable patrol data ECC",
400 "unknown",
401 "correctable demand data ECC",
402 "correctable spare-copy data ECC",
403 "correctable patrol data ECC",
404 "unknown",
405 "SPD protocol error",
406 "unknown",
407 "spare copy initiated",
408 "spare copy completed",
409 };
410 unsigned i;
411
412 for (i = 0; i < ARRAY_SIZE(merrs); i++)
413 if (1 << i & err)
414 return merrs[i];
415
416 return "none";
417}
418
419
420static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
421{
422 const struct i5100_priv *priv = mci->pvt_info;
423
424 return csrow % priv->ranksperchan;
425}
426
427
428static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
429{
430 const struct i5100_priv *priv = mci->pvt_info;
431
432 return csrow / priv->ranksperchan;
433}
434
435static void i5100_handle_ce(struct mem_ctl_info *mci,
436 int chan,
437 unsigned bank,
438 unsigned rank,
439 unsigned long syndrome,
440 unsigned cas,
441 unsigned ras,
442 const char *msg)
443{
444 char detail[80];
445
446
447 snprintf(detail, sizeof(detail),
448 "bank %u, cas %u, ras %u\n",
449 bank, cas, ras);
450
451 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
452 0, 0, syndrome,
453 chan, rank, -1,
454 msg, detail);
455}
456
457static void i5100_handle_ue(struct mem_ctl_info *mci,
458 int chan,
459 unsigned bank,
460 unsigned rank,
461 unsigned long syndrome,
462 unsigned cas,
463 unsigned ras,
464 const char *msg)
465{
466 char detail[80];
467
468
469 snprintf(detail, sizeof(detail),
470 "bank %u, cas %u, ras %u\n",
471 bank, cas, ras);
472
473 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
474 0, 0, syndrome,
475 chan, rank, -1,
476 msg, detail);
477}
478
479static void i5100_read_log(struct mem_ctl_info *mci, int chan,
480 u32 ferr, u32 nerr)
481{
482 struct i5100_priv *priv = mci->pvt_info;
483 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
484 u32 dw;
485 u32 dw2;
486 unsigned syndrome = 0;
487 unsigned ecc_loc = 0;
488 unsigned merr;
489 unsigned bank;
490 unsigned rank;
491 unsigned cas;
492 unsigned ras;
493
494 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
495
496 if (i5100_validlog_redmemvalid(dw)) {
497 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
498 syndrome = dw2;
499 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
500 ecc_loc = i5100_redmemb_ecc_locator(dw2);
501 }
502
503 if (i5100_validlog_recmemvalid(dw)) {
504 const char *msg;
505
506 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
507 merr = i5100_recmema_merr(dw2);
508 bank = i5100_recmema_bank(dw2);
509 rank = i5100_recmema_rank(dw2);
510
511 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
512 cas = i5100_recmemb_cas(dw2);
513 ras = i5100_recmemb_ras(dw2);
514
515
516
517 if (!merr)
518 msg = i5100_err_msg(ferr);
519 else
520 msg = i5100_err_msg(nerr);
521
522 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
523 }
524
525 if (i5100_validlog_nrecmemvalid(dw)) {
526 const char *msg;
527
528 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
529 merr = i5100_nrecmema_merr(dw2);
530 bank = i5100_nrecmema_bank(dw2);
531 rank = i5100_nrecmema_rank(dw2);
532
533 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
534 cas = i5100_nrecmemb_cas(dw2);
535 ras = i5100_nrecmemb_ras(dw2);
536
537
538
539 if (!merr)
540 msg = i5100_err_msg(ferr);
541 else
542 msg = i5100_err_msg(nerr);
543
544 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
545 }
546
547 pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
548}
549
550static void i5100_check_error(struct mem_ctl_info *mci)
551{
552 struct i5100_priv *priv = mci->pvt_info;
553 u32 dw, dw2;
554
555 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
556 if (i5100_ferr_nf_mem_any(dw)) {
557
558 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
559
560 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
561 i5100_ferr_nf_mem_any(dw),
562 i5100_nerr_nf_mem_any(dw2));
563
564 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
565 }
566 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
567}
568
569
570
571
572
573
574
575static void i5100_refresh_scrubbing(struct work_struct *work)
576{
577 struct delayed_work *i5100_scrubbing = container_of(work,
578 struct delayed_work,
579 work);
580 struct i5100_priv *priv = container_of(i5100_scrubbing,
581 struct i5100_priv,
582 i5100_scrubbing);
583 u32 dw;
584
585 pci_read_config_dword(priv->mc, I5100_MC, &dw);
586
587 if (priv->scrub_enable) {
588
589 pci_read_config_dword(priv->mc, I5100_MC, &dw);
590
591 if (i5100_mc_scrbdone(dw)) {
592 dw |= I5100_MC_SCRBEN_MASK;
593 pci_write_config_dword(priv->mc, I5100_MC, dw);
594 pci_read_config_dword(priv->mc, I5100_MC, &dw);
595 }
596
597 schedule_delayed_work(&(priv->i5100_scrubbing),
598 I5100_SCRUB_REFRESH_RATE);
599 }
600}
601
602
603
604static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
605{
606 struct i5100_priv *priv = mci->pvt_info;
607 u32 dw;
608
609 pci_read_config_dword(priv->mc, I5100_MC, &dw);
610 if (bandwidth) {
611 priv->scrub_enable = 1;
612 dw |= I5100_MC_SCRBEN_MASK;
613 schedule_delayed_work(&(priv->i5100_scrubbing),
614 I5100_SCRUB_REFRESH_RATE);
615 } else {
616 priv->scrub_enable = 0;
617 dw &= ~I5100_MC_SCRBEN_MASK;
618 cancel_delayed_work(&(priv->i5100_scrubbing));
619 }
620 pci_write_config_dword(priv->mc, I5100_MC, dw);
621
622 pci_read_config_dword(priv->mc, I5100_MC, &dw);
623
624 bandwidth = 5900000 * i5100_mc_scrben(dw);
625
626 return bandwidth;
627}
628
629static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
630{
631 struct i5100_priv *priv = mci->pvt_info;
632 u32 dw;
633
634 pci_read_config_dword(priv->mc, I5100_MC, &dw);
635
636 return 5900000 * i5100_mc_scrben(dw);
637}
638
639static struct pci_dev *pci_get_device_func(unsigned vendor,
640 unsigned device,
641 unsigned func)
642{
643 struct pci_dev *ret = NULL;
644
645 while (1) {
646 ret = pci_get_device(vendor, device, ret);
647
648 if (!ret)
649 break;
650
651 if (PCI_FUNC(ret->devfn) == func)
652 break;
653 }
654
655 return ret;
656}
657
658static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow)
659{
660 struct i5100_priv *priv = mci->pvt_info;
661 const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
662 const unsigned chan = i5100_csrow_to_chan(mci, csrow);
663 unsigned addr_lines;
664
665
666 if (!priv->mtr[chan][chan_rank].present)
667 return 0ULL;
668
669 addr_lines =
670 I5100_DIMM_ADDR_LINES +
671 priv->mtr[chan][chan_rank].numcol +
672 priv->mtr[chan][chan_rank].numrow +
673 priv->mtr[chan][chan_rank].numbank;
674
675 return (unsigned long)
676 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
677}
678
679static void i5100_init_mtr(struct mem_ctl_info *mci)
680{
681 struct i5100_priv *priv = mci->pvt_info;
682 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
683 int i;
684
685 for (i = 0; i < I5100_CHANNELS; i++) {
686 int j;
687 struct pci_dev *pdev = mms[i];
688
689 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
690 const unsigned addr =
691 (j < 4) ? I5100_MTR_0 + j * 2 :
692 I5100_MTR_4 + (j - 4) * 2;
693 u16 w;
694
695 pci_read_config_word(pdev, addr, &w);
696
697 priv->mtr[i][j].present = i5100_mtr_present(w);
698 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
699 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
700 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
701 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
702 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
703 }
704 }
705}
706
707
708
709
710
711static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
712 u8 ch, u8 slot, u8 addr, u8 *byte)
713{
714 struct i5100_priv *priv = mci->pvt_info;
715 u16 w;
716 unsigned long et;
717
718 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
719 if (i5100_spddata_busy(w))
720 return -1;
721
722 pci_write_config_dword(priv->mc, I5100_SPDCMD,
723 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
724 0, 0));
725
726
727 et = jiffies + HZ / 10;
728 udelay(100);
729 while (1) {
730 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
731 if (!i5100_spddata_busy(w))
732 break;
733 udelay(100);
734 }
735
736 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
737 return -1;
738
739 *byte = i5100_spddata_data(w);
740
741 return 0;
742}
743
744
745
746
747
748
749
750
751static void i5100_init_dimm_csmap(struct mem_ctl_info *mci)
752{
753 struct i5100_priv *priv = mci->pvt_info;
754 int i;
755
756 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
757 int j;
758
759 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
760 priv->dimm_csmap[i][j] = -1;
761 }
762
763
764 if (priv->ranksperchan == 4) {
765 priv->dimm_csmap[0][0] = 0;
766 priv->dimm_csmap[0][1] = 3;
767 priv->dimm_csmap[1][0] = 1;
768 priv->dimm_csmap[1][1] = 2;
769 priv->dimm_csmap[2][0] = 2;
770 priv->dimm_csmap[3][0] = 3;
771 } else {
772 priv->dimm_csmap[0][0] = 0;
773 priv->dimm_csmap[0][1] = 1;
774 priv->dimm_csmap[1][0] = 2;
775 priv->dimm_csmap[1][1] = 3;
776 priv->dimm_csmap[2][0] = 4;
777 priv->dimm_csmap[2][1] = 5;
778 }
779}
780
781static void i5100_init_dimm_layout(struct pci_dev *pdev,
782 struct mem_ctl_info *mci)
783{
784 struct i5100_priv *priv = mci->pvt_info;
785 int i;
786
787 for (i = 0; i < I5100_CHANNELS; i++) {
788 int j;
789
790 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
791 u8 rank;
792
793 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
794 priv->dimm_numrank[i][j] = 0;
795 else
796 priv->dimm_numrank[i][j] = (rank & 3) + 1;
797 }
798 }
799
800 i5100_init_dimm_csmap(mci);
801}
802
803static void i5100_init_interleaving(struct pci_dev *pdev,
804 struct mem_ctl_info *mci)
805{
806 u16 w;
807 u32 dw;
808 struct i5100_priv *priv = mci->pvt_info;
809 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
810 int i;
811
812 pci_read_config_word(pdev, I5100_TOLM, &w);
813 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
814
815 pci_read_config_word(pdev, I5100_MIR0, &w);
816 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
817 priv->mir[0].way[1] = i5100_mir_way1(w);
818 priv->mir[0].way[0] = i5100_mir_way0(w);
819
820 pci_read_config_word(pdev, I5100_MIR1, &w);
821 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
822 priv->mir[1].way[1] = i5100_mir_way1(w);
823 priv->mir[1].way[0] = i5100_mir_way0(w);
824
825 pci_read_config_word(pdev, I5100_AMIR_0, &w);
826 priv->amir[0] = w;
827 pci_read_config_word(pdev, I5100_AMIR_1, &w);
828 priv->amir[1] = w;
829
830 for (i = 0; i < I5100_CHANNELS; i++) {
831 int j;
832
833 for (j = 0; j < 5; j++) {
834 int k;
835
836 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
837
838 priv->dmir[i][j].limit =
839 (u64) i5100_dmir_limit(dw) << 28;
840 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
841 priv->dmir[i][j].rank[k] =
842 i5100_dmir_rank(dw, k);
843 }
844 }
845
846 i5100_init_mtr(mci);
847}
848
849static void i5100_init_csrows(struct mem_ctl_info *mci)
850{
851 int i;
852 struct i5100_priv *priv = mci->pvt_info;
853
854 for (i = 0; i < mci->tot_dimms; i++) {
855 struct dimm_info *dimm;
856 const unsigned long npages = i5100_npages(mci, i);
857 const unsigned chan = i5100_csrow_to_chan(mci, i);
858 const unsigned rank = i5100_csrow_to_rank(mci, i);
859
860 if (!npages)
861 continue;
862
863 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
864 chan, rank, 0);
865
866 dimm->nr_pages = npages;
867 dimm->grain = 32;
868 dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
869 DEV_X4 : DEV_X8;
870 dimm->mtype = MEM_RDDR2;
871 dimm->edac_mode = EDAC_SECDED;
872 snprintf(dimm->label, sizeof(dimm->label), "DIMM%u",
873 i5100_rank_to_slot(mci, chan, rank));
874
875 edac_dbg(2, "dimm channel %d, rank %d, size %ld\n",
876 chan, rank, (long)PAGES_TO_MiB(npages));
877 }
878}
879
880
881
882
883
884static void i5100_do_inject(struct mem_ctl_info *mci)
885{
886 struct i5100_priv *priv = mci->pvt_info;
887 u32 mask0;
888 u16 mask1;
889
890
891
892
893
894
895
896
897
898
899
900
901
902 mask0 = ((priv->inject_hlinesel & 0x3) << 28) |
903 I5100_MEMXEINJMSK0_EINJEN |
904 ((priv->inject_eccmask1 & 0xffff) << 10) |
905 ((priv->inject_deviceptr2 & 0x1f) << 5) |
906 (priv->inject_deviceptr1 & 0x1f);
907
908
909
910
911 mask1 = priv->inject_eccmask2;
912
913 if (priv->inject_channel == 0) {
914 pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0);
915 pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1);
916 } else {
917 pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0);
918 pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1);
919 }
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa);
941 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab);
942}
943
944#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
945static ssize_t inject_enable_write(struct file *file, const char __user *data,
946 size_t count, loff_t *ppos)
947{
948 struct device *dev = file->private_data;
949 struct mem_ctl_info *mci = to_mci(dev);
950
951 i5100_do_inject(mci);
952
953 return count;
954}
955
956static const struct file_operations i5100_inject_enable_fops = {
957 .open = simple_open,
958 .write = inject_enable_write,
959 .llseek = generic_file_llseek,
960};
961
962static int i5100_setup_debugfs(struct mem_ctl_info *mci)
963{
964 struct i5100_priv *priv = mci->pvt_info;
965
966 if (!i5100_debugfs)
967 return -ENODEV;
968
969 priv->debugfs = debugfs_create_dir(mci->bus->name, i5100_debugfs);
970
971 if (!priv->debugfs)
972 return -ENOMEM;
973
974 debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs,
975 &priv->inject_channel);
976 debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs,
977 &priv->inject_hlinesel);
978 debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs,
979 &priv->inject_deviceptr1);
980 debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs,
981 &priv->inject_deviceptr2);
982 debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs,
983 &priv->inject_eccmask1);
984 debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs,
985 &priv->inject_eccmask2);
986 debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs,
987 &mci->dev, &i5100_inject_enable_fops);
988
989 return 0;
990
991}
992
993static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
994{
995 int rc;
996 struct mem_ctl_info *mci;
997 struct edac_mc_layer layers[2];
998 struct i5100_priv *priv;
999 struct pci_dev *ch0mm, *ch1mm, *einj;
1000 int ret = 0;
1001 u32 dw;
1002 int ranksperch;
1003
1004 if (PCI_FUNC(pdev->devfn) != 1)
1005 return -ENODEV;
1006
1007 rc = pci_enable_device(pdev);
1008 if (rc < 0) {
1009 ret = rc;
1010 goto bail;
1011 }
1012
1013
1014 pci_read_config_dword(pdev, I5100_MC, &dw);
1015 if (!i5100_mc_errdeten(dw)) {
1016 printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
1017 ret = -ENODEV;
1018 goto bail_pdev;
1019 }
1020
1021
1022 pci_read_config_dword(pdev, I5100_MS, &dw);
1023 ranksperch = !!(dw & (1 << 8)) * 2 + 4;
1024
1025
1026 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
1027 dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
1028 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
1029
1030
1031 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1032 PCI_DEVICE_ID_INTEL_5100_21, 0);
1033 if (!ch0mm) {
1034 ret = -ENODEV;
1035 goto bail_pdev;
1036 }
1037
1038 rc = pci_enable_device(ch0mm);
1039 if (rc < 0) {
1040 ret = rc;
1041 goto bail_ch0;
1042 }
1043
1044
1045 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1046 PCI_DEVICE_ID_INTEL_5100_22, 0);
1047 if (!ch1mm) {
1048 ret = -ENODEV;
1049 goto bail_disable_ch0;
1050 }
1051
1052 rc = pci_enable_device(ch1mm);
1053 if (rc < 0) {
1054 ret = rc;
1055 goto bail_ch1;
1056 }
1057
1058 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1059 layers[0].size = 2;
1060 layers[0].is_virt_csrow = false;
1061 layers[1].type = EDAC_MC_LAYER_SLOT;
1062 layers[1].size = ranksperch;
1063 layers[1].is_virt_csrow = true;
1064 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
1065 sizeof(*priv));
1066 if (!mci) {
1067 ret = -ENOMEM;
1068 goto bail_disable_ch1;
1069 }
1070
1071
1072
1073 einj = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1074 PCI_DEVICE_ID_INTEL_5100_19, 0);
1075 if (!einj) {
1076 ret = -ENODEV;
1077 goto bail_einj;
1078 }
1079
1080 rc = pci_enable_device(einj);
1081 if (rc < 0) {
1082 ret = rc;
1083 goto bail_disable_einj;
1084 }
1085
1086
1087 mci->pdev = &pdev->dev;
1088
1089 priv = mci->pvt_info;
1090 priv->ranksperchan = ranksperch;
1091 priv->mc = pdev;
1092 priv->ch0mm = ch0mm;
1093 priv->ch1mm = ch1mm;
1094 priv->einj = einj;
1095
1096 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
1097
1098
1099 pci_read_config_dword(pdev, I5100_MC, &dw);
1100 if (i5100_mc_scrben(dw)) {
1101 priv->scrub_enable = 1;
1102 schedule_delayed_work(&(priv->i5100_scrubbing),
1103 I5100_SCRUB_REFRESH_RATE);
1104 }
1105
1106 i5100_init_dimm_layout(pdev, mci);
1107 i5100_init_interleaving(pdev, mci);
1108
1109 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1110 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
1111 mci->edac_cap = EDAC_FLAG_SECDED;
1112 mci->mod_name = "i5100_edac.c";
1113 mci->mod_ver = "not versioned";
1114 mci->ctl_name = "i5100";
1115 mci->dev_name = pci_name(pdev);
1116 mci->ctl_page_to_phys = NULL;
1117
1118 mci->edac_check = i5100_check_error;
1119 mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
1120 mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
1121
1122 priv->inject_channel = 0;
1123 priv->inject_hlinesel = 0;
1124 priv->inject_deviceptr1 = 0;
1125 priv->inject_deviceptr2 = 0;
1126 priv->inject_eccmask1 = 0;
1127 priv->inject_eccmask2 = 0;
1128
1129 i5100_init_csrows(mci);
1130
1131
1132 switch (edac_op_state) {
1133 case EDAC_OPSTATE_POLL:
1134 case EDAC_OPSTATE_NMI:
1135 break;
1136 default:
1137 edac_op_state = EDAC_OPSTATE_POLL;
1138 break;
1139 }
1140
1141 if (edac_mc_add_mc(mci)) {
1142 ret = -ENODEV;
1143 goto bail_scrub;
1144 }
1145
1146 i5100_setup_debugfs(mci);
1147
1148 return ret;
1149
1150bail_scrub:
1151 priv->scrub_enable = 0;
1152 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1153 edac_mc_free(mci);
1154
1155bail_disable_einj:
1156 pci_disable_device(einj);
1157
1158bail_einj:
1159 pci_dev_put(einj);
1160
1161bail_disable_ch1:
1162 pci_disable_device(ch1mm);
1163
1164bail_ch1:
1165 pci_dev_put(ch1mm);
1166
1167bail_disable_ch0:
1168 pci_disable_device(ch0mm);
1169
1170bail_ch0:
1171 pci_dev_put(ch0mm);
1172
1173bail_pdev:
1174 pci_disable_device(pdev);
1175
1176bail:
1177 return ret;
1178}
1179
1180static void i5100_remove_one(struct pci_dev *pdev)
1181{
1182 struct mem_ctl_info *mci;
1183 struct i5100_priv *priv;
1184
1185 mci = edac_mc_del_mc(&pdev->dev);
1186
1187 if (!mci)
1188 return;
1189
1190 priv = mci->pvt_info;
1191
1192 debugfs_remove_recursive(priv->debugfs);
1193
1194 priv->scrub_enable = 0;
1195 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1196
1197 pci_disable_device(pdev);
1198 pci_disable_device(priv->ch0mm);
1199 pci_disable_device(priv->ch1mm);
1200 pci_disable_device(priv->einj);
1201 pci_dev_put(priv->ch0mm);
1202 pci_dev_put(priv->ch1mm);
1203 pci_dev_put(priv->einj);
1204
1205 edac_mc_free(mci);
1206}
1207
1208static const struct pci_device_id i5100_pci_tbl[] = {
1209
1210 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
1211 { 0, }
1212};
1213MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
1214
1215static struct pci_driver i5100_driver = {
1216 .name = KBUILD_BASENAME,
1217 .probe = i5100_init_one,
1218 .remove = i5100_remove_one,
1219 .id_table = i5100_pci_tbl,
1220};
1221
1222static int __init i5100_init(void)
1223{
1224 int pci_rc;
1225
1226 i5100_debugfs = debugfs_create_dir("i5100_edac", NULL);
1227
1228 pci_rc = pci_register_driver(&i5100_driver);
1229 return (pci_rc < 0) ? pci_rc : 0;
1230}
1231
1232static void __exit i5100_exit(void)
1233{
1234 debugfs_remove(i5100_debugfs);
1235
1236 pci_unregister_driver(&i5100_driver);
1237}
1238
1239module_init(i5100_init);
1240module_exit(i5100_exit);
1241
1242MODULE_LICENSE("GPL");
1243MODULE_AUTHOR
1244 ("Arthur Jones <ajones@riverbed.com>");
1245MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");
1246