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23#include <drm/drmP.h>
24#include "radeon.h"
25#include "avivod.h"
26#include "atom.h"
27#include "r600_dpm.h"
28#include <linux/power_supply.h>
29#include <linux/hwmon.h>
30#include <linux/hwmon-sysfs.h>
31
32#define RADEON_IDLE_LOOP_MS 100
33#define RADEON_RECLOCK_DELAY_MS 200
34#define RADEON_WAIT_VBLANK_TIMEOUT 200
35
36static const char *radeon_pm_state_type_name[5] = {
37 "",
38 "Powersave",
39 "Battery",
40 "Balanced",
41 "Performance",
42};
43
44static void radeon_dynpm_idle_work_handler(struct work_struct *work);
45static int radeon_debugfs_pm_init(struct radeon_device *rdev);
46static bool radeon_pm_in_vbl(struct radeon_device *rdev);
47static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
48static void radeon_pm_update_profile(struct radeon_device *rdev);
49static void radeon_pm_set_clocks(struct radeon_device *rdev);
50
51int radeon_pm_get_type_index(struct radeon_device *rdev,
52 enum radeon_pm_state_type ps_type,
53 int instance)
54{
55 int i;
56 int found_instance = -1;
57
58 for (i = 0; i < rdev->pm.num_power_states; i++) {
59 if (rdev->pm.power_state[i].type == ps_type) {
60 found_instance++;
61 if (found_instance == instance)
62 return i;
63 }
64 }
65
66 return rdev->pm.default_power_state_index;
67}
68
69void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
70{
71 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
72 mutex_lock(&rdev->pm.mutex);
73 if (power_supply_is_system_supplied() > 0)
74 rdev->pm.dpm.ac_power = true;
75 else
76 rdev->pm.dpm.ac_power = false;
77 if (rdev->family == CHIP_ARUBA) {
78 if (rdev->asic->dpm.enable_bapm)
79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
80 }
81 mutex_unlock(&rdev->pm.mutex);
82 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
83 if (rdev->pm.profile == PM_PROFILE_AUTO) {
84 mutex_lock(&rdev->pm.mutex);
85 radeon_pm_update_profile(rdev);
86 radeon_pm_set_clocks(rdev);
87 mutex_unlock(&rdev->pm.mutex);
88 }
89 }
90}
91
92static void radeon_pm_update_profile(struct radeon_device *rdev)
93{
94 switch (rdev->pm.profile) {
95 case PM_PROFILE_DEFAULT:
96 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
97 break;
98 case PM_PROFILE_AUTO:
99 if (power_supply_is_system_supplied() > 0) {
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
104 } else {
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
107 else
108 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
109 }
110 break;
111 case PM_PROFILE_LOW:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
116 break;
117 case PM_PROFILE_MID:
118 if (rdev->pm.active_crtc_count > 1)
119 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
120 else
121 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
122 break;
123 case PM_PROFILE_HIGH:
124 if (rdev->pm.active_crtc_count > 1)
125 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
126 else
127 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
128 break;
129 }
130
131 if (rdev->pm.active_crtc_count == 0) {
132 rdev->pm.requested_power_state_index =
133 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
134 rdev->pm.requested_clock_mode_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
136 } else {
137 rdev->pm.requested_power_state_index =
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
139 rdev->pm.requested_clock_mode_index =
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
141 }
142}
143
144static void radeon_unmap_vram_bos(struct radeon_device *rdev)
145{
146 struct radeon_bo *bo, *n;
147
148 if (list_empty(&rdev->gem.objects))
149 return;
150
151 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
152 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
153 ttm_bo_unmap_virtual(&bo->tbo);
154 }
155}
156
157static void radeon_sync_with_vblank(struct radeon_device *rdev)
158{
159 if (rdev->pm.active_crtcs) {
160 rdev->pm.vblank_sync = false;
161 wait_event_timeout(
162 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
163 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
164 }
165}
166
167static void radeon_set_power_state(struct radeon_device *rdev)
168{
169 u32 sclk, mclk;
170 bool misc_after = false;
171
172 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
173 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
174 return;
175
176 if (radeon_gui_idle(rdev)) {
177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
178 clock_info[rdev->pm.requested_clock_mode_index].sclk;
179 if (sclk > rdev->pm.default_sclk)
180 sclk = rdev->pm.default_sclk;
181
182
183
184
185
186 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
187 (rdev->family >= CHIP_BARTS) &&
188 rdev->pm.active_crtc_count &&
189 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
190 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
193 else
194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
195 clock_info[rdev->pm.requested_clock_mode_index].mclk;
196
197 if (mclk > rdev->pm.default_mclk)
198 mclk = rdev->pm.default_mclk;
199
200
201 if (sclk < rdev->pm.current_sclk)
202 misc_after = true;
203
204 radeon_sync_with_vblank(rdev);
205
206 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
207 if (!radeon_pm_in_vbl(rdev))
208 return;
209 }
210
211 radeon_pm_prepare(rdev);
212
213 if (!misc_after)
214
215 radeon_pm_misc(rdev);
216
217
218 if (sclk != rdev->pm.current_sclk) {
219 radeon_pm_debug_check_in_vbl(rdev, false);
220 radeon_set_engine_clock(rdev, sclk);
221 radeon_pm_debug_check_in_vbl(rdev, true);
222 rdev->pm.current_sclk = sclk;
223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
224 }
225
226
227 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
228 radeon_pm_debug_check_in_vbl(rdev, false);
229 radeon_set_memory_clock(rdev, mclk);
230 radeon_pm_debug_check_in_vbl(rdev, true);
231 rdev->pm.current_mclk = mclk;
232 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
233 }
234
235 if (misc_after)
236
237 radeon_pm_misc(rdev);
238
239 radeon_pm_finish(rdev);
240
241 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
242 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
243 } else
244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
245}
246
247static void radeon_pm_set_clocks(struct radeon_device *rdev)
248{
249 int i, r;
250
251
252 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
253 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
254 return;
255
256 mutex_lock(&rdev->ddev->struct_mutex);
257 down_write(&rdev->pm.mclk_lock);
258 mutex_lock(&rdev->ring_lock);
259
260
261 for (i = 0; i < RADEON_NUM_RINGS; i++) {
262 struct radeon_ring *ring = &rdev->ring[i];
263 if (!ring->ready) {
264 continue;
265 }
266 r = radeon_fence_wait_empty(rdev, i);
267 if (r) {
268
269 mutex_unlock(&rdev->ring_lock);
270 up_write(&rdev->pm.mclk_lock);
271 mutex_unlock(&rdev->ddev->struct_mutex);
272 return;
273 }
274 }
275
276 radeon_unmap_vram_bos(rdev);
277
278 if (rdev->irq.installed) {
279 for (i = 0; i < rdev->num_crtc; i++) {
280 if (rdev->pm.active_crtcs & (1 << i)) {
281 rdev->pm.req_vblank |= (1 << i);
282 drm_vblank_get(rdev->ddev, i);
283 }
284 }
285 }
286
287 radeon_set_power_state(rdev);
288
289 if (rdev->irq.installed) {
290 for (i = 0; i < rdev->num_crtc; i++) {
291 if (rdev->pm.req_vblank & (1 << i)) {
292 rdev->pm.req_vblank &= ~(1 << i);
293 drm_vblank_put(rdev->ddev, i);
294 }
295 }
296 }
297
298
299 radeon_update_bandwidth_info(rdev);
300 if (rdev->pm.active_crtc_count)
301 radeon_bandwidth_update(rdev);
302
303 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
304
305 mutex_unlock(&rdev->ring_lock);
306 up_write(&rdev->pm.mclk_lock);
307 mutex_unlock(&rdev->ddev->struct_mutex);
308}
309
310static void radeon_pm_print_states(struct radeon_device *rdev)
311{
312 int i, j;
313 struct radeon_power_state *power_state;
314 struct radeon_pm_clock_info *clock_info;
315
316 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
317 for (i = 0; i < rdev->pm.num_power_states; i++) {
318 power_state = &rdev->pm.power_state[i];
319 DRM_DEBUG_DRIVER("State %d: %s\n", i,
320 radeon_pm_state_type_name[power_state->type]);
321 if (i == rdev->pm.default_power_state_index)
322 DRM_DEBUG_DRIVER("\tDefault");
323 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
324 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
325 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
326 DRM_DEBUG_DRIVER("\tSingle display only\n");
327 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
328 for (j = 0; j < power_state->num_clock_modes; j++) {
329 clock_info = &(power_state->clock_info[j]);
330 if (rdev->flags & RADEON_IS_IGP)
331 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
332 j,
333 clock_info->sclk * 10);
334 else
335 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
336 j,
337 clock_info->sclk * 10,
338 clock_info->mclk * 10,
339 clock_info->voltage.voltage);
340 }
341 }
342}
343
344static ssize_t radeon_get_pm_profile(struct device *dev,
345 struct device_attribute *attr,
346 char *buf)
347{
348 struct drm_device *ddev = dev_get_drvdata(dev);
349 struct radeon_device *rdev = ddev->dev_private;
350 int cp = rdev->pm.profile;
351
352 return snprintf(buf, PAGE_SIZE, "%s\n",
353 (cp == PM_PROFILE_AUTO) ? "auto" :
354 (cp == PM_PROFILE_LOW) ? "low" :
355 (cp == PM_PROFILE_MID) ? "mid" :
356 (cp == PM_PROFILE_HIGH) ? "high" : "default");
357}
358
359static ssize_t radeon_set_pm_profile(struct device *dev,
360 struct device_attribute *attr,
361 const char *buf,
362 size_t count)
363{
364 struct drm_device *ddev = dev_get_drvdata(dev);
365 struct radeon_device *rdev = ddev->dev_private;
366
367
368 if ((rdev->flags & RADEON_IS_PX) &&
369 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
370 return -EINVAL;
371
372 mutex_lock(&rdev->pm.mutex);
373 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
374 if (strncmp("default", buf, strlen("default")) == 0)
375 rdev->pm.profile = PM_PROFILE_DEFAULT;
376 else if (strncmp("auto", buf, strlen("auto")) == 0)
377 rdev->pm.profile = PM_PROFILE_AUTO;
378 else if (strncmp("low", buf, strlen("low")) == 0)
379 rdev->pm.profile = PM_PROFILE_LOW;
380 else if (strncmp("mid", buf, strlen("mid")) == 0)
381 rdev->pm.profile = PM_PROFILE_MID;
382 else if (strncmp("high", buf, strlen("high")) == 0)
383 rdev->pm.profile = PM_PROFILE_HIGH;
384 else {
385 count = -EINVAL;
386 goto fail;
387 }
388 radeon_pm_update_profile(rdev);
389 radeon_pm_set_clocks(rdev);
390 } else
391 count = -EINVAL;
392
393fail:
394 mutex_unlock(&rdev->pm.mutex);
395
396 return count;
397}
398
399static ssize_t radeon_get_pm_method(struct device *dev,
400 struct device_attribute *attr,
401 char *buf)
402{
403 struct drm_device *ddev = dev_get_drvdata(dev);
404 struct radeon_device *rdev = ddev->dev_private;
405 int pm = rdev->pm.pm_method;
406
407 return snprintf(buf, PAGE_SIZE, "%s\n",
408 (pm == PM_METHOD_DYNPM) ? "dynpm" :
409 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
410}
411
412static ssize_t radeon_set_pm_method(struct device *dev,
413 struct device_attribute *attr,
414 const char *buf,
415 size_t count)
416{
417 struct drm_device *ddev = dev_get_drvdata(dev);
418 struct radeon_device *rdev = ddev->dev_private;
419
420
421 if ((rdev->flags & RADEON_IS_PX) &&
422 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
423 count = -EINVAL;
424 goto fail;
425 }
426
427
428 if (rdev->pm.pm_method == PM_METHOD_DPM) {
429 count = -EINVAL;
430 goto fail;
431 }
432
433 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
434 mutex_lock(&rdev->pm.mutex);
435 rdev->pm.pm_method = PM_METHOD_DYNPM;
436 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
437 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
438 mutex_unlock(&rdev->pm.mutex);
439 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
440 mutex_lock(&rdev->pm.mutex);
441
442 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
443 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
444 rdev->pm.pm_method = PM_METHOD_PROFILE;
445 mutex_unlock(&rdev->pm.mutex);
446 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
447 } else {
448 count = -EINVAL;
449 goto fail;
450 }
451 radeon_pm_compute_clocks(rdev);
452fail:
453 return count;
454}
455
456static ssize_t radeon_get_dpm_state(struct device *dev,
457 struct device_attribute *attr,
458 char *buf)
459{
460 struct drm_device *ddev = dev_get_drvdata(dev);
461 struct radeon_device *rdev = ddev->dev_private;
462 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
463
464 return snprintf(buf, PAGE_SIZE, "%s\n",
465 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
466 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
467}
468
469static ssize_t radeon_set_dpm_state(struct device *dev,
470 struct device_attribute *attr,
471 const char *buf,
472 size_t count)
473{
474 struct drm_device *ddev = dev_get_drvdata(dev);
475 struct radeon_device *rdev = ddev->dev_private;
476
477 mutex_lock(&rdev->pm.mutex);
478 if (strncmp("battery", buf, strlen("battery")) == 0)
479 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
480 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
481 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
482 else if (strncmp("performance", buf, strlen("performance")) == 0)
483 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
484 else {
485 mutex_unlock(&rdev->pm.mutex);
486 count = -EINVAL;
487 goto fail;
488 }
489 mutex_unlock(&rdev->pm.mutex);
490
491
492 if (!(rdev->flags & RADEON_IS_PX) ||
493 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
494 radeon_pm_compute_clocks(rdev);
495
496fail:
497 return count;
498}
499
500static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
501 struct device_attribute *attr,
502 char *buf)
503{
504 struct drm_device *ddev = dev_get_drvdata(dev);
505 struct radeon_device *rdev = ddev->dev_private;
506 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
507
508 if ((rdev->flags & RADEON_IS_PX) &&
509 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
510 return snprintf(buf, PAGE_SIZE, "off\n");
511
512 return snprintf(buf, PAGE_SIZE, "%s\n",
513 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
514 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
515}
516
517static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
518 struct device_attribute *attr,
519 const char *buf,
520 size_t count)
521{
522 struct drm_device *ddev = dev_get_drvdata(dev);
523 struct radeon_device *rdev = ddev->dev_private;
524 enum radeon_dpm_forced_level level;
525 int ret = 0;
526
527
528 if ((rdev->flags & RADEON_IS_PX) &&
529 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
530 return -EINVAL;
531
532 mutex_lock(&rdev->pm.mutex);
533 if (strncmp("low", buf, strlen("low")) == 0) {
534 level = RADEON_DPM_FORCED_LEVEL_LOW;
535 } else if (strncmp("high", buf, strlen("high")) == 0) {
536 level = RADEON_DPM_FORCED_LEVEL_HIGH;
537 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
538 level = RADEON_DPM_FORCED_LEVEL_AUTO;
539 } else {
540 count = -EINVAL;
541 goto fail;
542 }
543 if (rdev->asic->dpm.force_performance_level) {
544 if (rdev->pm.dpm.thermal_active) {
545 count = -EINVAL;
546 goto fail;
547 }
548 ret = radeon_dpm_force_performance_level(rdev, level);
549 if (ret)
550 count = -EINVAL;
551 }
552fail:
553 mutex_unlock(&rdev->pm.mutex);
554
555 return count;
556}
557
558static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
559 struct device_attribute *attr,
560 char *buf)
561{
562 struct radeon_device *rdev = dev_get_drvdata(dev);
563 u32 pwm_mode = 0;
564
565 if (rdev->asic->dpm.fan_ctrl_get_mode)
566 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
567
568
569 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
570}
571
572static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
573 struct device_attribute *attr,
574 const char *buf,
575 size_t count)
576{
577 struct radeon_device *rdev = dev_get_drvdata(dev);
578 int err;
579 int value;
580
581 if(!rdev->asic->dpm.fan_ctrl_set_mode)
582 return -EINVAL;
583
584 err = kstrtoint(buf, 10, &value);
585 if (err)
586 return err;
587
588 switch (value) {
589 case 1:
590 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
591 break;
592 default:
593 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
594 break;
595 }
596
597 return count;
598}
599
600static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
601 struct device_attribute *attr,
602 char *buf)
603{
604 return sprintf(buf, "%i\n", 0);
605}
606
607static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
608 struct device_attribute *attr,
609 char *buf)
610{
611 return sprintf(buf, "%i\n", 255);
612}
613
614static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
615 struct device_attribute *attr,
616 const char *buf, size_t count)
617{
618 struct radeon_device *rdev = dev_get_drvdata(dev);
619 int err;
620 u32 value;
621
622 err = kstrtou32(buf, 10, &value);
623 if (err)
624 return err;
625
626 value = (value * 100) / 255;
627
628 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
629 if (err)
630 return err;
631
632 return count;
633}
634
635static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
636 struct device_attribute *attr,
637 char *buf)
638{
639 struct radeon_device *rdev = dev_get_drvdata(dev);
640 int err;
641 u32 speed;
642
643 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
644 if (err)
645 return err;
646
647 speed = (speed * 255) / 100;
648
649 return sprintf(buf, "%i\n", speed);
650}
651
652static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
653static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
654static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
655static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
656 radeon_get_dpm_forced_performance_level,
657 radeon_set_dpm_forced_performance_level);
658
659static ssize_t radeon_hwmon_show_temp(struct device *dev,
660 struct device_attribute *attr,
661 char *buf)
662{
663 struct radeon_device *rdev = dev_get_drvdata(dev);
664 struct drm_device *ddev = rdev->ddev;
665 int temp;
666
667
668 if ((rdev->flags & RADEON_IS_PX) &&
669 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
670 return -EINVAL;
671
672 if (rdev->asic->pm.get_temperature)
673 temp = radeon_get_temperature(rdev);
674 else
675 temp = 0;
676
677 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
678}
679
680static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
681 struct device_attribute *attr,
682 char *buf)
683{
684 struct radeon_device *rdev = dev_get_drvdata(dev);
685 int hyst = to_sensor_dev_attr(attr)->index;
686 int temp;
687
688 if (hyst)
689 temp = rdev->pm.dpm.thermal.min_temp;
690 else
691 temp = rdev->pm.dpm.thermal.max_temp;
692
693 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
694}
695
696static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
697static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
698static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
699static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
700static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
701static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
702static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
703
704
705static struct attribute *hwmon_attributes[] = {
706 &sensor_dev_attr_temp1_input.dev_attr.attr,
707 &sensor_dev_attr_temp1_crit.dev_attr.attr,
708 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
709 &sensor_dev_attr_pwm1.dev_attr.attr,
710 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
711 &sensor_dev_attr_pwm1_min.dev_attr.attr,
712 &sensor_dev_attr_pwm1_max.dev_attr.attr,
713 NULL
714};
715
716static umode_t hwmon_attributes_visible(struct kobject *kobj,
717 struct attribute *attr, int index)
718{
719 struct device *dev = container_of(kobj, struct device, kobj);
720 struct radeon_device *rdev = dev_get_drvdata(dev);
721 umode_t effective_mode = attr->mode;
722
723
724 if (rdev->pm.pm_method != PM_METHOD_DPM &&
725 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
726 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
727 return 0;
728
729
730 if (rdev->pm.no_fan &&
731 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
732 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
733 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
734 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
735 return 0;
736
737
738 if ((!rdev->asic->dpm.get_fan_speed_percent &&
739 attr == &sensor_dev_attr_pwm1.dev_attr.attr) ||
740 (!rdev->asic->dpm.fan_ctrl_get_mode &&
741 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr))
742 effective_mode &= ~S_IRUGO;
743
744 if ((!rdev->asic->dpm.set_fan_speed_percent &&
745 attr == &sensor_dev_attr_pwm1.dev_attr.attr) ||
746 (!rdev->asic->dpm.fan_ctrl_set_mode &&
747 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr))
748 effective_mode &= ~S_IWUSR;
749
750
751 if ((!rdev->asic->dpm.set_fan_speed_percent &&
752 !rdev->asic->dpm.get_fan_speed_percent) &&
753 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
754 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
755 return 0;
756
757 return effective_mode;
758}
759
760static const struct attribute_group hwmon_attrgroup = {
761 .attrs = hwmon_attributes,
762 .is_visible = hwmon_attributes_visible,
763};
764
765static const struct attribute_group *hwmon_groups[] = {
766 &hwmon_attrgroup,
767 NULL
768};
769
770static int radeon_hwmon_init(struct radeon_device *rdev)
771{
772 int err = 0;
773
774 switch (rdev->pm.int_thermal_type) {
775 case THERMAL_TYPE_RV6XX:
776 case THERMAL_TYPE_RV770:
777 case THERMAL_TYPE_EVERGREEN:
778 case THERMAL_TYPE_NI:
779 case THERMAL_TYPE_SUMO:
780 case THERMAL_TYPE_SI:
781 case THERMAL_TYPE_CI:
782 case THERMAL_TYPE_KV:
783 if (rdev->asic->pm.get_temperature == NULL)
784 return err;
785 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
786 "radeon", rdev,
787 hwmon_groups);
788 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
789 err = PTR_ERR(rdev->pm.int_hwmon_dev);
790 dev_err(rdev->dev,
791 "Unable to register hwmon device: %d\n", err);
792 }
793 break;
794 default:
795 break;
796 }
797
798 return err;
799}
800
801static void radeon_hwmon_fini(struct radeon_device *rdev)
802{
803 if (rdev->pm.int_hwmon_dev)
804 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
805}
806
807static void radeon_dpm_thermal_work_handler(struct work_struct *work)
808{
809 struct radeon_device *rdev =
810 container_of(work, struct radeon_device,
811 pm.dpm.thermal.work);
812
813 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
814
815 if (!rdev->pm.dpm_enabled)
816 return;
817
818 if (rdev->asic->pm.get_temperature) {
819 int temp = radeon_get_temperature(rdev);
820
821 if (temp < rdev->pm.dpm.thermal.min_temp)
822
823 dpm_state = rdev->pm.dpm.user_state;
824 } else {
825 if (rdev->pm.dpm.thermal.high_to_low)
826
827 dpm_state = rdev->pm.dpm.user_state;
828 }
829 mutex_lock(&rdev->pm.mutex);
830 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
831 rdev->pm.dpm.thermal_active = true;
832 else
833 rdev->pm.dpm.thermal_active = false;
834 rdev->pm.dpm.state = dpm_state;
835 mutex_unlock(&rdev->pm.mutex);
836
837 radeon_pm_compute_clocks(rdev);
838}
839
840static bool radeon_dpm_single_display(struct radeon_device *rdev)
841{
842 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
843 true : false;
844
845
846 if (single_display && rdev->asic->dpm.vblank_too_short) {
847 if (radeon_dpm_vblank_too_short(rdev))
848 single_display = false;
849 }
850
851
852
853
854 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
855 single_display = false;
856
857 return single_display;
858}
859
860static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
861 enum radeon_pm_state_type dpm_state)
862{
863 int i;
864 struct radeon_ps *ps;
865 u32 ui_class;
866 bool single_display = radeon_dpm_single_display(rdev);
867
868
869
870
871 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
872 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
873
874 if (dpm_state == POWER_STATE_TYPE_BALANCED)
875 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
876
877restart_search:
878
879 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
880 ps = &rdev->pm.dpm.ps[i];
881 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
882 switch (dpm_state) {
883
884 case POWER_STATE_TYPE_BATTERY:
885 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
886 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
887 if (single_display)
888 return ps;
889 } else
890 return ps;
891 }
892 break;
893 case POWER_STATE_TYPE_BALANCED:
894 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
895 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
896 if (single_display)
897 return ps;
898 } else
899 return ps;
900 }
901 break;
902 case POWER_STATE_TYPE_PERFORMANCE:
903 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
904 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
905 if (single_display)
906 return ps;
907 } else
908 return ps;
909 }
910 break;
911
912 case POWER_STATE_TYPE_INTERNAL_UVD:
913 if (rdev->pm.dpm.uvd_ps)
914 return rdev->pm.dpm.uvd_ps;
915 else
916 break;
917 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
918 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
919 return ps;
920 break;
921 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
922 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
923 return ps;
924 break;
925 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
926 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
927 return ps;
928 break;
929 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
930 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
931 return ps;
932 break;
933 case POWER_STATE_TYPE_INTERNAL_BOOT:
934 return rdev->pm.dpm.boot_ps;
935 case POWER_STATE_TYPE_INTERNAL_THERMAL:
936 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
937 return ps;
938 break;
939 case POWER_STATE_TYPE_INTERNAL_ACPI:
940 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
941 return ps;
942 break;
943 case POWER_STATE_TYPE_INTERNAL_ULV:
944 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
945 return ps;
946 break;
947 case POWER_STATE_TYPE_INTERNAL_3DPERF:
948 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
949 return ps;
950 break;
951 default:
952 break;
953 }
954 }
955
956 switch (dpm_state) {
957 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
958 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
959 goto restart_search;
960 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
961 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
962 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
963 if (rdev->pm.dpm.uvd_ps) {
964 return rdev->pm.dpm.uvd_ps;
965 } else {
966 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
967 goto restart_search;
968 }
969 case POWER_STATE_TYPE_INTERNAL_THERMAL:
970 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
971 goto restart_search;
972 case POWER_STATE_TYPE_INTERNAL_ACPI:
973 dpm_state = POWER_STATE_TYPE_BATTERY;
974 goto restart_search;
975 case POWER_STATE_TYPE_BATTERY:
976 case POWER_STATE_TYPE_BALANCED:
977 case POWER_STATE_TYPE_INTERNAL_3DPERF:
978 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
979 goto restart_search;
980 default:
981 break;
982 }
983
984 return NULL;
985}
986
987static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
988{
989 int i;
990 struct radeon_ps *ps;
991 enum radeon_pm_state_type dpm_state;
992 int ret;
993 bool single_display = radeon_dpm_single_display(rdev);
994
995
996 if (!rdev->pm.dpm_enabled)
997 return;
998
999 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1000
1001 if ((!rdev->pm.dpm.thermal_active) &&
1002 (!rdev->pm.dpm.uvd_active))
1003 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1004 }
1005 dpm_state = rdev->pm.dpm.state;
1006
1007 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1008 if (ps)
1009 rdev->pm.dpm.requested_ps = ps;
1010 else
1011 return;
1012
1013
1014 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1015
1016 if (ps->vce_active != rdev->pm.dpm.vce_active)
1017 goto force;
1018
1019 if (rdev->pm.dpm.single_display != single_display)
1020 goto force;
1021 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1022
1023
1024
1025 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1026
1027 radeon_bandwidth_update(rdev);
1028
1029 radeon_dpm_display_configuration_changed(rdev);
1030 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1031 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1032 }
1033 return;
1034 } else {
1035
1036
1037
1038
1039 if (rdev->pm.dpm.new_active_crtcs ==
1040 rdev->pm.dpm.current_active_crtcs) {
1041 return;
1042 } else {
1043 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1044 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1045
1046 radeon_bandwidth_update(rdev);
1047
1048 radeon_dpm_display_configuration_changed(rdev);
1049 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1050 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1051 return;
1052 }
1053 }
1054 }
1055 }
1056
1057force:
1058 if (radeon_dpm == 1) {
1059 printk("switching from power state:\n");
1060 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1061 printk("switching to power state:\n");
1062 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1063 }
1064
1065 mutex_lock(&rdev->ddev->struct_mutex);
1066 down_write(&rdev->pm.mclk_lock);
1067 mutex_lock(&rdev->ring_lock);
1068
1069
1070 ps->vce_active = rdev->pm.dpm.vce_active;
1071
1072 ret = radeon_dpm_pre_set_power_state(rdev);
1073 if (ret)
1074 goto done;
1075
1076
1077 radeon_bandwidth_update(rdev);
1078
1079 radeon_dpm_display_configuration_changed(rdev);
1080
1081 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1082 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1083 rdev->pm.dpm.single_display = single_display;
1084
1085
1086 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1087 struct radeon_ring *ring = &rdev->ring[i];
1088 if (ring->ready)
1089 radeon_fence_wait_empty(rdev, i);
1090 }
1091
1092
1093 radeon_dpm_set_power_state(rdev);
1094
1095
1096 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1097
1098 radeon_dpm_post_set_power_state(rdev);
1099
1100 if (rdev->asic->dpm.force_performance_level) {
1101 if (rdev->pm.dpm.thermal_active) {
1102 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1103
1104 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1105
1106 rdev->pm.dpm.forced_level = level;
1107 } else {
1108
1109 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1110 }
1111 }
1112
1113done:
1114 mutex_unlock(&rdev->ring_lock);
1115 up_write(&rdev->pm.mclk_lock);
1116 mutex_unlock(&rdev->ddev->struct_mutex);
1117}
1118
1119void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1120{
1121 enum radeon_pm_state_type dpm_state;
1122
1123 if (rdev->asic->dpm.powergate_uvd) {
1124 mutex_lock(&rdev->pm.mutex);
1125
1126
1127 enable |= rdev->pm.dpm.sd > 0;
1128 enable |= rdev->pm.dpm.hd > 0;
1129
1130 radeon_dpm_powergate_uvd(rdev, !enable);
1131 mutex_unlock(&rdev->pm.mutex);
1132 } else {
1133 if (enable) {
1134 mutex_lock(&rdev->pm.mutex);
1135 rdev->pm.dpm.uvd_active = true;
1136
1137#if 0
1138 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1139 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1140 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1141 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1142 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1143 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1144 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1145 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1146 else
1147#endif
1148 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1149 rdev->pm.dpm.state = dpm_state;
1150 mutex_unlock(&rdev->pm.mutex);
1151 } else {
1152 mutex_lock(&rdev->pm.mutex);
1153 rdev->pm.dpm.uvd_active = false;
1154 mutex_unlock(&rdev->pm.mutex);
1155 }
1156
1157 radeon_pm_compute_clocks(rdev);
1158 }
1159}
1160
1161void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1162{
1163 if (enable) {
1164 mutex_lock(&rdev->pm.mutex);
1165 rdev->pm.dpm.vce_active = true;
1166
1167 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1168 mutex_unlock(&rdev->pm.mutex);
1169 } else {
1170 mutex_lock(&rdev->pm.mutex);
1171 rdev->pm.dpm.vce_active = false;
1172 mutex_unlock(&rdev->pm.mutex);
1173 }
1174
1175 radeon_pm_compute_clocks(rdev);
1176}
1177
1178static void radeon_pm_suspend_old(struct radeon_device *rdev)
1179{
1180 mutex_lock(&rdev->pm.mutex);
1181 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1182 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1183 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1184 }
1185 mutex_unlock(&rdev->pm.mutex);
1186
1187 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1188}
1189
1190static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1191{
1192 mutex_lock(&rdev->pm.mutex);
1193
1194 radeon_dpm_disable(rdev);
1195
1196 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1197 rdev->pm.dpm_enabled = false;
1198 mutex_unlock(&rdev->pm.mutex);
1199}
1200
1201void radeon_pm_suspend(struct radeon_device *rdev)
1202{
1203 if (rdev->pm.pm_method == PM_METHOD_DPM)
1204 radeon_pm_suspend_dpm(rdev);
1205 else
1206 radeon_pm_suspend_old(rdev);
1207}
1208
1209static void radeon_pm_resume_old(struct radeon_device *rdev)
1210{
1211
1212 if ((rdev->family >= CHIP_BARTS) &&
1213 (rdev->family <= CHIP_CAYMAN) &&
1214 rdev->mc_fw) {
1215 if (rdev->pm.default_vddc)
1216 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1217 SET_VOLTAGE_TYPE_ASIC_VDDC);
1218 if (rdev->pm.default_vddci)
1219 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1220 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1221 if (rdev->pm.default_sclk)
1222 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1223 if (rdev->pm.default_mclk)
1224 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1225 }
1226
1227 mutex_lock(&rdev->pm.mutex);
1228 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1229 rdev->pm.current_clock_mode_index = 0;
1230 rdev->pm.current_sclk = rdev->pm.default_sclk;
1231 rdev->pm.current_mclk = rdev->pm.default_mclk;
1232 if (rdev->pm.power_state) {
1233 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1234 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1235 }
1236 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1237 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1238 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1239 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1240 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1241 }
1242 mutex_unlock(&rdev->pm.mutex);
1243 radeon_pm_compute_clocks(rdev);
1244}
1245
1246static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1247{
1248 int ret;
1249
1250
1251 mutex_lock(&rdev->pm.mutex);
1252 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1253 radeon_dpm_setup_asic(rdev);
1254 ret = radeon_dpm_enable(rdev);
1255 mutex_unlock(&rdev->pm.mutex);
1256 if (ret)
1257 goto dpm_resume_fail;
1258 rdev->pm.dpm_enabled = true;
1259 return;
1260
1261dpm_resume_fail:
1262 DRM_ERROR("radeon: dpm resume failed\n");
1263 if ((rdev->family >= CHIP_BARTS) &&
1264 (rdev->family <= CHIP_CAYMAN) &&
1265 rdev->mc_fw) {
1266 if (rdev->pm.default_vddc)
1267 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1268 SET_VOLTAGE_TYPE_ASIC_VDDC);
1269 if (rdev->pm.default_vddci)
1270 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1271 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1272 if (rdev->pm.default_sclk)
1273 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1274 if (rdev->pm.default_mclk)
1275 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1276 }
1277}
1278
1279void radeon_pm_resume(struct radeon_device *rdev)
1280{
1281 if (rdev->pm.pm_method == PM_METHOD_DPM)
1282 radeon_pm_resume_dpm(rdev);
1283 else
1284 radeon_pm_resume_old(rdev);
1285}
1286
1287static int radeon_pm_init_old(struct radeon_device *rdev)
1288{
1289 int ret;
1290
1291 rdev->pm.profile = PM_PROFILE_DEFAULT;
1292 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1293 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1294 rdev->pm.dynpm_can_upclock = true;
1295 rdev->pm.dynpm_can_downclock = true;
1296 rdev->pm.default_sclk = rdev->clock.default_sclk;
1297 rdev->pm.default_mclk = rdev->clock.default_mclk;
1298 rdev->pm.current_sclk = rdev->clock.default_sclk;
1299 rdev->pm.current_mclk = rdev->clock.default_mclk;
1300 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1301
1302 if (rdev->bios) {
1303 if (rdev->is_atom_bios)
1304 radeon_atombios_get_power_modes(rdev);
1305 else
1306 radeon_combios_get_power_modes(rdev);
1307 radeon_pm_print_states(rdev);
1308 radeon_pm_init_profile(rdev);
1309
1310 if ((rdev->family >= CHIP_BARTS) &&
1311 (rdev->family <= CHIP_CAYMAN) &&
1312 rdev->mc_fw) {
1313 if (rdev->pm.default_vddc)
1314 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1315 SET_VOLTAGE_TYPE_ASIC_VDDC);
1316 if (rdev->pm.default_vddci)
1317 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1318 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1319 if (rdev->pm.default_sclk)
1320 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1321 if (rdev->pm.default_mclk)
1322 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1323 }
1324 }
1325
1326
1327 ret = radeon_hwmon_init(rdev);
1328 if (ret)
1329 return ret;
1330
1331 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1332
1333 if (rdev->pm.num_power_states > 1) {
1334
1335 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1336 if (ret)
1337 DRM_ERROR("failed to create device file for power profile\n");
1338 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1339 if (ret)
1340 DRM_ERROR("failed to create device file for power method\n");
1341
1342 if (radeon_debugfs_pm_init(rdev)) {
1343 DRM_ERROR("Failed to register debugfs file for PM!\n");
1344 }
1345
1346 DRM_INFO("radeon: power management initialized\n");
1347 }
1348
1349 return 0;
1350}
1351
1352static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1353{
1354 int i;
1355
1356 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1357 printk("== power state %d ==\n", i);
1358 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1359 }
1360}
1361
1362static int radeon_pm_init_dpm(struct radeon_device *rdev)
1363{
1364 int ret;
1365
1366
1367 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1368 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1369 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1370 rdev->pm.default_sclk = rdev->clock.default_sclk;
1371 rdev->pm.default_mclk = rdev->clock.default_mclk;
1372 rdev->pm.current_sclk = rdev->clock.default_sclk;
1373 rdev->pm.current_mclk = rdev->clock.default_mclk;
1374 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1375
1376 if (rdev->bios && rdev->is_atom_bios)
1377 radeon_atombios_get_power_modes(rdev);
1378 else
1379 return -EINVAL;
1380
1381
1382 ret = radeon_hwmon_init(rdev);
1383 if (ret)
1384 return ret;
1385
1386 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1387 mutex_lock(&rdev->pm.mutex);
1388 radeon_dpm_init(rdev);
1389 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1390 if (radeon_dpm == 1)
1391 radeon_dpm_print_power_states(rdev);
1392 radeon_dpm_setup_asic(rdev);
1393 ret = radeon_dpm_enable(rdev);
1394 mutex_unlock(&rdev->pm.mutex);
1395 if (ret)
1396 goto dpm_failed;
1397 rdev->pm.dpm_enabled = true;
1398
1399 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1400 if (ret)
1401 DRM_ERROR("failed to create device file for dpm state\n");
1402 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1403 if (ret)
1404 DRM_ERROR("failed to create device file for dpm state\n");
1405
1406 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1407 if (ret)
1408 DRM_ERROR("failed to create device file for power profile\n");
1409 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1410 if (ret)
1411 DRM_ERROR("failed to create device file for power method\n");
1412
1413 if (radeon_debugfs_pm_init(rdev)) {
1414 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1415 }
1416
1417 DRM_INFO("radeon: dpm initialized\n");
1418
1419 return 0;
1420
1421dpm_failed:
1422 rdev->pm.dpm_enabled = false;
1423 if ((rdev->family >= CHIP_BARTS) &&
1424 (rdev->family <= CHIP_CAYMAN) &&
1425 rdev->mc_fw) {
1426 if (rdev->pm.default_vddc)
1427 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1428 SET_VOLTAGE_TYPE_ASIC_VDDC);
1429 if (rdev->pm.default_vddci)
1430 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1431 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1432 if (rdev->pm.default_sclk)
1433 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1434 if (rdev->pm.default_mclk)
1435 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1436 }
1437 DRM_ERROR("radeon: dpm initialization failed\n");
1438 return ret;
1439}
1440
1441struct radeon_dpm_quirk {
1442 u32 chip_vendor;
1443 u32 chip_device;
1444 u32 subsys_vendor;
1445 u32 subsys_device;
1446};
1447
1448
1449static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1450
1451 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1452
1453 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1454 { 0, 0, 0, 0 },
1455};
1456
1457int radeon_pm_init(struct radeon_device *rdev)
1458{
1459 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1460 bool disable_dpm = false;
1461
1462
1463 while (p && p->chip_device != 0) {
1464 if (rdev->pdev->vendor == p->chip_vendor &&
1465 rdev->pdev->device == p->chip_device &&
1466 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1467 rdev->pdev->subsystem_device == p->subsys_device) {
1468 disable_dpm = true;
1469 break;
1470 }
1471 ++p;
1472 }
1473
1474
1475 switch (rdev->family) {
1476 case CHIP_RV610:
1477 case CHIP_RV630:
1478 case CHIP_RV620:
1479 case CHIP_RV635:
1480 case CHIP_RV670:
1481 case CHIP_RS780:
1482 case CHIP_RS880:
1483 case CHIP_RV770:
1484
1485 if (!rdev->rlc_fw)
1486 rdev->pm.pm_method = PM_METHOD_PROFILE;
1487 else if ((rdev->family >= CHIP_RV770) &&
1488 (!(rdev->flags & RADEON_IS_IGP)) &&
1489 (!rdev->smc_fw))
1490 rdev->pm.pm_method = PM_METHOD_PROFILE;
1491 else if (radeon_dpm == 1)
1492 rdev->pm.pm_method = PM_METHOD_DPM;
1493 else
1494 rdev->pm.pm_method = PM_METHOD_PROFILE;
1495 break;
1496 case CHIP_RV730:
1497 case CHIP_RV710:
1498 case CHIP_RV740:
1499 case CHIP_CEDAR:
1500 case CHIP_REDWOOD:
1501 case CHIP_JUNIPER:
1502 case CHIP_CYPRESS:
1503 case CHIP_HEMLOCK:
1504 case CHIP_PALM:
1505 case CHIP_SUMO:
1506 case CHIP_SUMO2:
1507 case CHIP_BARTS:
1508 case CHIP_TURKS:
1509 case CHIP_CAICOS:
1510 case CHIP_CAYMAN:
1511 case CHIP_ARUBA:
1512 case CHIP_TAHITI:
1513 case CHIP_PITCAIRN:
1514 case CHIP_VERDE:
1515 case CHIP_OLAND:
1516 case CHIP_HAINAN:
1517 case CHIP_BONAIRE:
1518 case CHIP_KABINI:
1519 case CHIP_KAVERI:
1520 case CHIP_HAWAII:
1521 case CHIP_MULLINS:
1522
1523 if (!rdev->rlc_fw)
1524 rdev->pm.pm_method = PM_METHOD_PROFILE;
1525 else if ((rdev->family >= CHIP_RV770) &&
1526 (!(rdev->flags & RADEON_IS_IGP)) &&
1527 (!rdev->smc_fw))
1528 rdev->pm.pm_method = PM_METHOD_PROFILE;
1529 else if (disable_dpm && (radeon_dpm == -1))
1530 rdev->pm.pm_method = PM_METHOD_PROFILE;
1531 else if (radeon_dpm == 0)
1532 rdev->pm.pm_method = PM_METHOD_PROFILE;
1533 else
1534 rdev->pm.pm_method = PM_METHOD_DPM;
1535 break;
1536 default:
1537
1538 rdev->pm.pm_method = PM_METHOD_PROFILE;
1539 break;
1540 }
1541
1542 if (rdev->pm.pm_method == PM_METHOD_DPM)
1543 return radeon_pm_init_dpm(rdev);
1544 else
1545 return radeon_pm_init_old(rdev);
1546}
1547
1548int radeon_pm_late_init(struct radeon_device *rdev)
1549{
1550 int ret = 0;
1551
1552 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1553 mutex_lock(&rdev->pm.mutex);
1554 ret = radeon_dpm_late_enable(rdev);
1555 mutex_unlock(&rdev->pm.mutex);
1556 }
1557 return ret;
1558}
1559
1560static void radeon_pm_fini_old(struct radeon_device *rdev)
1561{
1562 if (rdev->pm.num_power_states > 1) {
1563 mutex_lock(&rdev->pm.mutex);
1564 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1565 rdev->pm.profile = PM_PROFILE_DEFAULT;
1566 radeon_pm_update_profile(rdev);
1567 radeon_pm_set_clocks(rdev);
1568 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1569
1570 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1571 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1572 radeon_pm_set_clocks(rdev);
1573 }
1574 mutex_unlock(&rdev->pm.mutex);
1575
1576 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1577
1578 device_remove_file(rdev->dev, &dev_attr_power_profile);
1579 device_remove_file(rdev->dev, &dev_attr_power_method);
1580 }
1581
1582 radeon_hwmon_fini(rdev);
1583 kfree(rdev->pm.power_state);
1584}
1585
1586static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1587{
1588 if (rdev->pm.num_power_states > 1) {
1589 mutex_lock(&rdev->pm.mutex);
1590 radeon_dpm_disable(rdev);
1591 mutex_unlock(&rdev->pm.mutex);
1592
1593 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1594 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1595
1596 device_remove_file(rdev->dev, &dev_attr_power_profile);
1597 device_remove_file(rdev->dev, &dev_attr_power_method);
1598 }
1599 radeon_dpm_fini(rdev);
1600
1601 radeon_hwmon_fini(rdev);
1602 kfree(rdev->pm.power_state);
1603}
1604
1605void radeon_pm_fini(struct radeon_device *rdev)
1606{
1607 if (rdev->pm.pm_method == PM_METHOD_DPM)
1608 radeon_pm_fini_dpm(rdev);
1609 else
1610 radeon_pm_fini_old(rdev);
1611}
1612
1613static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1614{
1615 struct drm_device *ddev = rdev->ddev;
1616 struct drm_crtc *crtc;
1617 struct radeon_crtc *radeon_crtc;
1618
1619 if (rdev->pm.num_power_states < 2)
1620 return;
1621
1622 mutex_lock(&rdev->pm.mutex);
1623
1624 rdev->pm.active_crtcs = 0;
1625 rdev->pm.active_crtc_count = 0;
1626 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1627 list_for_each_entry(crtc,
1628 &ddev->mode_config.crtc_list, head) {
1629 radeon_crtc = to_radeon_crtc(crtc);
1630 if (radeon_crtc->enabled) {
1631 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1632 rdev->pm.active_crtc_count++;
1633 }
1634 }
1635 }
1636
1637 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1638 radeon_pm_update_profile(rdev);
1639 radeon_pm_set_clocks(rdev);
1640 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1641 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1642 if (rdev->pm.active_crtc_count > 1) {
1643 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1644 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1645
1646 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1647 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1648 radeon_pm_get_dynpm_state(rdev);
1649 radeon_pm_set_clocks(rdev);
1650
1651 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1652 }
1653 } else if (rdev->pm.active_crtc_count == 1) {
1654
1655
1656 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1657 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1658 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1659 radeon_pm_get_dynpm_state(rdev);
1660 radeon_pm_set_clocks(rdev);
1661
1662 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1663 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1664 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1665 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1666 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1667 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1668 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1669 }
1670 } else {
1671 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1672 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1673
1674 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1675 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1676 radeon_pm_get_dynpm_state(rdev);
1677 radeon_pm_set_clocks(rdev);
1678 }
1679 }
1680 }
1681 }
1682
1683 mutex_unlock(&rdev->pm.mutex);
1684}
1685
1686static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1687{
1688 struct drm_device *ddev = rdev->ddev;
1689 struct drm_crtc *crtc;
1690 struct radeon_crtc *radeon_crtc;
1691
1692 if (!rdev->pm.dpm_enabled)
1693 return;
1694
1695 mutex_lock(&rdev->pm.mutex);
1696
1697
1698 rdev->pm.dpm.new_active_crtcs = 0;
1699 rdev->pm.dpm.new_active_crtc_count = 0;
1700 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1701 list_for_each_entry(crtc,
1702 &ddev->mode_config.crtc_list, head) {
1703 radeon_crtc = to_radeon_crtc(crtc);
1704 if (crtc->enabled) {
1705 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1706 rdev->pm.dpm.new_active_crtc_count++;
1707 }
1708 }
1709 }
1710
1711
1712 if (power_supply_is_system_supplied() > 0)
1713 rdev->pm.dpm.ac_power = true;
1714 else
1715 rdev->pm.dpm.ac_power = false;
1716
1717 radeon_dpm_change_power_state_locked(rdev);
1718
1719 mutex_unlock(&rdev->pm.mutex);
1720
1721}
1722
1723void radeon_pm_compute_clocks(struct radeon_device *rdev)
1724{
1725 if (rdev->pm.pm_method == PM_METHOD_DPM)
1726 radeon_pm_compute_clocks_dpm(rdev);
1727 else
1728 radeon_pm_compute_clocks_old(rdev);
1729}
1730
1731static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1732{
1733 int crtc, vpos, hpos, vbl_status;
1734 bool in_vbl = true;
1735
1736
1737
1738
1739 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1740 if (rdev->pm.active_crtcs & (1 << crtc)) {
1741 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1742 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1743 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1744 in_vbl = false;
1745 }
1746 }
1747
1748 return in_vbl;
1749}
1750
1751static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1752{
1753 u32 stat_crtc = 0;
1754 bool in_vbl = radeon_pm_in_vbl(rdev);
1755
1756 if (in_vbl == false)
1757 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1758 finish ? "exit" : "entry");
1759 return in_vbl;
1760}
1761
1762static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1763{
1764 struct radeon_device *rdev;
1765 int resched;
1766 rdev = container_of(work, struct radeon_device,
1767 pm.dynpm_idle_work.work);
1768
1769 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1770 mutex_lock(&rdev->pm.mutex);
1771 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1772 int not_processed = 0;
1773 int i;
1774
1775 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1776 struct radeon_ring *ring = &rdev->ring[i];
1777
1778 if (ring->ready) {
1779 not_processed += radeon_fence_count_emitted(rdev, i);
1780 if (not_processed >= 3)
1781 break;
1782 }
1783 }
1784
1785 if (not_processed >= 3) {
1786 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1787 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1788 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1789 rdev->pm.dynpm_can_upclock) {
1790 rdev->pm.dynpm_planned_action =
1791 DYNPM_ACTION_UPCLOCK;
1792 rdev->pm.dynpm_action_timeout = jiffies +
1793 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1794 }
1795 } else if (not_processed == 0) {
1796 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1797 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1798 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1799 rdev->pm.dynpm_can_downclock) {
1800 rdev->pm.dynpm_planned_action =
1801 DYNPM_ACTION_DOWNCLOCK;
1802 rdev->pm.dynpm_action_timeout = jiffies +
1803 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1804 }
1805 }
1806
1807
1808
1809
1810 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1811 jiffies > rdev->pm.dynpm_action_timeout) {
1812 radeon_pm_get_dynpm_state(rdev);
1813 radeon_pm_set_clocks(rdev);
1814 }
1815
1816 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1817 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1818 }
1819 mutex_unlock(&rdev->pm.mutex);
1820 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1821}
1822
1823
1824
1825
1826#if defined(CONFIG_DEBUG_FS)
1827
1828static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1829{
1830 struct drm_info_node *node = (struct drm_info_node *) m->private;
1831 struct drm_device *dev = node->minor->dev;
1832 struct radeon_device *rdev = dev->dev_private;
1833 struct drm_device *ddev = rdev->ddev;
1834
1835 if ((rdev->flags & RADEON_IS_PX) &&
1836 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1837 seq_printf(m, "PX asic powered off\n");
1838 } else if (rdev->pm.dpm_enabled) {
1839 mutex_lock(&rdev->pm.mutex);
1840 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1841 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1842 else
1843 seq_printf(m, "Debugfs support not implemented for this asic\n");
1844 mutex_unlock(&rdev->pm.mutex);
1845 } else {
1846 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1847
1848 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1849 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1850 else
1851 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1852 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1853 if (rdev->asic->pm.get_memory_clock)
1854 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1855 if (rdev->pm.current_vddc)
1856 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1857 if (rdev->asic->pm.get_pcie_lanes)
1858 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1859 }
1860
1861 return 0;
1862}
1863
1864static struct drm_info_list radeon_pm_info_list[] = {
1865 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1866};
1867#endif
1868
1869static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1870{
1871#if defined(CONFIG_DEBUG_FS)
1872 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1873#else
1874 return 0;
1875#endif
1876}
1877
