1/* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#ifndef DRM_TEGRA_SOR_H 10#define DRM_TEGRA_SOR_H 11 12#define SOR_CTXSW 0x00 13 14#define SOR_SUPER_STATE_0 0x01 15 16#define SOR_SUPER_STATE_1 0x02 17#define SOR_SUPER_STATE_ATTACHED (1 << 3) 18#define SOR_SUPER_STATE_MODE_NORMAL (1 << 2) 19#define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0) 20#define SOR_SUPER_STATE_HEAD_MODE_AWAKE (2 << 0) 21#define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0) 22#define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0) 23 24#define SOR_STATE_0 0x03 25 26#define SOR_STATE_1 0x04 27#define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17) 28#define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444 (0x2 << 17) 29#define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 (0x5 << 17) 30#define SOR_STATE_ASY_VSYNCPOL (1 << 13) 31#define SOR_STATE_ASY_HSYNCPOL (1 << 12) 32#define SOR_STATE_ASY_PROTOCOL_MASK (0xf << 8) 33#define SOR_STATE_ASY_PROTOCOL_CUSTOM (0xf << 8) 34#define SOR_STATE_ASY_PROTOCOL_DP_A (0x8 << 8) 35#define SOR_STATE_ASY_PROTOCOL_DP_B (0x9 << 8) 36#define SOR_STATE_ASY_PROTOCOL_LVDS (0x0 << 8) 37#define SOR_STATE_ASY_CRC_MODE_MASK (0x3 << 6) 38#define SOR_STATE_ASY_CRC_MODE_NON_ACTIVE (0x2 << 6) 39#define SOR_STATE_ASY_CRC_MODE_COMPLETE (0x1 << 6) 40#define SOR_STATE_ASY_CRC_MODE_ACTIVE (0x0 << 6) 41#define SOR_STATE_ASY_OWNER(x) (((x) & 0xf) << 0) 42 43#define SOR_HEAD_STATE_0(x) (0x05 + (x)) 44#define SOR_HEAD_STATE_1(x) (0x07 + (x)) 45#define SOR_HEAD_STATE_2(x) (0x09 + (x)) 46#define SOR_HEAD_STATE_3(x) (0x0b + (x)) 47#define SOR_HEAD_STATE_4(x) (0x0d + (x)) 48#define SOR_HEAD_STATE_5(x) (0x0f + (x)) 49#define SOR_CRC_CNTRL 0x11 50#define SOR_CRC_CNTRL_ENABLE (1 << 0) 51#define SOR_DP_DEBUG_MVID 0x12 52 53#define SOR_CLK_CNTRL 0x13 54#define SOR_CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2) 55#define SOR_CLK_CNTRL_DP_LINK_SPEED(x) (((x) & 0x1f) << 2) 56#define SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62 (0x06 << 2) 57#define SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70 (0x0a << 2) 58#define SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40 (0x14 << 2) 59#define SOR_CLK_CNTRL_DP_CLK_SEL_MASK (3 << 0) 60#define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0 << 0) 61#define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1 << 0) 62#define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK (2 << 0) 63#define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK (3 << 0) 64 65#define SOR_CAP 0x14 66 67#define SOR_PWR 0x15 68#define SOR_PWR_TRIGGER (1 << 31) 69#define SOR_PWR_MODE_SAFE (1 << 28) 70#define SOR_PWR_NORMAL_STATE_PU (1 << 0) 71 72#define SOR_TEST 0x16 73#define SOR_TEST_CRC_POST_SERIALIZE (1 << 23) 74#define SOR_TEST_ATTACHED (1 << 10) 75#define SOR_TEST_HEAD_MODE_MASK (3 << 8) 76#define SOR_TEST_HEAD_MODE_AWAKE (2 << 8) 77 78#define SOR_PLL_0 0x17 79#define SOR_PLL_0_ICHPMP_MASK (0xf << 24) 80#define SOR_PLL_0_ICHPMP(x) (((x) & 0xf) << 24) 81#define SOR_PLL_0_VCOCAP_MASK (0xf << 8) 82#define SOR_PLL_0_VCOCAP(x) (((x) & 0xf) << 8) 83#define SOR_PLL_0_VCOCAP_RST SOR_PLL_0_VCOCAP(3) 84#define SOR_PLL_0_PLLREG_MASK (0x3 << 6) 85#define SOR_PLL_0_PLLREG_LEVEL(x) (((x) & 0x3) << 6) 86#define SOR_PLL_0_PLLREG_LEVEL_V25 SOR_PLL_0_PLLREG_LEVEL(0) 87#define SOR_PLL_0_PLLREG_LEVEL_V15 SOR_PLL_0_PLLREG_LEVEL(1) 88#define SOR_PLL_0_PLLREG_LEVEL_V35 SOR_PLL_0_PLLREG_LEVEL(2) 89#define SOR_PLL_0_PLLREG_LEVEL_V45 SOR_PLL_0_PLLREG_LEVEL(3) 90#define SOR_PLL_0_PULLDOWN (1 << 5) 91#define SOR_PLL_0_RESISTOR_EXT (1 << 4) 92#define SOR_PLL_0_VCOPD (1 << 2) 93#define SOR_PLL_0_POWER_OFF (1 << 0) 94 95#define SOR_PLL_1 0x18 96/* XXX: read-only bit? */ 97#define SOR_PLL_1_TERM_COMPOUT (1 << 15) 98#define SOR_PLL_1_TMDS_TERM (1 << 8) 99 100#define SOR_PLL_2 0x19 101#define SOR_PLL_2_LVDS_ENABLE (1 << 25) 102#define SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE (1 << 24) 103#define SOR_PLL_2_PORT_POWERDOWN (1 << 23) 104#define SOR_PLL_2_BANDGAP_POWERDOWN (1 << 22) 105#define SOR_PLL_2_POWERDOWN_OVERRIDE (1 << 18) 106#define SOR_PLL_2_SEQ_PLLCAPPD (1 << 17) 107 108#define SOR_PLL_3 0x1a 109#define SOR_PLL_3_PLL_VDD_MODE_V1_8 (0 << 13) 110#define SOR_PLL_3_PLL_VDD_MODE_V3_3 (1 << 13) 111 112#define SOR_CSTM 0x1b 113#define SOR_CSTM_LVDS (1 << 16) 114#define SOR_CSTM_LINK_ACT_B (1 << 15) 115#define SOR_CSTM_LINK_ACT_A (1 << 14) 116#define SOR_CSTM_UPPER (1 << 11) 117 118#define SOR_LVDS 0x1c 119#define SOR_CRC_A 0x1d 120#define SOR_CRC_A_VALID (1 << 0) 121#define SOR_CRC_A_RESET (1 << 0) 122#define SOR_CRC_B 0x1e 123#define SOR_BLANK 0x1f 124#define SOR_SEQ_CTL 0x20 125 126#define SOR_LANE_SEQ_CTL 0x21 127#define SOR_LANE_SEQ_CTL_TRIGGER (1 << 31) 128#define SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20) 129#define SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20) 130#define SOR_LANE_SEQ_CTL_POWER_STATE_UP (0 << 16) 131#define SOR_LANE_SEQ_CTL_POWER_STATE_DOWN (1 << 16) 132 133#define SOR_SEQ_INST(x) (0x22 + (x)) 134 135#define SOR_PWM_DIV 0x32 136#define SOR_PWM_DIV_MASK 0xffffff 137 138#define SOR_PWM_CTL 0x33 139#define SOR_PWM_CTL_TRIGGER (1 << 31) 140#define SOR_PWM_CTL_CLK_SEL (1 << 30) 141#define SOR_PWM_CTL_DUTY_CYCLE_MASK 0xffffff 142 143#define SOR_VCRC_A_0 0x34 144#define SOR_VCRC_A_1 0x35 145#define SOR_VCRC_B_0 0x36 146#define SOR_VCRC_B_1 0x37 147#define SOR_CCRC_A_0 0x38 148#define SOR_CCRC_A_1 0x39 149#define SOR_CCRC_B_0 0x3a 150#define SOR_CCRC_B_1 0x3b 151#define SOR_EDATA_A_0 0x3c 152#define SOR_EDATA_A_1 0x3d 153#define SOR_EDATA_B_0 0x3e 154#define SOR_EDATA_B_1 0x3f 155#define SOR_COUNT_A_0 0x40 156#define SOR_COUNT_A_1 0x41 157#define SOR_COUNT_B_0 0x42 158#define SOR_COUNT_B_1 0x43 159#define SOR_DEBUG_A_0 0x44 160#define SOR_DEBUG_A_1 0x45 161#define SOR_DEBUG_B_0 0x46 162#define SOR_DEBUG_B_1 0x47 163#define SOR_TRIG 0x48 164#define SOR_MSCHECK 0x49 165#define SOR_XBAR_CTRL 0x4a 166#define SOR_XBAR_POL 0x4b 167 168#define SOR_DP_LINKCTL_0 0x4c 169#define SOR_DP_LINKCTL_LANE_COUNT_MASK (0x1f << 16) 170#define SOR_DP_LINKCTL_LANE_COUNT(x) (((1 << (x)) - 1) << 16) 171#define SOR_DP_LINKCTL_ENHANCED_FRAME (1 << 14) 172#define SOR_DP_LINKCTL_TU_SIZE_MASK (0x7f << 2) 173#define SOR_DP_LINKCTL_TU_SIZE(x) (((x) & 0x7f) << 2) 174#define SOR_DP_LINKCTL_ENABLE (1 << 0) 175 176#define SOR_DP_LINKCTL_1 0x4d 177 178#define SOR_LANE_DRIVE_CURRENT_0 0x4e 179#define SOR_LANE_DRIVE_CURRENT_1 0x4f 180#define SOR_LANE4_DRIVE_CURRENT_0 0x50 181#define SOR_LANE4_DRIVE_CURRENT_1 0x51 182#define SOR_LANE_DRIVE_CURRENT_LANE3(x) (((x) & 0xff) << 24) 183#define SOR_LANE_DRIVE_CURRENT_LANE2(x) (((x) & 0xff) << 16) 184#define SOR_LANE_DRIVE_CURRENT_LANE1(x) (((x) & 0xff) << 8) 185#define SOR_LANE_DRIVE_CURRENT_LANE0(x) (((x) & 0xff) << 0) 186 187#define SOR_LANE_PREEMPHASIS_0 0x52 188#define SOR_LANE_PREEMPHASIS_1 0x53 189#define SOR_LANE4_PREEMPHASIS_0 0x54 190#define SOR_LANE4_PREEMPHASIS_1 0x55 191#define SOR_LANE_PREEMPHASIS_LANE3(x) (((x) & 0xff) << 24) 192#define SOR_LANE_PREEMPHASIS_LANE2(x) (((x) & 0xff) << 16) 193#define SOR_LANE_PREEMPHASIS_LANE1(x) (((x) & 0xff) << 8) 194#define SOR_LANE_PREEMPHASIS_LANE0(x) (((x) & 0xff) << 0) 195 196#define SOR_LANE_POST_CURSOR_0 0x56 197#define SOR_LANE_POST_CURSOR_1 0x57 198#define SOR_LANE_POST_CURSOR_LANE3(x) (((x) & 0xff) << 24) 199#define SOR_LANE_POST_CURSOR_LANE2(x) (((x) & 0xff) << 16) 200#define SOR_LANE_POST_CURSOR_LANE1(x) (((x) & 0xff) << 8) 201#define SOR_LANE_POST_CURSOR_LANE0(x) (((x) & 0xff) << 0) 202 203#define SOR_DP_CONFIG_0 0x58 204#define SOR_DP_CONFIG_DISPARITY_NEGATIVE (1 << 31) 205#define SOR_DP_CONFIG_ACTIVE_SYM_ENABLE (1 << 26) 206#define SOR_DP_CONFIG_ACTIVE_SYM_POLARITY (1 << 24) 207#define SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK (0xf << 16) 208#define SOR_DP_CONFIG_ACTIVE_SYM_FRAC(x) (((x) & 0xf) << 16) 209#define SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK (0x7f << 8) 210#define SOR_DP_CONFIG_ACTIVE_SYM_COUNT(x) (((x) & 0x7f) << 8) 211#define SOR_DP_CONFIG_WATERMARK_MASK (0x3f << 0) 212#define SOR_DP_CONFIG_WATERMARK(x) (((x) & 0x3f) << 0) 213 214#define SOR_DP_CONFIG_1 0x59 215#define SOR_DP_MN_0 0x5a 216#define SOR_DP_MN_1 0x5b 217 218#define SOR_DP_PADCTL_0 0x5c 219#define SOR_DP_PADCTL_PAD_CAL_PD (1 << 23) 220#define SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22) 221#define SOR_DP_PADCTL_TX_PU_MASK (0xff << 8) 222#define SOR_DP_PADCTL_TX_PU(x) (((x) & 0xff) << 8) 223#define SOR_DP_PADCTL_CM_TXD_3 (1 << 7) 224#define SOR_DP_PADCTL_CM_TXD_2 (1 << 6) 225#define SOR_DP_PADCTL_CM_TXD_1 (1 << 5) 226#define SOR_DP_PADCTL_CM_TXD_0 (1 << 4) 227#define SOR_DP_PADCTL_PD_TXD_3 (1 << 3) 228#define SOR_DP_PADCTL_PD_TXD_0 (1 << 2) 229#define SOR_DP_PADCTL_PD_TXD_1 (1 << 1) 230#define SOR_DP_PADCTL_PD_TXD_2 (1 << 0) 231 232#define SOR_DP_PADCTL_1 0x5d 233 234#define SOR_DP_DEBUG_0 0x5e 235#define SOR_DP_DEBUG_1 0x5f 236 237#define SOR_DP_SPARE_0 0x60 238#define SOR_DP_SPARE_MACRO_SOR_CLK (1 << 2) 239#define SOR_DP_SPARE_PANEL_INTERNAL (1 << 1) 240#define SOR_DP_SPARE_SEQ_ENABLE (1 << 0) 241 242#define SOR_DP_SPARE_1 0x61 243#define SOR_DP_AUDIO_CTRL 0x62 244 245#define SOR_DP_AUDIO_HBLANK_SYMBOLS 0x63 246#define SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK (0x01ffff << 0) 247 248#define SOR_DP_AUDIO_VBLANK_SYMBOLS 0x64 249#define SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1fffff << 0) 250 251#define SOR_DP_GENERIC_INFOFRAME_HEADER 0x65 252#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_0 0x66 253#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_1 0x67 254#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_2 0x68 255#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_3 0x69 256#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_4 0x6a 257#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_5 0x6b 258#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_6 0x6c 259 260#define SOR_DP_TPG 0x6d 261#define SOR_DP_TPG_CHANNEL_CODING (1 << 6) 262#define SOR_DP_TPG_SCRAMBLER_MASK (3 << 4) 263#define SOR_DP_TPG_SCRAMBLER_FIBONACCI (2 << 4) 264#define SOR_DP_TPG_SCRAMBLER_GALIOS (1 << 4) 265#define SOR_DP_TPG_SCRAMBLER_NONE (0 << 4) 266#define SOR_DP_TPG_PATTERN_MASK (0xf << 0) 267#define SOR_DP_TPG_PATTERN_HBR2 (0x8 << 0) 268#define SOR_DP_TPG_PATTERN_CSTM (0x7 << 0) 269#define SOR_DP_TPG_PATTERN_PRBS7 (0x6 << 0) 270#define SOR_DP_TPG_PATTERN_SBLERRRATE (0x5 << 0) 271#define SOR_DP_TPG_PATTERN_D102 (0x4 << 0) 272#define SOR_DP_TPG_PATTERN_TRAIN3 (0x3 << 0) 273#define SOR_DP_TPG_PATTERN_TRAIN2 (0x2 << 0) 274#define SOR_DP_TPG_PATTERN_TRAIN1 (0x1 << 0) 275#define SOR_DP_TPG_PATTERN_NONE (0x0 << 0) 276 277#define SOR_DP_TPG_CONFIG 0x6e 278#define SOR_DP_LQ_CSTM_0 0x6f 279#define SOR_DP_LQ_CSTM_1 0x70 280#define SOR_DP_LQ_CSTM_2 0x71 281 282#endif 283