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11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/errno.h>
15#include <linux/platform_device.h>
16#include <linux/sched.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/timer.h>
24#include <linux/jiffies.h>
25#include <linux/completion.h>
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/partitions.h>
28#include <linux/mtd/spi-nor.h>
29
30
31#define QUADSPI_MCR 0x00
32#define QUADSPI_MCR_RESERVED_SHIFT 16
33#define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
34#define QUADSPI_MCR_MDIS_SHIFT 14
35#define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
36#define QUADSPI_MCR_CLR_TXF_SHIFT 11
37#define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
38#define QUADSPI_MCR_CLR_RXF_SHIFT 10
39#define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
40#define QUADSPI_MCR_DDR_EN_SHIFT 7
41#define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
42#define QUADSPI_MCR_END_CFG_SHIFT 2
43#define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
44#define QUADSPI_MCR_SWRSTHD_SHIFT 1
45#define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
46#define QUADSPI_MCR_SWRSTSD_SHIFT 0
47#define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
48
49#define QUADSPI_IPCR 0x08
50#define QUADSPI_IPCR_SEQID_SHIFT 24
51#define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
52
53#define QUADSPI_BUF0CR 0x10
54#define QUADSPI_BUF1CR 0x14
55#define QUADSPI_BUF2CR 0x18
56#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
57
58#define QUADSPI_BUF3CR 0x1c
59#define QUADSPI_BUF3CR_ALLMST_SHIFT 31
60#define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
61#define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
62#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
63
64#define QUADSPI_BFGENCR 0x20
65#define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
66#define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
67#define QUADSPI_BFGENCR_SEQID_SHIFT 12
68#define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
69
70#define QUADSPI_BUF0IND 0x30
71#define QUADSPI_BUF1IND 0x34
72#define QUADSPI_BUF2IND 0x38
73#define QUADSPI_SFAR 0x100
74
75#define QUADSPI_SMPR 0x108
76#define QUADSPI_SMPR_DDRSMP_SHIFT 16
77#define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
78#define QUADSPI_SMPR_FSDLY_SHIFT 6
79#define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
80#define QUADSPI_SMPR_FSPHS_SHIFT 5
81#define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
82#define QUADSPI_SMPR_HSENA_SHIFT 0
83#define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
84
85#define QUADSPI_RBSR 0x10c
86#define QUADSPI_RBSR_RDBFL_SHIFT 8
87#define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
88
89#define QUADSPI_RBCT 0x110
90#define QUADSPI_RBCT_WMRK_MASK 0x1F
91#define QUADSPI_RBCT_RXBRD_SHIFT 8
92#define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
93
94#define QUADSPI_TBSR 0x150
95#define QUADSPI_TBDR 0x154
96#define QUADSPI_SR 0x15c
97#define QUADSPI_SR_IP_ACC_SHIFT 1
98#define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
99#define QUADSPI_SR_AHB_ACC_SHIFT 2
100#define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
101
102#define QUADSPI_FR 0x160
103#define QUADSPI_FR_TFF_MASK 0x1
104
105#define QUADSPI_SFA1AD 0x180
106#define QUADSPI_SFA2AD 0x184
107#define QUADSPI_SFB1AD 0x188
108#define QUADSPI_SFB2AD 0x18c
109#define QUADSPI_RBDR 0x200
110
111#define QUADSPI_LUTKEY 0x300
112#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
113
114#define QUADSPI_LCKCR 0x304
115#define QUADSPI_LCKER_LOCK 0x1
116#define QUADSPI_LCKER_UNLOCK 0x2
117
118#define QUADSPI_RSER 0x164
119#define QUADSPI_RSER_TFIE (0x1 << 0)
120
121#define QUADSPI_LUT_BASE 0x310
122
123
124
125
126
127
128
129
130#define OPRND0_SHIFT 0
131#define PAD0_SHIFT 8
132#define INSTR0_SHIFT 10
133#define OPRND1_SHIFT 16
134
135
136#define LUT_STOP 0
137#define LUT_CMD 1
138#define LUT_ADDR 2
139#define LUT_DUMMY 3
140#define LUT_MODE 4
141#define LUT_MODE2 5
142#define LUT_MODE4 6
143#define LUT_READ 7
144#define LUT_WRITE 8
145#define LUT_JMP_ON_CS 9
146#define LUT_ADDR_DDR 10
147#define LUT_MODE_DDR 11
148#define LUT_MODE2_DDR 12
149#define LUT_MODE4_DDR 13
150#define LUT_READ_DDR 14
151#define LUT_WRITE_DDR 15
152#define LUT_DATA_LEARN 16
153
154
155
156
157
158
159
160
161#define LUT_PAD1 0
162#define LUT_PAD2 1
163#define LUT_PAD4 2
164
165
166#define ADDR24BIT 0x18
167#define ADDR32BIT 0x20
168
169
170#define LUT0(ins, pad, opr) \
171 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
172 ((LUT_##ins) << INSTR0_SHIFT))
173
174#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
175
176
177#define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
178#define QUADSPI_LUT_NUM 64
179
180
181#define SEQID_QUAD_READ 0
182#define SEQID_WREN 1
183#define SEQID_WRDI 2
184#define SEQID_RDSR 3
185#define SEQID_SE 4
186#define SEQID_CHIP_ERASE 5
187#define SEQID_PP 6
188#define SEQID_RDID 7
189#define SEQID_WRSR 8
190#define SEQID_RDCR 9
191#define SEQID_EN4B 10
192#define SEQID_BRWR 11
193
194enum fsl_qspi_devtype {
195 FSL_QUADSPI_VYBRID,
196 FSL_QUADSPI_IMX6SX,
197};
198
199struct fsl_qspi_devtype_data {
200 enum fsl_qspi_devtype devtype;
201 int rxfifo;
202 int txfifo;
203 int ahb_buf_size;
204};
205
206static struct fsl_qspi_devtype_data vybrid_data = {
207 .devtype = FSL_QUADSPI_VYBRID,
208 .rxfifo = 128,
209 .txfifo = 64,
210 .ahb_buf_size = 1024
211};
212
213static struct fsl_qspi_devtype_data imx6sx_data = {
214 .devtype = FSL_QUADSPI_IMX6SX,
215 .rxfifo = 128,
216 .txfifo = 512,
217 .ahb_buf_size = 1024
218};
219
220#define FSL_QSPI_MAX_CHIP 4
221struct fsl_qspi {
222 struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
223 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
224 void __iomem *iobase;
225 void __iomem *ahb_base;
226 u32 memmap_phy;
227 struct clk *clk, *clk_en;
228 struct device *dev;
229 struct completion c;
230 struct fsl_qspi_devtype_data *devtype_data;
231 u32 nor_size;
232 u32 nor_num;
233 u32 clk_rate;
234 unsigned int chip_base_addr;
235 bool has_second_chip;
236};
237
238static inline int is_vybrid_qspi(struct fsl_qspi *q)
239{
240 return q->devtype_data->devtype == FSL_QUADSPI_VYBRID;
241}
242
243static inline int is_imx6sx_qspi(struct fsl_qspi *q)
244{
245 return q->devtype_data->devtype == FSL_QUADSPI_IMX6SX;
246}
247
248
249
250
251
252static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
253{
254 return is_vybrid_qspi(q) ? __swab32(a) : a;
255}
256
257static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
258{
259 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
260 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
261}
262
263static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
264{
265 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
266 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
267}
268
269static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
270{
271 struct fsl_qspi *q = dev_id;
272 u32 reg;
273
274
275 reg = readl(q->iobase + QUADSPI_FR);
276 writel(reg, q->iobase + QUADSPI_FR);
277
278 if (reg & QUADSPI_FR_TFF_MASK)
279 complete(&q->c);
280
281 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
282 return IRQ_HANDLED;
283}
284
285static void fsl_qspi_init_lut(struct fsl_qspi *q)
286{
287 void __iomem *base = q->iobase;
288 int rxfifo = q->devtype_data->rxfifo;
289 u32 lut_base;
290 u8 cmd, addrlen, dummy;
291 int i;
292
293 fsl_qspi_unlock_lut(q);
294
295
296 for (i = 0; i < QUADSPI_LUT_NUM; i++)
297 writel(0, base + QUADSPI_LUT_BASE + i * 4);
298
299
300 lut_base = SEQID_QUAD_READ * 4;
301
302 if (q->nor_size <= SZ_16M) {
303 cmd = SPINOR_OP_READ_1_1_4;
304 addrlen = ADDR24BIT;
305 dummy = 8;
306 } else {
307
308 cmd = SPINOR_OP_READ_1_1_4;
309 addrlen = ADDR32BIT;
310 dummy = 8;
311 }
312
313 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
314 base + QUADSPI_LUT(lut_base));
315 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
316 base + QUADSPI_LUT(lut_base + 1));
317
318
319 lut_base = SEQID_WREN * 4;
320 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
321
322
323 lut_base = SEQID_PP * 4;
324
325 if (q->nor_size <= SZ_16M) {
326 cmd = SPINOR_OP_PP;
327 addrlen = ADDR24BIT;
328 } else {
329
330 cmd = SPINOR_OP_PP;
331 addrlen = ADDR32BIT;
332 }
333
334 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
335 base + QUADSPI_LUT(lut_base));
336 writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
337
338
339 lut_base = SEQID_RDSR * 4;
340 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
341 base + QUADSPI_LUT(lut_base));
342
343
344 lut_base = SEQID_SE * 4;
345
346 if (q->nor_size <= SZ_16M) {
347 cmd = SPINOR_OP_SE;
348 addrlen = ADDR24BIT;
349 } else {
350
351 cmd = SPINOR_OP_SE;
352 addrlen = ADDR32BIT;
353 }
354
355 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
356 base + QUADSPI_LUT(lut_base));
357
358
359 lut_base = SEQID_CHIP_ERASE * 4;
360 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
361 base + QUADSPI_LUT(lut_base));
362
363
364 lut_base = SEQID_RDID * 4;
365 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
366 base + QUADSPI_LUT(lut_base));
367
368
369 lut_base = SEQID_WRSR * 4;
370 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
371 base + QUADSPI_LUT(lut_base));
372
373
374 lut_base = SEQID_RDCR * 4;
375 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
376 base + QUADSPI_LUT(lut_base));
377
378
379 lut_base = SEQID_WRDI * 4;
380 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
381
382
383 lut_base = SEQID_EN4B * 4;
384 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
385
386
387 lut_base = SEQID_BRWR * 4;
388 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
389
390 fsl_qspi_lock_lut(q);
391}
392
393
394static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
395{
396 switch (cmd) {
397 case SPINOR_OP_READ_1_1_4:
398 return SEQID_QUAD_READ;
399 case SPINOR_OP_WREN:
400 return SEQID_WREN;
401 case SPINOR_OP_WRDI:
402 return SEQID_WRDI;
403 case SPINOR_OP_RDSR:
404 return SEQID_RDSR;
405 case SPINOR_OP_SE:
406 return SEQID_SE;
407 case SPINOR_OP_CHIP_ERASE:
408 return SEQID_CHIP_ERASE;
409 case SPINOR_OP_PP:
410 return SEQID_PP;
411 case SPINOR_OP_RDID:
412 return SEQID_RDID;
413 case SPINOR_OP_WRSR:
414 return SEQID_WRSR;
415 case SPINOR_OP_RDCR:
416 return SEQID_RDCR;
417 case SPINOR_OP_EN4B:
418 return SEQID_EN4B;
419 case SPINOR_OP_BRWR:
420 return SEQID_BRWR;
421 default:
422 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
423 break;
424 }
425 return -EINVAL;
426}
427
428static int
429fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
430{
431 void __iomem *base = q->iobase;
432 int seqid;
433 u32 reg, reg2;
434 int err;
435
436 init_completion(&q->c);
437 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
438 q->chip_base_addr, addr, len, cmd);
439
440
441 reg = readl(base + QUADSPI_MCR);
442
443 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
444 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
445 base + QUADSPI_RBCT);
446 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
447
448 do {
449 reg2 = readl(base + QUADSPI_SR);
450 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
451 udelay(1);
452 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
453 continue;
454 }
455 break;
456 } while (1);
457
458
459 seqid = fsl_qspi_get_seqid(q, cmd);
460 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
461
462
463 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
464 dev_err(q->dev,
465 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
466 cmd, addr, readl(base + QUADSPI_FR),
467 readl(base + QUADSPI_SR));
468 err = -ETIMEDOUT;
469 } else {
470 err = 0;
471 }
472
473
474 writel(reg, base + QUADSPI_MCR);
475
476 return err;
477}
478
479
480static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
481{
482 u32 tmp;
483 int i = 0;
484
485 while (len > 0) {
486 tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
487 tmp = fsl_qspi_endian_xchg(q, tmp);
488 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
489 q->chip_base_addr, tmp);
490
491 if (len >= 4) {
492 *((u32 *)rxbuf) = tmp;
493 rxbuf += 4;
494 } else {
495 memcpy(rxbuf, &tmp, len);
496 break;
497 }
498
499 len -= 4;
500 i++;
501 }
502}
503
504
505
506
507
508
509
510static inline void fsl_qspi_invalid(struct fsl_qspi *q)
511{
512 u32 reg;
513
514 reg = readl(q->iobase + QUADSPI_MCR);
515 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
516 writel(reg, q->iobase + QUADSPI_MCR);
517
518
519
520
521
522 udelay(1);
523
524 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
525 writel(reg, q->iobase + QUADSPI_MCR);
526}
527
528static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
529 u8 opcode, unsigned int to, u32 *txbuf,
530 unsigned count, size_t *retlen)
531{
532 int ret, i, j;
533 u32 tmp;
534
535 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
536 q->chip_base_addr, to, count);
537
538
539 tmp = readl(q->iobase + QUADSPI_MCR);
540 writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);
541
542
543 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
544 tmp = fsl_qspi_endian_xchg(q, *txbuf);
545 writel(tmp, q->iobase + QUADSPI_TBDR);
546 txbuf++;
547 }
548
549
550 ret = fsl_qspi_runcmd(q, opcode, to, count);
551
552 if (ret == 0 && retlen)
553 *retlen += count;
554
555 return ret;
556}
557
558static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
559{
560 int nor_size = q->nor_size;
561 void __iomem *base = q->iobase;
562
563 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
564 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
565 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
566 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
567}
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
583{
584 void __iomem *base = q->iobase;
585 int seqid;
586
587
588 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
589 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
590 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
591
592
593
594
595 writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
596 << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
597
598
599 writel(0, base + QUADSPI_BUF0IND);
600 writel(0, base + QUADSPI_BUF1IND);
601 writel(0, base + QUADSPI_BUF2IND);
602
603
604 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
605 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
606 q->iobase + QUADSPI_BFGENCR);
607}
608
609
610static int fsl_qspi_nor_setup(struct fsl_qspi *q)
611{
612 void __iomem *base = q->iobase;
613 u32 reg;
614 int ret;
615
616
617 ret = clk_set_rate(q->clk, 66000000);
618 if (ret)
619 return ret;
620
621
622 fsl_qspi_init_lut(q);
623
624
625 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
626 base + QUADSPI_MCR);
627
628 reg = readl(base + QUADSPI_SMPR);
629 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
630 | QUADSPI_SMPR_FSPHS_MASK
631 | QUADSPI_SMPR_HSENA_MASK
632 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
633
634
635 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
636 base + QUADSPI_MCR);
637
638
639 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
640
641 return 0;
642}
643
644static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
645{
646 unsigned long rate = q->clk_rate;
647 int ret;
648
649 if (is_imx6sx_qspi(q))
650 rate *= 4;
651
652 ret = clk_set_rate(q->clk, rate);
653 if (ret)
654 return ret;
655
656
657 fsl_qspi_init_lut(q);
658
659
660 fsl_qspi_init_abh_read(q);
661
662 return 0;
663}
664
665static const struct of_device_id fsl_qspi_dt_ids[] = {
666 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
667 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
668 { }
669};
670MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
671
672static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
673{
674 q->chip_base_addr = q->nor_size * (nor - q->nor);
675}
676
677static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
678{
679 int ret;
680 struct fsl_qspi *q = nor->priv;
681
682 ret = fsl_qspi_runcmd(q, opcode, 0, len);
683 if (ret)
684 return ret;
685
686 fsl_qspi_read_data(q, len, buf);
687 return 0;
688}
689
690static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
691 int write_enable)
692{
693 struct fsl_qspi *q = nor->priv;
694 int ret;
695
696 if (!buf) {
697 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
698 if (ret)
699 return ret;
700
701 if (opcode == SPINOR_OP_CHIP_ERASE)
702 fsl_qspi_invalid(q);
703
704 } else if (len > 0) {
705 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
706 (u32 *)buf, len, NULL);
707 } else {
708 dev_err(q->dev, "invalid cmd %d\n", opcode);
709 ret = -EINVAL;
710 }
711
712 return ret;
713}
714
715static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
716 size_t len, size_t *retlen, const u_char *buf)
717{
718 struct fsl_qspi *q = nor->priv;
719
720 fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
721 (u32 *)buf, len, retlen);
722
723
724 fsl_qspi_invalid(q);
725}
726
727static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
728 size_t len, size_t *retlen, u_char *buf)
729{
730 struct fsl_qspi *q = nor->priv;
731 u8 cmd = nor->read_opcode;
732
733 dev_dbg(q->dev, "cmd [%x],read from (0x%p, 0x%.8x, 0x%.8x),len:%d\n",
734 cmd, q->ahb_base, q->chip_base_addr, (unsigned int)from, len);
735
736
737 memcpy(buf, q->ahb_base + q->chip_base_addr + from, len);
738
739 *retlen += len;
740 return 0;
741}
742
743static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
744{
745 struct fsl_qspi *q = nor->priv;
746 int ret;
747
748 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
749 nor->mtd->erasesize / 1024, q->chip_base_addr, (u32)offs);
750
751 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
752 if (ret)
753 return ret;
754
755 fsl_qspi_invalid(q);
756 return 0;
757}
758
759static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
760{
761 struct fsl_qspi *q = nor->priv;
762 int ret;
763
764 ret = clk_enable(q->clk_en);
765 if (ret)
766 return ret;
767
768 ret = clk_enable(q->clk);
769 if (ret) {
770 clk_disable(q->clk_en);
771 return ret;
772 }
773
774 fsl_qspi_set_base_addr(q, nor);
775 return 0;
776}
777
778static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
779{
780 struct fsl_qspi *q = nor->priv;
781
782 clk_disable(q->clk);
783 clk_disable(q->clk_en);
784}
785
786static int fsl_qspi_probe(struct platform_device *pdev)
787{
788 struct device_node *np = pdev->dev.of_node;
789 struct mtd_part_parser_data ppdata;
790 struct device *dev = &pdev->dev;
791 struct fsl_qspi *q;
792 struct resource *res;
793 struct spi_nor *nor;
794 struct mtd_info *mtd;
795 int ret, i = 0;
796 const struct of_device_id *of_id =
797 of_match_device(fsl_qspi_dt_ids, &pdev->dev);
798
799 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
800 if (!q)
801 return -ENOMEM;
802
803 q->nor_num = of_get_child_count(dev->of_node);
804 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
805 return -ENODEV;
806
807
808 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
809 q->iobase = devm_ioremap_resource(dev, res);
810 if (IS_ERR(q->iobase))
811 return PTR_ERR(q->iobase);
812
813 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
814 "QuadSPI-memory");
815 q->ahb_base = devm_ioremap_resource(dev, res);
816 if (IS_ERR(q->ahb_base))
817 return PTR_ERR(q->ahb_base);
818
819 q->memmap_phy = res->start;
820
821
822 q->clk_en = devm_clk_get(dev, "qspi_en");
823 if (IS_ERR(q->clk_en))
824 return PTR_ERR(q->clk_en);
825
826 q->clk = devm_clk_get(dev, "qspi");
827 if (IS_ERR(q->clk))
828 return PTR_ERR(q->clk);
829
830 ret = clk_prepare_enable(q->clk_en);
831 if (ret) {
832 dev_err(dev, "cannot enable the qspi_en clock: %d\n", ret);
833 return ret;
834 }
835
836 ret = clk_prepare_enable(q->clk);
837 if (ret) {
838 dev_err(dev, "cannot enable the qspi clock: %d\n", ret);
839 goto clk_failed;
840 }
841
842
843 ret = platform_get_irq(pdev, 0);
844 if (ret < 0) {
845 dev_err(dev, "failed to get the irq: %d\n", ret);
846 goto irq_failed;
847 }
848
849 ret = devm_request_irq(dev, ret,
850 fsl_qspi_irq_handler, 0, pdev->name, q);
851 if (ret) {
852 dev_err(dev, "failed to request irq: %d\n", ret);
853 goto irq_failed;
854 }
855
856 q->dev = dev;
857 q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
858 platform_set_drvdata(pdev, q);
859
860 ret = fsl_qspi_nor_setup(q);
861 if (ret)
862 goto irq_failed;
863
864 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
865 q->has_second_chip = true;
866
867
868 for_each_available_child_of_node(dev->of_node, np) {
869 char modalias[40];
870
871
872 if (!q->has_second_chip)
873 i *= 2;
874
875 nor = &q->nor[i];
876 mtd = &q->mtd[i];
877
878 nor->mtd = mtd;
879 nor->dev = dev;
880 nor->priv = q;
881 mtd->priv = nor;
882
883
884 nor->read_reg = fsl_qspi_read_reg;
885 nor->write_reg = fsl_qspi_write_reg;
886 nor->read = fsl_qspi_read;
887 nor->write = fsl_qspi_write;
888 nor->erase = fsl_qspi_erase;
889
890 nor->prepare = fsl_qspi_prep;
891 nor->unprepare = fsl_qspi_unprep;
892
893 ret = of_modalias_node(np, modalias, sizeof(modalias));
894 if (ret < 0)
895 goto irq_failed;
896
897 ret = of_property_read_u32(np, "spi-max-frequency",
898 &q->clk_rate);
899 if (ret < 0)
900 goto irq_failed;
901
902
903 fsl_qspi_set_base_addr(q, nor);
904
905 ret = spi_nor_scan(nor, modalias, SPI_NOR_QUAD);
906 if (ret)
907 goto irq_failed;
908
909 ppdata.of_node = np;
910 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
911 if (ret)
912 goto irq_failed;
913
914
915 if (q->nor_size == 0) {
916 q->nor_size = mtd->size;
917
918
919 fsl_qspi_set_map_addr(q);
920 }
921
922
923
924
925
926
927
928
929
930
931 if (nor->page_size > q->devtype_data->txfifo)
932 nor->page_size = q->devtype_data->txfifo;
933
934 i++;
935 }
936
937
938 ret = fsl_qspi_nor_setup_last(q);
939 if (ret)
940 goto last_init_failed;
941
942 clk_disable(q->clk);
943 clk_disable(q->clk_en);
944 return 0;
945
946last_init_failed:
947 for (i = 0; i < q->nor_num; i++) {
948
949 if (!q->has_second_chip)
950 i *= 2;
951 mtd_device_unregister(&q->mtd[i]);
952 }
953irq_failed:
954 clk_disable_unprepare(q->clk);
955clk_failed:
956 clk_disable_unprepare(q->clk_en);
957 return ret;
958}
959
960static int fsl_qspi_remove(struct platform_device *pdev)
961{
962 struct fsl_qspi *q = platform_get_drvdata(pdev);
963 int i;
964
965 for (i = 0; i < q->nor_num; i++) {
966
967 if (!q->has_second_chip)
968 i *= 2;
969 mtd_device_unregister(&q->mtd[i]);
970 }
971
972
973 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
974 writel(0x0, q->iobase + QUADSPI_RSER);
975
976 clk_unprepare(q->clk);
977 clk_unprepare(q->clk_en);
978 return 0;
979}
980
981static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
982{
983 return 0;
984}
985
986static int fsl_qspi_resume(struct platform_device *pdev)
987{
988 struct fsl_qspi *q = platform_get_drvdata(pdev);
989
990 fsl_qspi_nor_setup(q);
991 fsl_qspi_set_map_addr(q);
992 fsl_qspi_nor_setup_last(q);
993
994 return 0;
995}
996
997static struct platform_driver fsl_qspi_driver = {
998 .driver = {
999 .name = "fsl-quadspi",
1000 .bus = &platform_bus_type,
1001 .of_match_table = fsl_qspi_dt_ids,
1002 },
1003 .probe = fsl_qspi_probe,
1004 .remove = fsl_qspi_remove,
1005 .suspend = fsl_qspi_suspend,
1006 .resume = fsl_qspi_resume,
1007};
1008module_platform_driver(fsl_qspi_driver);
1009
1010MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1011MODULE_AUTHOR("Freescale Semiconductor Inc.");
1012MODULE_LICENSE("GPL v2");
1013