LXR linux/drivers/net/ethernet/intel/ixgb/ixgb

   1/*******************************************************************************
   2
   3  Intel PRO/10GbE Linux driver
   4  Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6  This program is free software; you can redistribute it and/or modify it
   7  under the terms and conditions of the GNU General Public License,
   8  version 2, as published by the Free Software Foundation.
   9
  10  This program is distributed in the hope it will be useful, but WITHOUT
  11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  more details.
  14
  15  You should have received a copy of the GNU General Public License along with
  16  this program; if not, write to the Free Software Foundation, Inc.,
  17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19  The full GNU General Public License is included in this distribution in
  20  the file called "COPYING".
  21
  22  Contact Information:
  23  Linux NICS <linux.nics@intel.com>
  24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27*******************************************************************************/
  28
  29/* glue for the OS independent part of ixgb
  30 * includes register access macros
  31 */
  32
  33#ifndef _IXGB_OSDEP_H_
  34#define _IXGB_OSDEP_H_
  35
  36#include <linux/types.h>
  37#include <linux/delay.h>
  38#include <asm/io.h>
  39#include <linux/interrupt.h>
  40#include <linux/sched.h>
  41#include <linux/if_ether.h>
  42
  43#undef ASSERT
  44#define ASSERT(x)       BUG_ON(!(x))
  45
  46#define ENTER() pr_debug("%s\n", __func__);
  47
  48#define IXGB_WRITE_REG(a, reg, value) ( \
  49        writel((value), ((a)->hw_addr + IXGB_##reg)))
  50
  51#define IXGB_READ_REG(a, reg) ( \
  52        readl((a)->hw_addr + IXGB_##reg))
  53
  54#define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \
  55        writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2))))
  56
  57#define IXGB_READ_REG_ARRAY(a, reg, offset) ( \
  58        readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
  59
  60#define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS)
  61
  62#define IXGB_MEMCPY memcpy
  63
  64#endif /* _IXGB_OSDEP_H_ */
  65