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37
38#ifndef _CASSINI_H
39#define _CASSINI_H
40
41
42
43
44
45
46#define CAS_ID_REV2 0x02
47#define CAS_ID_REVPLUS 0x10
48#define CAS_ID_REVPLUS02u 0x11
49#define CAS_ID_REVSATURNB2 0x30
50
51
52
53
54
55
56
57
58
59#define REG_CAWR 0x0004
60#define CAWR_RX_DMA_WEIGHT_SHIFT 0
61#define CAWR_RX_DMA_WEIGHT_MASK 0x03
62#define CAWR_TX_DMA_WEIGHT_SHIFT 2
63#define CAWR_TX_DMA_WEIGHT_MASK 0x0C
64#define CAWR_RR_DIS 0x10
65
66
67
68
69
70
71#define REG_INF_BURST 0x0008
72#define INF_BURST_EN 0x1
73
74
75
76
77
78
79#define REG_INTR_STATUS 0x000C
80#define INTR_TX_INTME 0x00000001
81
82
83#define INTR_TX_ALL 0x00000002
84
85
86
87
88#define INTR_TX_DONE 0x00000004
89
90#define INTR_TX_TAG_ERROR 0x00000008
91
92#define INTR_RX_DONE 0x00000010
93
94
95
96
97#define INTR_RX_BUF_UNAVAIL 0x00000020
98
99#define INTR_RX_TAG_ERROR 0x00000040
100
101#define INTR_RX_COMP_FULL 0x00000080
102
103
104
105
106#define INTR_RX_BUF_AE 0x00000100
107
108
109
110#define INTR_RX_COMP_AF 0x00000200
111
112
113
114
115#define INTR_RX_LEN_MISMATCH 0x00000400
116
117
118
119
120
121
122#define INTR_SUMMARY 0x00001000
123
124
125
126
127#define INTR_PCS_STATUS 0x00002000
128#define INTR_TX_MAC_STATUS 0x00004000
129
130#define INTR_RX_MAC_STATUS 0x00008000
131
132#define INTR_MAC_CTRL_STATUS 0x00010000
133
134
135#define INTR_MIF_STATUS 0x00020000
136
137#define INTR_PCI_ERROR_STATUS 0x00040000
138
139
140#define INTR_TX_COMP_3_MASK 0xFFF80000
141
142#define INTR_TX_COMP_3_SHIFT 19
143#define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
144 INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
145 INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
146 INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
147 INTR_MAC_CTRL_STATUS)
148
149
150
151
152
153#define REG_INTR_MASK 0x0010
154
155
156
157
158
159#define REG_ALIAS_CLEAR 0x0014
160
161
162
163
164
165#define REG_INTR_STATUS_ALIAS 0x001C
166
167
168
169#define REG_PCI_ERR_STATUS 0x1000
170#define PCI_ERR_BADACK 0x01
171
172
173#define PCI_ERR_DTRTO 0x02
174
175#define PCI_ERR_OTHER 0x04
176#define PCI_ERR_BIM_DMA_WRITE 0x08
177
178#define PCI_ERR_BIM_DMA_READ 0x10
179
180#define PCI_ERR_BIM_DMA_TIMEOUT 0x20
181
182
183
184
185
186
187#define REG_PCI_ERR_STATUS_MASK 0x1004
188
189
190
191
192#define REG_BIM_CFG 0x1008
193#define BIM_CFG_RESERVED0 0x001
194#define BIM_CFG_RESERVED1 0x002
195#define BIM_CFG_64BIT_DISABLE 0x004
196#define BIM_CFG_66MHZ 0x008
197#define BIM_CFG_32BIT 0x010
198#define BIM_CFG_DPAR_INTR_ENABLE 0x020
199#define BIM_CFG_RMA_INTR_ENABLE 0x040
200#define BIM_CFG_RTA_INTR_ENABLE 0x080
201#define BIM_CFG_RESERVED2 0x100
202#define BIM_CFG_BIM_DISABLE 0x200
203
204#define BIM_CFG_BIM_STATUS 0x400
205
206#define BIM_CFG_PERROR_BLOCK 0x800
207
208
209
210#define REG_BIM_DIAG 0x100C
211#define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00
212
213#define BIM_DIAG_BRST_SM_MASK 0x7F
214
215
216
217
218
219#define REG_SW_RESET 0x1010
220#define SW_RESET_TX 0x00000001
221
222#define SW_RESET_RX 0x00000002
223
224#define SW_RESET_RSTOUT 0x00000004
225
226
227
228
229
230#define SW_RESET_BLOCK_PCS_SLINK 0x00000008
231
232
233
234#define SW_RESET_BREQ_SM_MASK 0x00007F00
235#define SW_RESET_PCIARB_SM_MASK 0x00070000
236
237
238
239
240
241
242
243
244#define SW_RESET_RDPCI_SM_MASK 0x00300000
245
246
247
248#define SW_RESET_RDARB_SM_MASK 0x00C00000
249
250
251
252
253#define SW_RESET_WRPCI_SM_MASK 0x06000000
254
255
256
257#define SW_RESET_WRARB_SM_MASK 0x38000000
258
259
260
261
262
263
264
265
266
267
268
269#define REG_MINUS_BIM_DATAPATH_TEST 0x1018
270
271
272
273
274
275
276
277#define REG_BIM_LOCAL_DEV_EN 0x1020
278
279#define BIM_LOCAL_DEV_PAD 0x01
280
281
282
283
284#define BIM_LOCAL_DEV_PROM 0x02
285#define BIM_LOCAL_DEV_EXT 0x04
286
287#define BIM_LOCAL_DEV_SOFT_0 0x08
288#define BIM_LOCAL_DEV_SOFT_1 0x10
289#define BIM_LOCAL_DEV_HW_RESET 0x20
290
291
292
293
294
295
296#define REG_BIM_BUFFER_ADDR 0x1024
297
298#define BIM_BUFFER_ADDR_MASK 0x3F
299#define BIM_BUFFER_WR_SELECT 0x40
300
301
302#define REG_BIM_BUFFER_DATA_LOW 0x1028
303#define REG_BIM_BUFFER_DATA_HI 0x102C
304
305
306
307
308#define REG_BIM_RAM_BIST 0x102C
309
310#define BIM_RAM_BIST_RD_START 0x01
311#define BIM_RAM_BIST_WR_START 0x02
312
313
314#define BIM_RAM_BIST_RD_PASS 0x04
315
316#define BIM_RAM_BIST_WR_PASS 0x08
317
318
319#define BIM_RAM_BIST_RD_LOW_PASS 0x10
320#define BIM_RAM_BIST_RD_HI_PASS 0x20
321#define BIM_RAM_BIST_WR_LOW_PASS 0x40
322
323
324#define BIM_RAM_BIST_WR_HI_PASS 0x80
325
326
327
328
329
330
331#define REG_BIM_DIAG_MUX 0x1030
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353#define REG_PLUS_PROBE_MUX_SELECT 0x1034
354#define PROBE_MUX_EN 0x80000000
355
356
357#define PROBE_MUX_SUB_MUX_MASK 0x0000FF00
358
359
360
361
362#define PROBE_MUX_SEL_HI_MASK 0x000000F0
363
364
365#define PROBE_MUX_SEL_LOW_MASK 0x0000000F
366
367
368
369
370
371#define REG_PLUS_INTR_MASK_1 0x1038
372
373#define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
374
375
376
377
378
379#define INTR_RX_DONE_ALT 0x01
380#define INTR_RX_COMP_FULL_ALT 0x02
381#define INTR_RX_COMP_AF_ALT 0x04
382#define INTR_RX_BUF_UNAVAIL_1 0x08
383#define INTR_RX_BUF_AE_1 0x10
384#define INTRN_MASK_RX_EN 0x80
385#define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
386 INTR_RX_COMP_FULL_ALT | \
387 INTR_RX_COMP_AF_ALT | \
388 INTR_RX_BUF_UNAVAIL_1 | \
389 INTR_RX_BUF_AE_1)
390#define REG_PLUS_INTR_STATUS_1 0x103C
391
392#define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
393#define INTR_STATUS_ALT_INTX_EN 0x80
394
395
396#define REG_PLUS_ALIAS_CLEAR_1 0x1040
397
398#define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
399
400#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044
401
402#define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
403
404#define REG_SATURN_PCFG 0x106c
405
406
407#define SATURN_PCFG_TLA 0x00000001
408#define SATURN_PCFG_FLA 0x00000002
409#define SATURN_PCFG_CLA 0x00000004
410#define SATURN_PCFG_LLA 0x00000008
411#define SATURN_PCFG_RLA 0x00000010
412#define SATURN_PCFG_PDS 0x00000020
413
414#define SATURN_PCFG_MTP 0x00000080
415#define SATURN_PCFG_GMO 0x00000100
416
417
418#define SATURN_PCFG_FSI 0x00000200
419
420
421
422#define SATURN_PCFG_LAD 0x00000800
423
424
425
426
427
428
429
430#define MAX_TX_RINGS_SHIFT 2
431#define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
432#define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
433
434
435
436
437
438#define REG_TX_CFG 0x2004
439#define TX_CFG_DMA_EN 0x00000001
440
441
442#define TX_CFG_FIFO_PIO_SEL 0x00000002
443
444
445
446
447#define TX_CFG_DESC_RING0_MASK 0x0000003C
448
449#define TX_CFG_DESC_RING0_SHIFT 2
450#define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
451#define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
452#define TX_CFG_PACED_MODE 0x00100000
453
454
455
456#define TX_CFG_DMA_RDPIPE_DIS 0x01000000
457#define TX_CFG_COMPWB_Q1 0x02000000
458
459
460#define TX_CFG_COMPWB_Q2 0x04000000
461
462
463#define TX_CFG_COMPWB_Q3 0x08000000
464
465
466#define TX_CFG_COMPWB_Q4 0x10000000
467
468
469#define TX_CFG_INTR_COMPWB_DIS 0x20000000
470
471#define TX_CFG_CTX_SEL_MASK 0xC0000000
472
473
474
475
476
477
478
479
480
481
482
483
484#define TX_CFG_CTX_SEL_SHIFT 30
485
486
487
488
489#define REG_TX_FIFO_WRITE_PTR 0x2014
490#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018
491
492
493#define REG_TX_FIFO_READ_PTR 0x201C
494#define REG_TX_FIFO_SHADOW_READ_PTR 0x2020
495
496
497
498#define REG_TX_FIFO_PKT_CNT 0x2024
499
500
501#define REG_TX_SM_1 0x2028
502#define TX_SM_1_CHAIN_MASK 0x000003FF
503#define TX_SM_1_CSUM_MASK 0x00000C00
504#define TX_SM_1_FIFO_LOAD_MASK 0x0003F000
505
506#define TX_SM_1_FIFO_UNLOAD_MASK 0x003C0000
507#define TX_SM_1_CACHE_MASK 0x03C00000
508
509#define TX_SM_1_CBQ_ARB_MASK 0xF8000000
510
511#define REG_TX_SM_2 0x202C
512#define TX_SM_2_COMP_WB_MASK 0x07
513#define TX_SM_2_SUB_LOAD_MASK 0x38
514#define TX_SM_2_KICK_MASK 0xC0
515
516
517
518
519#define REG_TX_DATA_PTR_LOW 0x2030
520#define REG_TX_DATA_PTR_HI 0x2034
521
522
523
524
525
526
527
528#define REG_TX_KICK0 0x2038
529#define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
530#define REG_TX_COMP0 0x2048
531#define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549#define TX_COMPWB_SIZE 8
550#define REG_TX_COMPWB_DB_LOW 0x2058
551
552#define REG_TX_COMPWB_DB_HI 0x205C
553
554#define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
555#define TX_COMPWB_MSB_SHIFT 0
556#define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
557#define TX_COMPWB_LSB_SHIFT 8
558#define TX_COMPWB_NEXT(x) ((x) >> 16)
559
560
561
562#define REG_TX_DB0_LOW 0x2060
563#define REG_TX_DB0_HI 0x2064
564#define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
565#define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
566
567
568
569
570
571
572
573
574
575
576#define REG_TX_MAXBURST_0 0x2080
577#define REG_TX_MAXBURST_1 0x2084
578#define REG_TX_MAXBURST_2 0x2088
579#define REG_TX_MAXBURST_3 0x208C
580
581
582
583
584
585
586
587
588#define REG_TX_FIFO_ADDR 0x2104
589#define REG_TX_FIFO_TAG 0x2108
590#define REG_TX_FIFO_DATA_LOW 0x210C
591#define REG_TX_FIFO_DATA_HI_T1 0x2110
592#define REG_TX_FIFO_DATA_HI_T0 0x2114
593#define REG_TX_FIFO_SIZE 0x2118
594
595
596
597
598#define REG_TX_RAMBIST 0x211C
599#define TX_RAMBIST_STATE 0x01C0
600
601#define TX_RAMBIST_RAM33A_PASS 0x0020
602#define TX_RAMBIST_RAM32A_PASS 0x0010
603#define TX_RAMBIST_RAM33B_PASS 0x0008
604#define TX_RAMBIST_RAM32B_PASS 0x0004
605#define TX_RAMBIST_SUMMARY 0x0002
606#define TX_RAMBIST_START 0x0001
607
608
609
610#define MAX_RX_DESC_RINGS 2
611#define MAX_RX_COMP_RINGS 4
612
613
614
615
616
617
618#define REG_RX_CFG 0x4000
619#define RX_CFG_DMA_EN 0x00000001
620
621
622
623
624
625#define RX_CFG_DESC_RING_MASK 0x0000001E
626
627
628#define RX_CFG_DESC_RING_SHIFT 1
629#define RX_CFG_COMP_RING_MASK 0x000001E0
630
631#define RX_CFG_COMP_RING_SHIFT 5
632#define RX_CFG_BATCH_DIS 0x00000200
633
634
635#define RX_CFG_SWIVEL_MASK 0x00001C00
636
637
638
639
640
641
642
643
644#define RX_CFG_SWIVEL_SHIFT 10
645
646
647#define RX_CFG_DESC_RING1_MASK 0x000F0000
648
649
650#define RX_CFG_DESC_RING1_SHIFT 16
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665#define REG_RX_PAGE_SIZE 0x4004
666#define RX_PAGE_SIZE_MASK 0x00000003
667
668
669
670
671
672
673
674#define RX_PAGE_SIZE_SHIFT 0
675#define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800
676
677
678#define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
679#define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000
680
681
682
683
684
685
686#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
687#define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000
688
689
690
691
692
693
694#define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
695
696
697
698
699
700#define REG_RX_FIFO_WRITE_PTR 0x4008
701#define REG_RX_FIFO_READ_PTR 0x400C
702#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010
703
704#define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014
705
706#define REG_RX_IPP_FIFO_READ_PTR 0x400C
707
708
709
710
711
712#define REG_RX_DEBUG 0x401C
713#define RX_DEBUG_LOAD_STATE_MASK 0x0000000F
714
715
716
717
718
719
720
721
722
723#define RX_DEBUG_LM_STATE_MASK 0x00000070
724
725
726
727
728
729
730
731
732#define RX_DEBUG_FC_STATE_MASK 0x000000180
733
734
735
736
737
738#define RX_DEBUG_DATA_STATE_MASK 0x000001E00
739
740
741
742
743
744
745
746
747
748
749
750
751
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753
754
755
756#define RX_DEBUG_DESC_STATE_MASK 0x0001E000
757
758
759
760
761
762
763
764
765
766
767
768#define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000
769
770#define RX_DEBUG_INTR_WRITE_PTR_MASK 0xC0000000
771
772
773
774
775
776
777
778
779
780
781
782#define REG_RX_PAUSE_THRESH 0x4020
783#define RX_PAUSE_THRESH_QUANTUM 64
784#define RX_PAUSE_THRESH_OFF_MASK 0x000001FF
785
786
787#define RX_PAUSE_THRESH_OFF_SHIFT 0
788#define RX_PAUSE_THRESH_ON_MASK 0x001FF000
789
790
791
792
793
794
795#define RX_PAUSE_THRESH_ON_SHIFT 12
796
797
798
799
800
801
802
803#define REG_RX_KICK 0x4024
804
805
806
807
808#define REG_RX_DB_LOW 0x4028
809
810#define REG_RX_DB_HI 0x402C
811
812#define REG_RX_CB_LOW 0x4030
813
814#define REG_RX_CB_HI 0x4034
815
816
817
818
819
820#define REG_RX_COMP 0x4038
821
822
823
824
825
826
827
828
829
830
831
832#define REG_RX_COMP_HEAD 0x403C
833#define REG_RX_COMP_TAIL 0x4040
834
835
836
837
838#define REG_RX_BLANK 0x4044
839
840#define RX_BLANK_INTR_PKT_MASK 0x000001FF
841
842
843
844
845
846#define RX_BLANK_INTR_PKT_SHIFT 0
847#define RX_BLANK_INTR_TIME_MASK 0x3FFFF000
848
849
850
851
852
853
854#define RX_BLANK_INTR_TIME_SHIFT 12
855
856
857
858
859
860#define REG_RX_AE_THRESH 0x4048
861
862#define RX_AE_THRESH_FREE_MASK 0x00001FFF
863
864
865
866#define RX_AE_THRESH_FREE_SHIFT 0
867#define RX_AE_THRESH_COMP_MASK 0x0FFFE000
868
869
870
871
872#define RX_AE_THRESH_COMP_SHIFT 13
873
874
875
876
877
878
879
880#define REG_RX_RED 0x404C
881#define RX_RED_4K_6K_FIFO_MASK 0x000000FF
882#define RX_RED_6K_8K_FIFO_MASK 0x0000FF00
883#define RX_RED_8K_10K_FIFO_MASK 0x00FF0000
884#define RX_RED_10K_12K_FIFO_MASK 0xFF000000
885
886
887
888
889
890#define REG_RX_FIFO_FULLNESS 0x4050
891#define RX_FIFO_FULLNESS_RX_FIFO_MASK 0x3FF80000
892#define RX_FIFO_FULLNESS_IPP_FIFO_MASK 0x0007FF00
893#define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF
894#define REG_RX_IPP_PACKET_COUNT 0x4054
895#define REG_RX_WORK_DMA_PTR_LOW 0x4058
896#define REG_RX_WORK_DMA_PTR_HI 0x405C
897
898
899
900
901
902
903
904#define REG_RX_BIST 0x4060
905#define RX_BIST_32A_PASS 0x80000000
906#define RX_BIST_33A_PASS 0x40000000
907#define RX_BIST_32B_PASS 0x20000000
908#define RX_BIST_33B_PASS 0x10000000
909#define RX_BIST_32C_PASS 0x08000000
910#define RX_BIST_33C_PASS 0x04000000
911#define RX_BIST_IPP_32A_PASS 0x02000000
912#define RX_BIST_IPP_33A_PASS 0x01000000
913#define RX_BIST_IPP_32B_PASS 0x00800000
914#define RX_BIST_IPP_33B_PASS 0x00400000
915#define RX_BIST_IPP_32C_PASS 0x00200000
916#define RX_BIST_IPP_33C_PASS 0x00100000
917#define RX_BIST_CTRL_32_PASS 0x00800000
918#define RX_BIST_CTRL_33_PASS 0x00400000
919#define RX_BIST_REAS_26A_PASS 0x00200000
920#define RX_BIST_REAS_26B_PASS 0x00100000
921#define RX_BIST_REAS_27_PASS 0x00080000
922#define RX_BIST_STATE_MASK 0x00078000
923#define RX_BIST_SUMMARY 0x00000002
924
925
926
927
928#define RX_BIST_START 0x00000001
929
930
931
932
933
934
935
936#define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064
937
938#define REG_RX_CTRL_FIFO_READ_PTR 0x4068
939
940
941
942
943
944
945#define REG_RX_BLANK_ALIAS_READ 0x406C
946
947#define RX_BAR_INTR_PACKET_MASK 0x000001FF
948
949
950
951
952
953
954#define RX_BAR_INTR_TIME_MASK 0x3FFFF000
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969#define REG_RX_FIFO_ADDR 0x4080
970#define REG_RX_FIFO_TAG 0x4084
971#define REG_RX_FIFO_DATA_LOW 0x4088
972#define REG_RX_FIFO_DATA_HI_T0 0x408C
973#define REG_RX_FIFO_DATA_HI_T1 0x4090
974
975
976
977
978
979
980
981
982#define REG_RX_CTRL_FIFO_ADDR 0x4094
983
984#define REG_RX_CTRL_FIFO_DATA_LOW 0x4098
985
986#define REG_RX_CTRL_FIFO_DATA_MID 0x409C
987
988#define REG_RX_CTRL_FIFO_DATA_HI 0x4100
989
990#define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001
991#define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E
992
993
994
995
996#define REG_RX_IPP_FIFO_ADDR 0x4104
997#define REG_RX_IPP_FIFO_TAG 0x4108
998#define REG_RX_IPP_FIFO_DATA_LOW 0x410C
999#define REG_RX_IPP_FIFO_DATA_HI_T0 0x4110
1000
1001#define REG_RX_IPP_FIFO_DATA_HI_T1 0x4114
1002
1003
1004
1005
1006
1007
1008
1009
1010#define REG_RX_HEADER_PAGE_PTR_LOW 0x4118
1011
1012#define REG_RX_HEADER_PAGE_PTR_HI 0x411C
1013
1014#define REG_RX_MTU_PAGE_PTR_LOW 0x4120
1015
1016#define REG_RX_MTU_PAGE_PTR_HI 0x4124
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028#define REG_RX_TABLE_ADDR 0x4128
1029
1030#define RX_TABLE_ADDR_MASK 0x0000003F
1031
1032#define REG_RX_TABLE_DATA_LOW 0x412C
1033
1034#define REG_RX_TABLE_DATA_MID 0x4130
1035
1036#define REG_RX_TABLE_DATA_HI 0x4134
1037
1038
1039
1040
1041
1042
1043#define REG_PLUS_RX_DB1_LOW 0x4200
1044
1045#define REG_PLUS_RX_DB1_HI 0x4204
1046
1047#define REG_PLUS_RX_CB1_LOW 0x4208
1048
1049#define REG_PLUS_RX_CB1_HI 0x420C
1050
1051#define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1052#define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1053#define REG_PLUS_RX_KICK1 0x4220
1054#define REG_PLUS_RX_COMP1 0x4224
1055
1056#define REG_PLUS_RX_COMP1_HEAD 0x4228
1057
1058#define REG_PLUS_RX_COMP1_TAIL 0x422C
1059
1060#define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1061#define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1062#define REG_PLUS_RX_AE1_THRESH 0x4240
1063
1064#define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK
1065#define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT
1066
1067
1068
1069
1070
1071
1072#define REG_HP_CFG 0x4140
1073
1074#define HP_CFG_PARSE_EN 0x00000001
1075#define HP_CFG_NUM_CPU_MASK 0x000000FC
1076
1077#define HP_CFG_NUM_CPU_SHIFT 2
1078#define HP_CFG_SYN_INC_MASK 0x00000100
1079
1080
1081#define HP_CFG_TCP_THRESH_MASK 0x000FFE00
1082
1083
1084#define HP_CFG_TCP_THRESH_SHIFT 9
1085
1086
1087
1088
1089
1090
1091
1092#define REG_HP_INSTR_RAM_ADDR 0x4144
1093
1094#define HP_INSTR_RAM_ADDR_MASK 0x01F
1095#define REG_HP_INSTR_RAM_DATA_LOW 0x4148
1096
1097#define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
1098#define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
1099#define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
1100#define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
1101#define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
1102#define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
1103#define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1104#define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
1105#define REG_HP_INSTR_RAM_DATA_MID 0x414C
1106
1107#define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1108#define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
1109#define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
1110#define HP_INSTR_RAM_MID_OUTOP_SHIFT 2
1111#define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
1112#define HP_INSTR_RAM_MID_FNEXT_SHIFT 6
1113#define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
1114#define HP_INSTR_RAM_MID_FOFF_SHIFT 11
1115#define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
1116#define HP_INSTR_RAM_MID_SNEXT_SHIFT 18
1117#define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
1118#define HP_INSTR_RAM_MID_SOFF_SHIFT 23
1119#define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
1120#define HP_INSTR_RAM_MID_OP_SHIFT 30
1121#define REG_HP_INSTR_RAM_DATA_HI 0x4150
1122
1123#define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
1124#define HP_INSTR_RAM_HI_VAL_SHIFT 0
1125#define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
1126#define HP_INSTR_RAM_HI_MASK_SHIFT 16
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138#define REG_HP_DATA_RAM_FDB_ADDR 0x4154
1139
1140#define HP_DATA_RAM_FDB_DATA_MASK 0x001F
1141
1142
1143
1144#define HP_DATA_RAM_FDB_FDB_MASK 0x3F00
1145
1146#define REG_HP_DATA_RAM_DATA 0x4158
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157#define REG_HP_FLOW_DB0 0x415C
1158#define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
1159
1160
1161
1162
1163
1164#define REG_HP_STATE_MACHINE 0x418C
1165#define REG_HP_STATUS0 0x4190
1166#define HP_STATUS0_SAP_MASK 0xFFFF0000
1167#define HP_STATUS0_L3_OFF_MASK 0x0000FE00
1168#define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8
1169
1170#define HP_STATUS0_HRP_OPCODE_MASK 0x00000007
1171
1172#define REG_HP_STATUS1 0x4194
1173#define HP_STATUS1_ACCUR2_MASK 0xE0000000
1174#define HP_STATUS1_FLOWID_MASK 0x1F800000
1175#define HP_STATUS1_TCP_OFF_MASK 0x007F0000
1176#define HP_STATUS1_TCP_SIZE_MASK 0x0000FFFF
1177
1178#define REG_HP_STATUS2 0x4198
1179#define HP_STATUS2_ACCUR2_MASK 0xF0000000
1180#define HP_STATUS2_CSUM_OFF_MASK 0x07F00000
1181
1182#define HP_STATUS2_ACCUR1_MASK 0x000FE000
1183#define HP_STATUS2_FORCE_DROP 0x00001000
1184#define HP_STATUS2_BWO_REASSM 0x00000800
1185
1186#define HP_STATUS2_JH_SPLIT_EN 0x00000400
1187
1188#define HP_STATUS2_FORCE_TCP_NOCHECK 0x00000200
1189
1190#define HP_STATUS2_DATA_MASK_ZERO 0x00000100
1191
1192#define HP_STATUS2_FORCE_TCP_CHECK 0x00000080
1193
1194#define HP_STATUS2_MASK_TCP_THRESH 0x00000040
1195
1196#define HP_STATUS2_NO_ASSIST 0x00000020
1197#define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010
1198#define HP_STATUS2_TCP_FLAG_CHECK 0x00000008
1199#define HP_STATUS2_SYN_FLAG 0x00000004
1200#define HP_STATUS2_TCP_CHECK 0x00000002
1201#define HP_STATUS2_TCP_NOCHECK 0x00000001
1202
1203
1204
1205
1206
1207
1208#define REG_HP_RAM_BIST 0x419C
1209#define HP_RAM_BIST_HP_DATA_PASS 0x80000000
1210#define HP_RAM_BIST_HP_INSTR0_PASS 0x40000000
1211#define HP_RAM_BIST_HP_INSTR1_PASS 0x20000000
1212#define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000
1213#define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000
1214#define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000
1215#define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000
1216
1217#define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000
1218
1219#define HP_RAM_BIST_FDBM_FLOWID20_PASS 0x00800000
1220
1221#define HP_RAM_BIST_FDBM_FLOWID30_PASS 0x00400000
1222
1223#define HP_RAM_BIST_FDBM_FLOWID01_PASS 0x00200000
1224
1225#define HP_RAM_BIST_FDBM_FLOWID11_PASS 0x00100000
1226
1227#define HP_RAM_BIST_FDBM_FLOWID21_PASS 0x00080000
1228
1229#define HP_RAM_BIST_FDBM_FLOWID31_PASS 0x00040000
1230
1231#define HP_RAM_BIST_FDBM_TCPSEQ_PASS 0x00020000
1232
1233#define HP_RAM_BIST_SUMMARY 0x00000002
1234#define HP_RAM_BIST_START 0x00000001
1235
1236
1237
1238
1239
1240
1241#define REG_MAC_TX_RESET 0x6000
1242
1243#define REG_MAC_RX_RESET 0x6004
1244
1245
1246
1247#define REG_MAC_SEND_PAUSE 0x6008
1248#define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF
1249
1250
1251
1252#define MAC_SEND_PAUSE_SEND 0x00010000
1253
1254
1255
1256
1257
1258
1259
1260
1261#define REG_MAC_TX_STATUS 0x6010
1262#define MAC_TX_FRAME_XMIT 0x0001
1263
1264#define MAC_TX_UNDERRUN 0x0002
1265
1266
1267
1268#define MAC_TX_MAX_PACKET_ERR 0x0004
1269
1270
1271#define MAC_TX_COLL_NORMAL 0x0008
1272
1273#define MAC_TX_COLL_EXCESS 0x0010
1274
1275#define MAC_TX_COLL_LATE 0x0020
1276
1277#define MAC_TX_COLL_FIRST 0x0040
1278
1279#define MAC_TX_DEFER_TIMER 0x0080
1280
1281#define MAC_TX_PEAK_ATTEMPTS 0x0100
1282
1283
1284#define REG_MAC_RX_STATUS 0x6014
1285#define MAC_RX_FRAME_RECV 0x0001
1286
1287#define MAC_RX_OVERFLOW 0x0002
1288
1289#define MAC_RX_FRAME_COUNT 0x0004
1290
1291#define MAC_RX_ALIGN_ERR 0x0008
1292
1293#define MAC_RX_CRC_ERR 0x0010
1294
1295#define MAC_RX_LEN_ERR 0x0020
1296
1297#define MAC_RX_VIOL_ERR 0x0040
1298
1299
1300
1301#define REG_MAC_CTRL_STATUS 0x6018
1302#define MAC_CTRL_PAUSE_RECEIVED 0x00000001
1303
1304
1305
1306#define MAC_CTRL_PAUSE_STATE 0x00000002
1307
1308
1309
1310#define MAC_CTRL_NOPAUSE_STATE 0x00000004
1311
1312
1313
1314#define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000
1315
1316
1317
1318
1319
1320
1321#define REG_MAC_TX_MASK 0x6020
1322
1323#define REG_MAC_RX_MASK 0x6024
1324
1325#define REG_MAC_CTRL_MASK 0x6028
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337#define REG_MAC_TX_CFG 0x6030
1338#define MAC_TX_CFG_EN 0x0001
1339
1340
1341
1342
1343
1344
1345#define MAC_TX_CFG_IGNORE_CARRIER 0x0002
1346
1347
1348
1349#define MAC_TX_CFG_IGNORE_COLL 0x0004
1350
1351
1352
1353#define MAC_TX_CFG_IPG_EN 0x0008
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369#define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381#define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020
1382
1383
1384
1385
1386
1387
1388
1389#define MAC_TX_CFG_NO_BACKOFF 0x0040
1390
1391
1392
1393
1394
1395#define MAC_TX_CFG_SLOW_DOWN 0x0080
1396
1397
1398
1399
1400
1401
1402
1403
1404#define MAC_TX_CFG_NO_FCS 0x0100
1405
1406
1407
1408
1409
1410
1411#define MAC_TX_CFG_CARRIER_EXTEND 0x0200
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432#define REG_MAC_RX_CFG 0x6034
1433#define MAC_RX_CFG_EN 0x0001
1434#define MAC_RX_CFG_STRIP_PAD 0x0002
1435
1436#define MAC_RX_CFG_STRIP_FCS 0x0004
1437
1438
1439#define MAC_RX_CFG_PROMISC_EN 0x0008
1440#define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010
1441
1442
1443#define MAC_RX_CFG_HASH_FILTER_EN 0x0020
1444
1445#define MAC_RX_CFG_ADDR_FILTER_EN 0x0040
1446
1447
1448
1449
1450#define MAC_RX_CFG_DISABLE_DISCARD 0x0080
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460#define MAC_RX_CFG_CARRIER_EXTEND 0x0100
1461
1462
1463
1464
1465
1466
1467
1468#define REG_MAC_CTRL_CFG 0x6038
1469#define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001
1470
1471
1472#define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002
1473
1474#define MAC_CTRL_CFG_PASS_CTRL 0x0004
1475
1476
1477
1478
1479
1480
1481
1482
1483#define REG_MAC_XIF_CFG 0x603C
1484#define MAC_XIF_TX_MII_OUTPUT_EN 0x0001
1485
1486#define MAC_XIF_MII_INT_LOOPBACK 0x0002
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496#define MAC_XIF_DISABLE_ECHO 0x0004
1497
1498
1499
1500
1501
1502
1503
1504
1505#define MAC_XIF_GMII_MODE 0x0008
1506
1507#define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010
1508
1509
1510
1511#define MAC_XIF_LINK_LED 0x0020
1512#define MAC_XIF_FDPLX_LED 0x0040
1513
1514#define REG_MAC_IPG0 0x6040
1515
1516#define REG_MAC_IPG1 0x6044
1517
1518#define REG_MAC_IPG2 0x6048
1519
1520#define REG_MAC_SLOT_TIME 0x604C
1521
1522#define REG_MAC_FRAMESIZE_MIN 0x6050
1523
1524
1525
1526
1527
1528#define REG_MAC_FRAMESIZE_MAX 0x6054
1529#define MAC_FRAMESIZE_MAX_BURST_MASK 0x3FFF0000
1530#define MAC_FRAMESIZE_MAX_BURST_SHIFT 16
1531#define MAC_FRAMESIZE_MAX_FRAME_MASK 0x00007FFF
1532#define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
1533#define REG_MAC_PA_SIZE 0x6058
1534
1535
1536
1537
1538
1539
1540#define REG_MAC_JAM_SIZE 0x605C
1541
1542
1543
1544#define REG_MAC_ATTEMPT_LIMIT 0x6060
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556#define REG_MAC_CTRL_TYPE 0x6064
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583#define REG_MAC_ADDR0 0x6080
1584#define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
1585#define REG_MAC_ADDR_FILTER0 0x614C
1586
1587#define REG_MAC_ADDR_FILTER1 0x6150
1588
1589#define REG_MAC_ADDR_FILTER2 0x6154
1590
1591#define REG_MAC_ADDR_FILTER2_1_MASK 0x6158
1592
1593
1594
1595#define REG_MAC_ADDR_FILTER0_MASK 0x615C
1596
1597
1598
1599
1600
1601
1602
1603#define REG_MAC_HASH_TABLE0 0x6160
1604#define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
1605
1606
1607
1608
1609
1610#define REG_MAC_COLL_NORMAL 0x61A0
1611
1612#define REG_MAC_COLL_FIRST 0x61A4
1613
1614
1615#define REG_MAC_COLL_EXCESS 0x61A8
1616
1617#define REG_MAC_COLL_LATE 0x61AC
1618#define REG_MAC_TIMER_DEFER 0x61B0
1619
1620
1621#define REG_MAC_ATTEMPTS_PEAK 0x61B4
1622#define REG_MAC_RECV_FRAME 0x61B8
1623#define REG_MAC_LEN_ERR 0x61BC
1624#define REG_MAC_ALIGN_ERR 0x61C0
1625#define REG_MAC_FCS_ERR 0x61C4
1626#define REG_MAC_RX_CODE_ERR 0x61C8
1627
1628
1629
1630#define REG_MAC_RANDOM_SEED 0x61CC
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649#define REG_MAC_STATE_MACHINE 0x61D0
1650#define MAC_SM_RLM_MASK 0x07800000
1651#define MAC_SM_RLM_SHIFT 23
1652#define MAC_SM_RX_FC_MASK 0x00700000
1653#define MAC_SM_RX_FC_SHIFT 20
1654#define MAC_SM_TLM_MASK 0x000F0000
1655#define MAC_SM_TLM_SHIFT 16
1656#define MAC_SM_ENCAP_SM_MASK 0x0000F000
1657#define MAC_SM_ENCAP_SM_SHIFT 12
1658#define MAC_SM_TX_REQ_MASK 0x00000C00
1659#define MAC_SM_TX_REQ_SHIFT 10
1660#define MAC_SM_TX_FC_MASK 0x000003C0
1661#define MAC_SM_TX_FC_SHIFT 6
1662#define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
1663#define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
1664#define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1665#define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1666
1667
1668
1669
1670#define REG_MIF_BIT_BANG_CLOCK 0x6200
1671
1672
1673
1674#define REG_MIF_BIT_BANG_DATA 0x6204
1675
1676#define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689#define REG_MIF_FRAME 0x620C
1690#define MIF_FRAME_START_MASK 0xC0000000
1691
1692
1693#define MIF_FRAME_ST 0x40000000
1694#define MIF_FRAME_OPCODE_MASK 0x30000000
1695
1696
1697#define MIF_FRAME_OP_READ 0x20000000
1698#define MIF_FRAME_OP_WRITE 0x10000000
1699#define MIF_FRAME_PHY_ADDR_MASK 0x0F800000
1700
1701
1702
1703
1704#define MIF_FRAME_PHY_ADDR_SHIFT 23
1705#define MIF_FRAME_REG_ADDR_MASK 0x007C0000
1706
1707
1708
1709#define MIF_FRAME_REG_ADDR_SHIFT 18
1710#define MIF_FRAME_TURN_AROUND_MSB 0x00020000
1711
1712
1713#define MIF_FRAME_TURN_AROUND_LSB 0x00010000
1714
1715
1716
1717
1718
1719
1720#define MIF_FRAME_DATA_MASK 0x0000FFFF
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734#define REG_MIF_CFG 0x6210
1735#define MIF_CFG_PHY_SELECT 0x0001
1736
1737#define MIF_CFG_POLL_EN 0x0002
1738
1739
1740#define MIF_CFG_BB_MODE 0x0004
1741
1742#define MIF_CFG_POLL_REG_MASK 0x00F8
1743
1744
1745
1746#define MIF_CFG_POLL_REG_SHIFT 3
1747#define MIF_CFG_MDIO_0 0x0100
1748
1749
1750
1751
1752
1753
1754
1755
1756#define MIF_CFG_MDIO_1 0x0200
1757
1758
1759
1760
1761
1762
1763
1764
1765#define MIF_CFG_POLL_PHY_MASK 0x7C00
1766
1767#define MIF_CFG_POLL_PHY_SHIFT 10
1768
1769
1770
1771
1772
1773
1774#define REG_MIF_MASK 0x6214
1775
1776
1777#define REG_MIF_STATUS 0x6218
1778#define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000
1779
1780
1781
1782#define MIF_STATUS_POLL_DATA_SHIFT 16
1783#define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF
1784
1785
1786
1787
1788
1789#define MIF_STATUS_POLL_STATUS_SHIFT 0
1790
1791
1792#define REG_MIF_STATE_MACHINE 0x621C
1793#define MIF_SM_CONTROL_MASK 0x07
1794
1795#define MIF_SM_EXECUTION_MASK 0x60
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809#define REG_PCS_MII_CTRL 0x9000
1810#define PCS_MII_CTRL_1000_SEL 0x0040
1811
1812#define PCS_MII_CTRL_COLLISION_TEST 0x0080
1813
1814
1815
1816#define PCS_MII_CTRL_DUPLEX 0x0100
1817
1818
1819#define PCS_MII_RESTART_AUTONEG 0x0200
1820
1821
1822#define PCS_MII_ISOLATE 0x0400
1823
1824#define PCS_MII_POWER_DOWN 0x0800
1825
1826#define PCS_MII_AUTONEG_EN 0x1000
1827
1828
1829
1830
1831
1832
1833#define PCS_MII_10_100_SEL 0x2000
1834
1835#define PCS_MII_RESET 0x8000
1836
1837
1838
1839#define REG_PCS_MII_STATUS 0x9004
1840#define PCS_MII_STATUS_EXTEND_CAP 0x0001
1841#define PCS_MII_STATUS_JABBER_DETECT 0x0002
1842#define PCS_MII_STATUS_LINK_STATUS 0x0004
1843
1844
1845
1846
1847
1848#define PCS_MII_STATUS_AUTONEG_ABLE 0x0008
1849
1850#define PCS_MII_STATUS_REMOTE_FAULT 0x0010
1851
1852
1853
1854#define PCS_MII_STATUS_AUTONEG_COMP 0x0020
1855
1856
1857
1858#define PCS_MII_STATUS_EXTEND_STATUS 0x0100
1859
1860
1861
1862
1863
1864
1865
1866#define REG_PCS_MII_ADVERT 0x9008
1867
1868#define PCS_MII_ADVERT_FD 0x0020
1869
1870#define PCS_MII_ADVERT_HD 0x0040
1871
1872#define PCS_MII_ADVERT_SYM_PAUSE 0x0080
1873
1874#define PCS_MII_ADVERT_ASYM_PAUSE 0x0100
1875
1876#define PCS_MII_ADVERT_RF_MASK 0x3000
1877
1878
1879
1880
1881
1882
1883
1884#define PCS_MII_ADVERT_ACK 0x4000
1885#define PCS_MII_ADVERT_NEXT_PAGE 0x8000
1886
1887
1888
1889
1890#define REG_PCS_MII_LPA 0x900C
1891
1892#define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
1893#define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
1894#define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE
1895#define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE
1896#define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK
1897#define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
1898#define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE
1899
1900
1901#define REG_PCS_CFG 0x9010
1902#define PCS_CFG_EN 0x01
1903
1904
1905#define PCS_CFG_SD_OVERRIDE 0x02
1906
1907
1908#define PCS_CFG_SD_ACTIVE_LOW 0x04
1909
1910
1911
1912#define PCS_CFG_JITTER_STUDY_MASK 0x18
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922#define PCS_CFG_10MS_TIMER_OVERRIDE 0x20
1923
1924
1925
1926
1927
1928#define REG_PCS_STATE_MACHINE 0x9014
1929
1930#define PCS_SM_TX_STATE_MASK 0x0000000F
1931
1932
1933
1934#define PCS_SM_RX_STATE_MASK 0x000000F0
1935
1936
1937#define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700
1938
1939#define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800
1940
1941
1942
1943
1944#define PCS_SM_LINK_STATE_MASK 0x0001E000
1945#define SM_LINK_STATE_UP 0x00016000
1946
1947#define PCS_SM_LOSS_LINK_C 0x00100000
1948
1949
1950#define PCS_SM_LOSS_LINK_SYNC 0x00200000
1951
1952#define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000
1953
1954
1955
1956#define PCS_SM_NO_LINK_BREAKLINK 0x01000000
1957
1958
1959
1960
1961
1962
1963
1964
1965#define PCS_SM_NO_LINK_SERDES 0x02000000
1966
1967
1968#define PCS_SM_NO_LINK_C 0x04000000
1969
1970#define PCS_SM_NO_LINK_SYNC 0x08000000
1971
1972#define PCS_SM_NO_LINK_WAIT_C 0x10000000
1973
1974#define PCS_SM_NO_LINK_NO_IDLE 0x20000000
1975
1976
1977
1978
1979
1980
1981
1982
1983#define REG_PCS_INTR_STATUS 0x9018
1984#define PCS_INTR_STATUS_LINK_CHANGE 0x04
1985
1986
1987
1988
1989
1990
1991#define REG_PCS_DATAPATH_MODE 0x9050
1992#define PCS_DATAPATH_MODE_MII 0x00
1993
1994
1995
1996
1997#define PCS_DATAPATH_MODE_SERDES 0x02
1998
1999
2000
2001#define REG_PCS_SERDES_CTRL 0x9054
2002#define PCS_SERDES_CTRL_LOOPBACK 0x01
2003
2004#define PCS_SERDES_CTRL_SYNCD_EN 0x02
2005
2006
2007
2008#define PCS_SERDES_CTRL_LOCKREF 0x04
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024#define REG_PCS_SHARED_OUTPUT_SEL 0x9058
2025#define PCS_SOS_PROM_ADDR_MASK 0x0007
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035#define REG_PCS_SERDES_STATE 0x905C
2036#define PCS_SERDES_STATE_MASK 0x03
2037
2038
2039
2040
2041
2042#define REG_PCS_PACKET_COUNT 0x9060
2043#define PCS_PACKET_COUNT_TX 0x000007FF
2044#define PCS_PACKET_COUNT_RX 0x07FF0000
2045
2046
2047
2048
2049
2050
2051
2052#define REG_EXPANSION_ROM_RUN_START 0x100000
2053
2054#define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2055
2056#define REG_SECOND_LOCALBUS_START 0x180000
2057
2058#define REG_SECOND_LOCALBUS_END 0x1FFFFF
2059
2060
2061#define REG_ENTROPY_START REG_SECOND_LOCALBUS_START
2062#define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
2063#define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
2064#define ENTROPY_STATUS_DRDY 0x01
2065#define ENTROPY_STATUS_BUSY 0x02
2066#define ENTROPY_STATUS_CIPHER 0x04
2067#define ENTROPY_STATUS_BYPASS_MASK 0x18
2068#define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
2069#define ENTROPY_MODE_KEY_MASK 0x07
2070#define ENTROPY_MODE_ENCRYPT 0x40
2071#define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
2072#define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
2073#define ENTROPY_RESET_DES_IO 0x01
2074#define ENTROPY_RESET_STC_MODE 0x02
2075#define ENTROPY_RESET_KEY_CACHE 0x04
2076#define ENTROPY_RESET_IV 0x08
2077#define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
2078#define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
2079#define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x))
2080
2081
2082#define PHY_LUCENT_B0 0x00437421
2083#define LUCENT_MII_REG 0x1F
2084
2085#define PHY_NS_DP83065 0x20005c78
2086#define DP83065_MII_MEM 0x16
2087#define DP83065_MII_REGD 0x1D
2088#define DP83065_MII_REGE 0x1E
2089
2090#define PHY_BROADCOM_5411 0x00206071
2091#define PHY_BROADCOM_B0 0x00206050
2092#define BROADCOM_MII_REG4 0x14
2093#define BROADCOM_MII_REG5 0x15
2094#define BROADCOM_MII_REG7 0x17
2095#define BROADCOM_MII_REG8 0x18
2096
2097#define CAS_MII_ANNPTR 0x07
2098#define CAS_MII_ANNPRR 0x08
2099#define CAS_MII_1000_CTRL 0x09
2100#define CAS_MII_1000_STATUS 0x0A
2101#define CAS_MII_1000_EXTEND 0x0F
2102
2103#define CAS_BMSR_1000_EXTEND 0x0100
2104
2105
2106
2107
2108
2109
2110#define CAS_BMCR_SPEED1000 0x0040
2111
2112#define CAS_ADVERTISE_1000HALF 0x0100
2113#define CAS_ADVERTISE_1000FULL 0x0200
2114#define CAS_ADVERTISE_PAUSE 0x0400
2115#define CAS_ADVERTISE_ASYM_PAUSE 0x0800
2116
2117
2118#define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE
2119#define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE
2120
2121
2122#define CAS_LPA_1000HALF 0x0400
2123#define CAS_LPA_1000FULL 0x0800
2124
2125#define CAS_EXTEND_1000XFULL 0x8000
2126#define CAS_EXTEND_1000XHALF 0x4000
2127#define CAS_EXTEND_1000TFULL 0x2000
2128#define CAS_EXTEND_1000THALF 0x1000
2129
2130
2131typedef struct cas_hp_inst {
2132 const char *note;
2133
2134 u16 mask, val;
2135
2136 u8 op;
2137 u8 soff, snext;
2138 u8 foff, fnext;
2139
2140 u8 outop;
2141
2142 u16 outarg;
2143 u8 outenab;
2144
2145 u8 outshift;
2146 u16 outmask;
2147} cas_hp_inst_t;
2148
2149
2150#define OP_EQ 0
2151#define OP_LT 1
2152#define OP_GT 2
2153#define OP_NP 3
2154
2155
2156#define CL_REG 0
2157#define LD_FID 1
2158#define LD_SEQ 2
2159#define LD_CTL 3
2160#define LD_SAP 4
2161#define LD_R1 5
2162#define LD_L3 6
2163#define LD_SUM 7
2164#define LD_HDR 8
2165#define IM_FID 9
2166#define IM_SEQ 10
2167#define IM_SAP 11
2168#define IM_R1 12
2169#define IM_CTL 13
2170#define LD_LEN 14
2171#define ST_FLG 15
2172
2173
2174#define S1_PCKT 0
2175#define S1_VLAN 1
2176#define S1_CFI 2
2177#define S1_8023 3
2178#define S1_LLC 4
2179#define S1_LLCc 5
2180#define S1_IPV4 6
2181#define S1_IPV4c 7
2182#define S1_IPV4F 8
2183#define S1_TCP44 9
2184#define S1_IPV6 10
2185#define S1_IPV6L 11
2186#define S1_IPV6c 12
2187#define S1_TCP64 13
2188#define S1_TCPSQ 14
2189#define S1_TCPFG 15
2190#define S1_TCPHL 16
2191#define S1_TCPHc 17
2192#define S1_CLNP 18
2193#define S1_CLNP2 19
2194#define S1_DROP 20
2195#define S2_HTTP 21
2196#define S1_ESP4 22
2197#define S1_AH4 23
2198#define S1_ESP6 24
2199#define S1_AH6 25
2200
2201#define CAS_PROG_IP46TCP4_PREAMBLE \
2202{ "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, \
2203 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2204{ "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, \
2205 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
2206{ "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, \
2207 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2208{ "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, \
2209 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2210{ "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, \
2211 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2212{ "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
2213 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2214{ "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, \
2215 LD_SAP, 0x100, 3, 0x0, 0xffff}, \
2216{ "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, \
2217 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
2218{ "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, \
2219 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
2220{ "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, \
2221 LD_FID, 0x182, 1, 0x0, 0xffff}, \
2222{ "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, \
2223 LD_SUM, 0x015, 1, 0x0, 0x0000}, \
2224{ "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, \
2225 IM_R1, 0x128, 1, 0x0, 0xffff}, \
2226{ "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, \
2227 LD_FID, 0x484, 1, 0x0, 0xffff}, \
2228{ "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \
2229 LD_LEN, 0x03f, 1, 0x0, 0xffff}
2230
2231#ifdef USE_HP_IP46TCP4
2232static cas_hp_inst_t cas_prog_ip46tcp4tab[] = {
2233 CAS_PROG_IP46TCP4_PREAMBLE,
2234 { "TCP seq",
2235 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2236 0x081, 3, 0x0, 0xffff},
2237 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2238 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f},
2239 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2240 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2241 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2242 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2243 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2244 IM_CTL, 0x001, 3, 0x0, 0x0001},
2245 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2246 IM_CTL, 0x000, 0, 0x0, 0x0000},
2247 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2248 IM_CTL, 0x080, 3, 0x0, 0xffff},
2249 { NULL },
2250};
2251#ifdef HP_IP46TCP4_DEFAULT
2252#define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab
2253#endif
2254#endif
2255
2256
2257
2258
2259
2260#ifdef USE_HP_IP46TCP4NOHTTP
2261static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = {
2262 CAS_PROG_IP46TCP4_PREAMBLE,
2263 { "TCP seq",
2264 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2265 0x081, 3, 0x0, 0xffff} ,
2266 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2267 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, },
2268 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2269 LD_R1, 0x205, 3, 0xB, 0xf000},
2270 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2271 LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2272 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2273 IM_CTL, 0x001, 3, 0x0, 0x0001},
2274 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2275 CL_REG, 0x002, 3, 0x0, 0x0000},
2276 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2277 IM_CTL, 0x080, 3, 0x0, 0xffff},
2278 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2279 IM_CTL, 0x044, 3, 0x0, 0xffff},
2280 { NULL },
2281};
2282#ifdef HP_IP46TCP4NOHTTP_DEFAULT
2283#define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab
2284#endif
2285#endif
2286
2287
2288#define S3_IPV6c 11
2289#define S3_TCP64 12
2290#define S3_TCPSQ 13
2291#define S3_TCPFG 14
2292#define S3_TCPHL 15
2293#define S3_TCPHc 16
2294#define S3_FRAG 17
2295#define S3_FOFF 18
2296#define S3_CLNP 19
2297
2298#ifdef USE_HP_IP4FRAG
2299static cas_hp_inst_t cas_prog_ip4fragtab[] = {
2300 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT,
2301 CL_REG, 0x3ff, 1, 0x0, 0x0000},
2302 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2303 IM_CTL, 0x00a, 3, 0x0, 0xffff},
2304 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S3_CLNP, 1, S1_8023,
2305 CL_REG, 0x000, 0, 0x0, 0x0000},
2306 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2307 CL_REG, 0x000, 0, 0x0, 0x0000},
2308 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S3_CLNP,
2309 CL_REG, 0x000, 0, 0x0, 0x0000},
2310 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
2311 CL_REG, 0x000, 0, 0x0, 0x0000},
2312 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2313 LD_SAP, 0x100, 3, 0x0, 0xffff},
2314 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S3_CLNP,
2315 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2316 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S3_FRAG,
2317 LD_LEN, 0x03e, 3, 0x0, 0xffff},
2318 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S3_TCPSQ, 0, S3_CLNP,
2319 LD_FID, 0x182, 3, 0x0, 0xffff},
2320 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S3_IPV6c, 0, S3_CLNP,
2321 LD_SUM, 0x015, 1, 0x0, 0x0000},
2322 { "IPV6 cont?", 0xf000, 0x6000, OP_EQ, 3, S3_TCP64, 0, S3_CLNP,
2323 LD_FID, 0x484, 1, 0x0, 0xffff},
2324 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP,
2325 LD_LEN, 0x03f, 1, 0x0, 0xffff},
2326 { "TCP seq",
2327 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ,
2328 0x081, 3, 0x0, 0xffff},
2329 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0,
2330 S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f},
2331 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc,
2332 LD_R1, 0x205, 3, 0xB, 0xf000},
2333 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2334 LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2335 { "IP4 Fragment", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2336 LD_FID, 0x103, 3, 0x0, 0xffff},
2337 { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2338 LD_SEQ, 0x040, 1, 0xD, 0xfff8},
2339 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2340 IM_CTL, 0x001, 3, 0x0, 0x0001},
2341 { NULL },
2342};
2343#ifdef HP_IP4FRAG_DEFAULT
2344#define CAS_HP_FIRMWARE cas_prog_ip4fragtab
2345#endif
2346#endif
2347
2348
2349
2350
2351#ifdef USE_HP_IP46TCP4BATCH
2352static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = {
2353 CAS_PROG_IP46TCP4_PREAMBLE,
2354 { "TCP seq",
2355 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ,
2356 0x081, 3, 0x0, 0xffff},
2357 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2358 S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000},
2359 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2360 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2361 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2362 S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff},
2363 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2364 IM_CTL, 0x001, 3, 0x0, 0x0001},
2365 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2366 S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff},
2367 { NULL },
2368};
2369#ifdef HP_IP46TCP4BATCH_DEFAULT
2370#define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab
2371#endif
2372#endif
2373
2374
2375
2376
2377
2378#ifdef USE_HP_WORKAROUND
2379static cas_hp_inst_t cas_prog_workaroundtab[] = {
2380 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2381 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} ,
2382 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2383 IM_CTL, 0x04a, 3, 0x0, 0xffff},
2384 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2385 CL_REG, 0x000, 0, 0x0, 0x0000},
2386 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2387 CL_REG, 0x000, 0, 0x0, 0x0000},
2388 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2389 CL_REG, 0x000, 0, 0x0, 0x0000},
2390 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2391 CL_REG, 0x000, 0, 0x0, 0x0000},
2392 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2393 IM_SAP, 0x6AE, 3, 0x0, 0xffff},
2394 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2395 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2396 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2397 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2398 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP,
2399 LD_FID, 0x182, 3, 0x0, 0xffff},
2400 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2401 LD_SUM, 0x015, 1, 0x0, 0x0000},
2402 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2403 IM_R1, 0x128, 1, 0x0, 0xffff},
2404 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2405 LD_FID, 0x484, 1, 0x0, 0xffff},
2406 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP,
2407 LD_LEN, 0x03f, 1, 0x0, 0xffff},
2408 { "TCP seq",
2409 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2410 0x081, 3, 0x0, 0xffff},
2411 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2412 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f},
2413 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2414 LD_R1, 0x205, 3, 0xB, 0xf000},
2415 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2416 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2417 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2418 IM_SAP, 0x6AE, 3, 0x0, 0xffff} ,
2419 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2420 IM_CTL, 0x001, 3, 0x0, 0x0001},
2421 { NULL },
2422};
2423#ifdef HP_WORKAROUND_DEFAULT
2424#define CAS_HP_FIRMWARE cas_prog_workaroundtab
2425#endif
2426#endif
2427
2428#ifdef USE_HP_ENCRYPT
2429static cas_hp_inst_t cas_prog_encryptiontab[] = {
2430 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2431 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000},
2432 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2433 IM_CTL, 0x00a, 3, 0x0, 0xffff},
2434#if 0
2435
2436
2437 00,
2438#endif
2439 { "CFI?",
2440 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2441 CL_REG, 0x000, 0, 0x0, 0x0000},
2442 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2443 CL_REG, 0x000, 0, 0x0, 0x0000},
2444 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2445 CL_REG, 0x000, 0, 0x0, 0x0000},
2446 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2447 CL_REG, 0x000, 0, 0x0, 0x0000},
2448 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2449 LD_SAP, 0x100, 3, 0x0, 0xffff},
2450 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2451 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2452 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2453 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2454 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4,
2455 LD_FID, 0x182, 1, 0x0, 0xffff},
2456 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2457 LD_SUM, 0x015, 1, 0x0, 0x0000},
2458 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2459 IM_R1, 0x128, 1, 0x0, 0xffff},
2460 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2461 LD_FID, 0x484, 1, 0x0, 0xffff},
2462 { "TCP64?",
2463#if 0
2464
2465#endif
2466 0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6, LD_LEN,
2467 0x03f, 1, 0x0, 0xffff},
2468 { "TCP seq",
2469 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2470 0x081, 3, 0x0, 0xffff},
2471 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2472 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f},
2473 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2474 LD_R1, 0x205, 3, 0xB, 0xf000} ,
2475 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2476 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2477 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2478 IM_CTL, 0x001, 3, 0x0, 0x0001},
2479 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2480 CL_REG, 0x002, 3, 0x0, 0x0000},
2481 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2482 IM_CTL, 0x080, 3, 0x0, 0xffff},
2483 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2484 IM_CTL, 0x044, 3, 0x0, 0xffff},
2485 { "IPV4 ESP encrypted?",
2486 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL,
2487 0x021, 1, 0x0, 0xffff},
2488 { "IPV4 AH encrypted?",
2489 0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2490 0x021, 1, 0x0, 0xffff},
2491 { "IPV6 ESP encrypted?",
2492#if 0
2493
2494#endif
2495 0xff00, 0x3200, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL,
2496 0x021, 1, 0x0, 0xffff},
2497 { "IPV6 AH encrypted?",
2498#if 0
2499
2500#endif
2501 0xff00, 0x3300, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2502 0x021, 1, 0x0, 0xffff},
2503 { NULL },
2504};
2505#ifdef HP_ENCRYPT_DEFAULT
2506#define CAS_HP_FIRMWARE cas_prog_encryptiontab
2507#endif
2508#endif
2509
2510static cas_hp_inst_t cas_prog_null[] = { {NULL} };
2511#ifdef HP_NULL_DEFAULT
2512#define CAS_HP_FIRMWARE cas_prog_null
2513#endif
2514
2515
2516#define CAS_PHY_UNKNOWN 0x00
2517#define CAS_PHY_SERDES 0x01
2518#define CAS_PHY_MII_MDIO0 0x02
2519#define CAS_PHY_MII_MDIO1 0x04
2520#define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533#define DESC_RING_I_TO_S(x) (32*(1 << (x)))
2534#define COMP_RING_I_TO_S(x) (128*(1 << (x)))
2535#define TX_DESC_RING_INDEX 4
2536#define RX_DESC_RING_INDEX 4
2537#define RX_COMP_RING_INDEX 4
2538
2539#if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2540#error TX_DESC_RING_INDEX must be between 0 and 8
2541#endif
2542
2543#if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2544#error RX_DESC_RING_INDEX must be between 0 and 8
2545#endif
2546
2547#if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2548#error RX_COMP_RING_INDEX must be between 0 and 8
2549#endif
2550
2551#define N_TX_RINGS MAX_TX_RINGS
2552#define N_TX_RINGS_MASK MAX_TX_RINGS_MASK
2553#define N_RX_DESC_RINGS MAX_RX_DESC_RINGS
2554#define N_RX_COMP_RINGS 0x1
2555
2556
2557#define N_RX_FLOWS 64
2558
2559#define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
2560#define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
2561#define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
2562#define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
2563#define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
2564#define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
2565#define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE
2566#define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE
2567#define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE
2568
2569
2570#define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))
2571#define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))
2572#define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \
2573 TX_CFG_DESC_RINGN_SHIFT(y)) & \
2574 TX_CFG_DESC_RINGN_MASK(y))
2575
2576
2577#define CAS_MIN_PAGE_SHIFT 11
2578#define CAS_JUMBO_PAGE_SHIFT 13
2579#define CAS_MAX_PAGE_SHIFT 14
2580
2581#define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL
2582
2583#define TX_DESC_BUFLEN_SHIFT 0
2584#define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL
2585
2586
2587
2588
2589
2590#define TX_DESC_CSUM_START_SHIFT 15
2591#define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL
2592
2593
2594
2595
2596#define TX_DESC_CSUM_STUFF_SHIFT 21
2597#define TX_DESC_CSUM_EN 0x0000000020000000ULL
2598#define TX_DESC_EOF 0x0000000040000000ULL
2599#define TX_DESC_SOF 0x0000000080000000ULL
2600#define TX_DESC_INTME 0x0000000100000000ULL
2601#define TX_DESC_NO_CRC 0x0000000200000000ULL
2602
2603
2604
2605struct cas_tx_desc {
2606 __le64 control;
2607 __le64 buffer;
2608};
2609
2610
2611
2612
2613
2614struct cas_rx_desc {
2615 __le64 index;
2616 __le64 buffer;
2617};
2618
2619
2620
2621#define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
2622#define RX_COMP1_DATA_SIZE_SHIFT 13
2623#define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
2624#define RX_COMP1_DATA_OFF_SHIFT 27
2625#define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
2626#define RX_COMP1_DATA_INDEX_SHIFT 41
2627#define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
2628#define RX_COMP1_SKIP_SHIFT 55
2629#define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
2630#define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
2631#define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
2632#define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
2633#define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
2634#define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
2635#define RX_COMP1_TYPE_SHIFT 62
2636
2637
2638#define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
2639#define RX_COMP2_NEXT_INDEX_SHIFT 21
2640#define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
2641#define RX_COMP2_HDR_SIZE_SHIFT 35
2642#define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
2643#define RX_COMP2_HDR_OFF_SHIFT 44
2644#define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
2645#define RX_COMP2_HDR_INDEX_SHIFT 50
2646
2647
2648#define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
2649#define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
2650#define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
2651#define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
2652#define RX_COMP3_CSUM_START_SHIFT 12
2653#define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
2654#define RX_COMP3_FLOWID_SHIFT 19
2655#define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
2656#define RX_COMP3_OPCODE_SHIFT 25
2657#define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
2658#define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
2659#define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
2660#define RX_COMP3_LOAD_BAL_SHIFT 35
2661#define RX_PLUS_COMP3_ENC_PKT 0x0000020000000000ULL
2662#define RX_COMP3_L3_HEAD_OFF_MASK 0x0000FE0000000000ULL
2663#define RX_COMP3_L3_HEAD_OFF_SHIFT 41
2664#define RX_PLUS_COMP_L3_HEAD_OFF_MASK 0x0000FC0000000000ULL
2665#define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42
2666#define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
2667#define RX_COMP3_SAP_SHIFT 48
2668
2669
2670#define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
2671#define RX_COMP4_TCP_CSUM_SHIFT 0
2672#define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
2673#define RX_COMP4_PKT_LEN_SHIFT 16
2674#define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
2675#define RX_COMP4_PERFECT_MATCH_SHIFT 30
2676#define RX_COMP4_ZERO 0x0000080000000000ULL
2677#define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
2678#define RX_COMP4_HASH_VAL_SHIFT 44
2679#define RX_COMP4_HASH_PASS 0x1000000000000000ULL
2680#define RX_COMP4_BAD 0x4000000000000000ULL
2681#define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
2682
2683
2684
2685
2686
2687#define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
2688#define RX_INDEX_NUM_SHIFT 0
2689#define RX_INDEX_RING_MASK 0x0000000000001000ULL
2690#define RX_INDEX_RING_SHIFT 12
2691#define RX_INDEX_RELEASE 0x0000000000002000ULL
2692
2693struct cas_rx_comp {
2694 __le64 word1;
2695 __le64 word2;
2696 __le64 word3;
2697 __le64 word4;
2698};
2699
2700enum link_state {
2701 link_down = 0,
2702 link_aneg,
2703 link_force_try,
2704 link_force_ret,
2705 link_force_ok,
2706 link_up
2707};
2708
2709typedef struct cas_page {
2710 struct list_head list;
2711 struct page *buffer;
2712 dma_addr_t dma_addr;
2713 int used;
2714} cas_page_t;
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728#define INIT_BLOCK_TX (TX_DESC_RING_SIZE)
2729#define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE)
2730#define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE)
2731
2732struct cas_init_block {
2733 struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP];
2734 struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC];
2735 struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX];
2736 __le64 tx_compwb;
2737};
2738
2739
2740
2741
2742
2743#define TX_TINY_BUF_LEN 0x100
2744#define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
2745
2746struct cas_tiny_count {
2747 int nbufs;
2748 int used;
2749};
2750
2751struct cas {
2752 spinlock_t lock;
2753 spinlock_t tx_lock[N_TX_RINGS];
2754 spinlock_t stat_lock[N_TX_RINGS + 1];
2755 spinlock_t rx_inuse_lock;
2756 spinlock_t rx_spare_lock;
2757
2758 void __iomem *regs;
2759 int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS];
2760 int rx_old[N_RX_DESC_RINGS];
2761 int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS];
2762 int rx_last[N_RX_DESC_RINGS];
2763
2764 struct napi_struct napi;
2765
2766
2767
2768 int hw_running;
2769 int opened;
2770 struct mutex pm_mutex;
2771
2772 struct cas_init_block *init_block;
2773 struct cas_tx_desc *init_txds[MAX_TX_RINGS];
2774 struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS];
2775 struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS];
2776
2777
2778
2779 struct sk_buff *tx_skbs[N_TX_RINGS][TX_DESC_RING_SIZE];
2780 struct sk_buff_head rx_flows[N_RX_FLOWS];
2781 cas_page_t *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE];
2782 struct list_head rx_spare_list, rx_inuse_list;
2783 int rx_spares_needed;
2784
2785
2786
2787 struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE];
2788 u8 *tx_tiny_bufs[N_TX_RINGS];
2789
2790 u32 msg_enable;
2791
2792
2793 struct net_device_stats net_stats[N_TX_RINGS + 1];
2794
2795 u32 pci_cfg[64 >> 2];
2796 u8 pci_revision;
2797
2798 int phy_type;
2799 int phy_addr;
2800 u32 phy_id;
2801#define CAS_FLAG_1000MB_CAP 0x00000001
2802#define CAS_FLAG_REG_PLUS 0x00000002
2803#define CAS_FLAG_TARGET_ABORT 0x00000004
2804#define CAS_FLAG_SATURN 0x00000008
2805#define CAS_FLAG_RXD_POST_MASK 0x000000F0
2806#define CAS_FLAG_RXD_POST_SHIFT 4
2807#define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
2808 CAS_FLAG_RXD_POST_MASK)
2809#define CAS_FLAG_ENTROPY_DEV 0x00000100
2810#define CAS_FLAG_NO_HW_CSUM 0x00000200
2811 u32 cas_flags;
2812 int packet_min;
2813 int tx_fifo_size;
2814 int rx_fifo_size;
2815 int rx_pause_off;
2816 int rx_pause_on;
2817 int crc_size;
2818
2819 int pci_irq_INTC;
2820 int min_frame_size;
2821
2822
2823 int page_size;
2824 int page_order;
2825 int mtu_stride;
2826
2827 u32 mac_rx_cfg;
2828
2829
2830 int link_cntl;
2831 int link_fcntl;
2832 enum link_state lstate;
2833 struct timer_list link_timer;
2834 int timer_ticks;
2835 struct work_struct reset_task;
2836#if 0
2837 atomic_t reset_task_pending;
2838#else
2839 atomic_t reset_task_pending;
2840 atomic_t reset_task_pending_mtu;
2841 atomic_t reset_task_pending_spare;
2842 atomic_t reset_task_pending_all;
2843#endif
2844
2845
2846#define LINK_TRANSITION_UNKNOWN 0
2847#define LINK_TRANSITION_ON_FAILURE 1
2848#define LINK_TRANSITION_STILL_FAILED 2
2849#define LINK_TRANSITION_LINK_UP 3
2850#define LINK_TRANSITION_LINK_CONFIG 4
2851#define LINK_TRANSITION_LINK_DOWN 5
2852#define LINK_TRANSITION_REQUESTED_RESET 6
2853 int link_transition;
2854 int link_transition_jiffies_valid;
2855 unsigned long link_transition_jiffies;
2856
2857
2858 u8 orig_cacheline_size;
2859#define CAS_PREF_CACHELINE_SIZE 0x20
2860
2861
2862 int casreg_len;
2863 u64 pause_entered;
2864 u16 pause_last_time_recvd;
2865
2866 dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
2867 struct pci_dev *pdev;
2868 struct net_device *dev;
2869#if defined(CONFIG_OF)
2870 struct device_node *of_node;
2871#endif
2872
2873
2874 u16 fw_load_addr;
2875 u32 fw_size;
2876 u8 *fw_data;
2877};
2878
2879#define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2880#define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2881#define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2882
2883#define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2884 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2885
2886#define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2887 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2888 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2889
2890#define CAS_ALIGN(addr, align) \
2891 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
2892
2893#define RX_FIFO_SIZE 16384
2894#define EXPANSION_ROM_SIZE 65536
2895
2896#define CAS_MC_EXACT_MATCH_SIZE 15
2897#define CAS_MC_HASH_SIZE 256
2898#define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \
2899 CAS_MC_HASH_SIZE)
2900
2901#define TX_TARGET_ABORT_LEN 0x20
2902#define RX_SWIVEL_OFF_VAL 0x2
2903#define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1)
2904#define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1)
2905#define RX_BLANK_INTR_PKT_VAL 0x05
2906#define RX_BLANK_INTR_TIME_VAL 0x0F
2907#define HP_TCP_THRESH_VAL 1530
2908
2909#define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1)
2910#define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2)
2911
2912#endif
2913