LXR linux/drivers/pci/hotplug/pciehp

   1/*
   2 * PCI Express PCI Hot Plug Driver
   3 *
   4 * Copyright (C) 1995,2001 Compaq Computer Corporation
   5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6 * Copyright (C) 2001 IBM Corp.
   7 * Copyright (C) 2003-2004 Intel Corporation
   8 *
   9 * All rights reserved.
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or (at
  14 * your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful, but
  17 * WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19 * NON INFRINGEMENT.  See the GNU General Public License for more
  20 * details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25 *
  26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27 *
  28 */
  29
  30#include <linux/kernel.h>
  31#include <linux/module.h>
  32#include <linux/types.h>
  33#include <linux/signal.h>
  34#include <linux/jiffies.h>
  35#include <linux/timer.h>
  36#include <linux/pci.h>
  37#include <linux/interrupt.h>
  38#include <linux/time.h>
  39#include <linux/slab.h>
  40
  41#include "../pci.h"
  42#include "pciehp.h"
  43
  44static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
  45{
  46        return ctrl->pcie->port;
  47}
  48
  49static irqreturn_t pcie_isr(int irq, void *dev_id);
  50static void start_int_poll_timer(struct controller *ctrl, int sec);
  51
  52/* This is the interrupt polling timeout function. */
  53static void int_poll_timeout(unsigned long data)
  54{
  55        struct controller *ctrl = (struct controller *)data;
  56
  57        /* Poll for interrupt events.  regs == NULL => polling */
  58        pcie_isr(0, ctrl);
  59
  60        init_timer(&ctrl->poll_timer);
  61        if (!pciehp_poll_time)
  62                pciehp_poll_time = 2; /* default polling interval is 2 sec */
  63
  64        start_int_poll_timer(ctrl, pciehp_poll_time);
  65}
  66
  67/* This function starts the interrupt polling timer. */
  68static void start_int_poll_timer(struct controller *ctrl, int sec)
  69{
  70        /* Clamp to sane value */
  71        if ((sec <= 0) || (sec > 60))
  72                sec = 2;
  73
  74        ctrl->poll_timer.function = &int_poll_timeout;
  75        ctrl->poll_timer.data = (unsigned long)ctrl;
  76        ctrl->poll_timer.expires = jiffies + sec * HZ;
  77        add_timer(&ctrl->poll_timer);
  78}
  79
  80static inline int pciehp_request_irq(struct controller *ctrl)
  81{
  82        int retval, irq = ctrl->pcie->irq;
  83
  84        /* Install interrupt polling timer. Start with 10 sec delay */
  85        if (pciehp_poll_mode) {
  86                init_timer(&ctrl->poll_timer);
  87                start_int_poll_timer(ctrl, 10);
  88                return 0;
  89        }
  90
  91        /* Installs the interrupt handler */
  92        retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
  93        if (retval)
  94                ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
  95                         irq);
  96        return retval;
  97}
  98
  99static inline void pciehp_free_irq(struct controller *ctrl)
 100{
 101        if (pciehp_poll_mode)
 102                del_timer_sync(&ctrl->poll_timer);
 103        else
 104                free_irq(ctrl->pcie->irq, ctrl);
 105}
 106
 107static int pcie_poll_cmd(struct controller *ctrl, int timeout)
 108{
 109        struct pci_dev *pdev = ctrl_dev(ctrl);
 110        u16 slot_status;
 111
 112        pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 113        if (slot_status & PCI_EXP_SLTSTA_CC) {
 114                pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 115                                           PCI_EXP_SLTSTA_CC);
 116                return 1;
 117        }
 118        while (timeout > 0) {
 119                msleep(10);
 120                timeout -= 10;
 121                pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 122                if (slot_status & PCI_EXP_SLTSTA_CC) {
 123                        pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 124                                                   PCI_EXP_SLTSTA_CC);
 125                        return 1;
 126                }
 127        }
 128        return 0;       /* timeout */
 129}
 130
 131static void pcie_wait_cmd(struct controller *ctrl)
 132{
 133        unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 134        unsigned long duration = msecs_to_jiffies(msecs);
 135        unsigned long cmd_timeout = ctrl->cmd_started + duration;
 136        unsigned long now, timeout;
 137        int rc;
 138
 139        /*
 140         * If the controller does not generate notifications for command
 141         * completions, we never need to wait between writes.
 142         */
 143        if (NO_CMD_CMPL(ctrl))
 144                return;
 145
 146        if (!ctrl->cmd_busy)
 147                return;
 148
 149        /*
 150         * Even if the command has already timed out, we want to call
 151         * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
 152         */
 153        now = jiffies;
 154        if (time_before_eq(cmd_timeout, now))
 155                timeout = 1;
 156        else
 157                timeout = cmd_timeout - now;
 158
 159        if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
 160            ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
 161                rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 162        else
 163                rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
 164
 165        /*
 166         * Controllers with errata like Intel CF118 don't generate
 167         * completion notifications unless the power/indicator/interlock
 168         * control bits are changed.  On such controllers, we'll emit this
 169         * timeout message when we wait for completion of commands that
 170         * don't change those bits, e.g., commands that merely enable
 171         * interrupts.
 172         */
 173        if (!rc)
 174                ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
 175                          ctrl->slot_ctrl,
 176                          jiffies_to_msecs(jiffies - ctrl->cmd_started));
 177}
 178
 179static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
 180                              u16 mask, bool wait)
 181{
 182        struct pci_dev *pdev = ctrl_dev(ctrl);
 183        u16 slot_ctrl;
 184
 185        mutex_lock(&ctrl->ctrl_lock);
 186
 187        /*
 188         * Always wait for any previous command that might still be in progress
 189         */
 190        pcie_wait_cmd(ctrl);
 191
 192        pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 193        slot_ctrl &= ~mask;
 194        slot_ctrl |= (cmd & mask);
 195        ctrl->cmd_busy = 1;
 196        smp_mb();
 197        pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
 198        ctrl->cmd_started = jiffies;
 199        ctrl->slot_ctrl = slot_ctrl;
 200
 201        /*
 202         * Optionally wait for the hardware to be ready for a new command,
 203         * indicating completion of the above issued command.
 204         */
 205        if (wait)
 206                pcie_wait_cmd(ctrl);
 207
 208        mutex_unlock(&ctrl->ctrl_lock);
 209}
 210
 211/**
 212 * pcie_write_cmd - Issue controller command
 213 * @ctrl: controller to which the command is issued
 214 * @cmd:  command value written to slot control register
 215 * @mask: bitmask of slot control register to be modified
 216 */
 217static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 218{
 219        pcie_do_write_cmd(ctrl, cmd, mask, true);
 220}
 221
 222/* Same as above without waiting for the hardware to latch */
 223static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
 224{
 225        pcie_do_write_cmd(ctrl, cmd, mask, false);
 226}
 227
 228bool pciehp_check_link_active(struct controller *ctrl)
 229{
 230        struct pci_dev *pdev = ctrl_dev(ctrl);
 231        u16 lnk_status;
 232        bool ret;
 233
 234        pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 235        ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
 236
 237        if (ret)
 238                ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 239
 240        return ret;
 241}
 242
 243static void __pcie_wait_link_active(struct controller *ctrl, bool active)
 244{
 245        int timeout = 1000;
 246
 247        if (pciehp_check_link_active(ctrl) == active)
 248                return;
 249        while (timeout > 0) {
 250                msleep(10);
 251                timeout -= 10;
 252                if (pciehp_check_link_active(ctrl) == active)
 253                        return;
 254        }
 255        ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
 256                        active ? "set" : "cleared");
 257}
 258
 259static void pcie_wait_link_active(struct controller *ctrl)
 260{
 261        __pcie_wait_link_active(ctrl, true);
 262}
 263
 264static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
 265{
 266        u32 l;
 267        int count = 0;
 268        int delay = 1000, step = 20;
 269        bool found = false;
 270
 271        do {
 272                found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
 273                count++;
 274
 275                if (found)
 276                        break;
 277
 278                msleep(step);
 279                delay -= step;
 280        } while (delay > 0);
 281
 282        if (count > 1 && pciehp_debug)
 283                printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
 284                        pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
 285                        PCI_FUNC(devfn), count, step, l);
 286
 287        return found;
 288}
 289
 290int pciehp_check_link_status(struct controller *ctrl)
 291{
 292        struct pci_dev *pdev = ctrl_dev(ctrl);
 293        bool found;
 294        u16 lnk_status;
 295
 296        /*
 297         * Data Link Layer Link Active Reporting must be capable for
 298         * hot-plug capable downstream port. But old controller might
 299         * not implement it. In this case, we wait for 1000 ms.
 300        */
 301        if (ctrl->link_active_reporting)
 302                pcie_wait_link_active(ctrl);
 303        else
 304                msleep(1000);
 305
 306        /* wait 100ms before read pci conf, and try in 1s */
 307        msleep(100);
 308        found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
 309                                        PCI_DEVFN(0, 0));
 310
 311        pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 312        ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 313        if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 314            !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 315                ctrl_err(ctrl, "link training error: status %#06x\n",
 316                         lnk_status);
 317                return -1;
 318        }
 319
 320        pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 321
 322        if (!found)
 323                return -1;
 324
 325        return 0;
 326}
 327
 328static int __pciehp_link_set(struct controller *ctrl, bool enable)
 329{
 330        struct pci_dev *pdev = ctrl_dev(ctrl);
 331        u16 lnk_ctrl;
 332
 333        pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
 334
 335        if (enable)
 336                lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
 337        else
 338                lnk_ctrl |= PCI_EXP_LNKCTL_LD;
 339
 340        pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
 341        ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
 342        return 0;
 343}
 344
 345static int pciehp_link_enable(struct controller *ctrl)
 346{
 347        return __pciehp_link_set(ctrl, true);
 348}
 349
 350void pciehp_get_attention_status(struct slot *slot, u8 *status)
 351{
 352        struct controller *ctrl = slot->ctrl;
 353        struct pci_dev *pdev = ctrl_dev(ctrl);
 354        u16 slot_ctrl;
 355
 356        pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 357        ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 358                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 359
 360        switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
 361        case PCI_EXP_SLTCTL_ATTN_IND_ON:
 362                *status = 1;    /* On */
 363                break;
 364        case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
 365                *status = 2;    /* Blink */
 366                break;
 367        case PCI_EXP_SLTCTL_ATTN_IND_OFF:
 368                *status = 0;    /* Off */
 369                break;
 370        default:
 371                *status = 0xFF;
 372                break;
 373        }
 374}
 375
 376void pciehp_get_power_status(struct slot *slot, u8 *status)
 377{
 378        struct controller *ctrl = slot->ctrl;
 379        struct pci_dev *pdev = ctrl_dev(ctrl);
 380        u16 slot_ctrl;
 381
 382        pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 383        ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 384                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 385
 386        switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
 387        case PCI_EXP_SLTCTL_PWR_ON:
 388                *status = 1;    /* On */
 389                break;
 390        case PCI_EXP_SLTCTL_PWR_OFF:
 391                *status = 0;    /* Off */
 392                break;
 393        default:
 394                *status = 0xFF;
 395                break;
 396        }
 397}
 398
 399void pciehp_get_latch_status(struct slot *slot, u8 *status)
 400{
 401        struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 402        u16 slot_status;
 403
 404        pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 405        *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 406}
 407
 408void pciehp_get_adapter_status(struct slot *slot, u8 *status)
 409{
 410        struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 411        u16 slot_status;
 412
 413        pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 414        *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 415}
 416
 417int pciehp_query_power_fault(struct slot *slot)
 418{
 419        struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 420        u16 slot_status;
 421
 422        pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 423        return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 424}
 425
 426void pciehp_set_attention_status(struct slot *slot, u8 value)
 427{
 428        struct controller *ctrl = slot->ctrl;
 429        u16 slot_cmd;
 430
 431        if (!ATTN_LED(ctrl))
 432                return;
 433
 434        switch (value) {
 435        case 0:         /* turn off */
 436                slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
 437                break;
 438        case 1:         /* turn on */
 439                slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
 440                break;
 441        case 2:         /* turn blink */
 442                slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
 443                break;
 444        default:
 445                return;
 446        }
 447        pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
 448        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 449                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 450}
 451
 452void pciehp_green_led_on(struct slot *slot)
 453{
 454        struct controller *ctrl = slot->ctrl;
 455
 456        if (!PWR_LED(ctrl))
 457                return;
 458
 459        pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
 460                              PCI_EXP_SLTCTL_PIC);
 461        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 462                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 463                 PCI_EXP_SLTCTL_PWR_IND_ON);
 464}
 465
 466void pciehp_green_led_off(struct slot *slot)
 467{
 468        struct controller *ctrl = slot->ctrl;
 469
 470        if (!PWR_LED(ctrl))
 471                return;
 472
 473        pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
 474                              PCI_EXP_SLTCTL_PIC);
 475        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 476                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 477                 PCI_EXP_SLTCTL_PWR_IND_OFF);
 478}
 479
 480void pciehp_green_led_blink(struct slot *slot)
 481{
 482        struct controller *ctrl = slot->ctrl;
 483
 484        if (!PWR_LED(ctrl))
 485                return;
 486
 487        pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
 488                              PCI_EXP_SLTCTL_PIC);
 489        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 490                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 491                 PCI_EXP_SLTCTL_PWR_IND_BLINK);
 492}
 493
 494int pciehp_power_on_slot(struct slot *slot)
 495{
 496        struct controller *ctrl = slot->ctrl;
 497        struct pci_dev *pdev = ctrl_dev(ctrl);
 498        u16 slot_status;
 499        int retval;
 500
 501        /* Clear sticky power-fault bit from previous power failures */
 502        pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 503        if (slot_status & PCI_EXP_SLTSTA_PFD)
 504                pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 505                                           PCI_EXP_SLTSTA_PFD);
 506        ctrl->power_fault_detected = 0;
 507
 508        pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
 509        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 510                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 511                 PCI_EXP_SLTCTL_PWR_ON);
 512
 513        retval = pciehp_link_enable(ctrl);
 514        if (retval)
 515                ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
 516
 517        return retval;
 518}
 519
 520void pciehp_power_off_slot(struct slot *slot)
 521{
 522        struct controller *ctrl = slot->ctrl;
 523
 524        pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
 525        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 526                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 527                 PCI_EXP_SLTCTL_PWR_OFF);
 528}
 529
 530static irqreturn_t pcie_isr(int irq, void *dev_id)
 531{
 532        struct controller *ctrl = (struct controller *)dev_id;
 533        struct pci_dev *pdev = ctrl_dev(ctrl);
 534        struct pci_bus *subordinate = pdev->subordinate;
 535        struct pci_dev *dev;
 536        struct slot *slot = ctrl->slot;
 537        u16 detected, intr_loc;
 538        u8 open, present;
 539        bool link;
 540
 541        /*
 542         * In order to guarantee that all interrupt events are
 543         * serviced, we need to re-inspect Slot Status register after
 544         * clearing what is presumed to be the last pending interrupt.
 545         */
 546        intr_loc = 0;
 547        do {
 548                pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
 549
 550                detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 551                             PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 552                             PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
 553                detected &= ~intr_loc;
 554                intr_loc |= detected;
 555                if (!intr_loc)
 556                        return IRQ_NONE;
 557                if (detected)
 558                        pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 559                                                   intr_loc);
 560        } while (detected);
 561
 562        ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", intr_loc);
 563
 564        /* Check Command Complete Interrupt Pending */
 565        if (intr_loc & PCI_EXP_SLTSTA_CC) {
 566                ctrl->cmd_busy = 0;
 567                smp_mb();
 568                wake_up(&ctrl->queue);
 569        }
 570
 571        if (subordinate) {
 572                list_for_each_entry(dev, &subordinate->devices, bus_list) {
 573                        if (dev->ignore_hotplug) {
 574                                ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
 575                                         intr_loc, pci_name(dev));
 576                                return IRQ_HANDLED;
 577                        }
 578                }
 579        }
 580
 581        if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
 582                return IRQ_HANDLED;
 583
 584        /* Check MRL Sensor Changed */
 585        if (intr_loc & PCI_EXP_SLTSTA_MRLSC) {
 586                pciehp_get_latch_status(slot, &open);
 587                ctrl_info(ctrl, "Latch %s on Slot(%s)\n",
 588                          open ? "open" : "close", slot_name(slot));
 589                pciehp_queue_interrupt_event(slot, open ? INT_SWITCH_OPEN :
 590                                             INT_SWITCH_CLOSE);
 591        }
 592
 593        /* Check Attention Button Pressed */
 594        if (intr_loc & PCI_EXP_SLTSTA_ABP) {
 595                ctrl_info(ctrl, "Button pressed on Slot(%s)\n",
 596                          slot_name(slot));
 597                pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
 598        }
 599
 600        /* Check Presence Detect Changed */
 601        if (intr_loc & PCI_EXP_SLTSTA_PDC) {
 602                pciehp_get_adapter_status(slot, &present);
 603                ctrl_info(ctrl, "Card %spresent on Slot(%s)\n",
 604                          present ? "" : "not ", slot_name(slot));
 605                pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
 606                                             INT_PRESENCE_OFF);
 607        }
 608
 609        /* Check Power Fault Detected */
 610        if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 611                ctrl->power_fault_detected = 1;
 612                ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(slot));
 613                pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
 614        }
 615
 616        if (intr_loc & PCI_EXP_SLTSTA_DLLSC) {
 617                link = pciehp_check_link_active(ctrl);
 618                ctrl_info(ctrl, "slot(%s): Link %s event\n",
 619                          slot_name(slot), link ? "Up" : "Down");
 620                pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
 621                                             INT_LINK_DOWN);
 622        }
 623
 624        return IRQ_HANDLED;
 625}
 626
 627void pcie_enable_notification(struct controller *ctrl)
 628{
 629        u16 cmd, mask;
 630
 631        /*
 632         * TBD: Power fault detected software notification support.
 633         *
 634         * Power fault detected software notification is not enabled
 635         * now, because it caused power fault detected interrupt storm
 636         * on some machines. On those machines, power fault detected
 637         * bit in the slot status register was set again immediately
 638         * when it is cleared in the interrupt service routine, and
 639         * next power fault detected interrupt was notified again.
 640         */
 641
 642        /*
 643         * Always enable link events: thus link-up and link-down shall
 644         * always be treated as hotplug and unplug respectively. Enable
 645         * presence detect only if Attention Button is not present.
 646         */
 647        cmd = PCI_EXP_SLTCTL_DLLSCE;
 648        if (ATTN_BUTTN(ctrl))
 649                cmd |= PCI_EXP_SLTCTL_ABPE;
 650        else
 651                cmd |= PCI_EXP_SLTCTL_PDCE;
 652        if (MRL_SENS(ctrl))
 653                cmd |= PCI_EXP_SLTCTL_MRLSCE;
 654        if (!pciehp_poll_mode)
 655                cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 656
 657        mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 658                PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 659                PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 660                PCI_EXP_SLTCTL_DLLSCE);
 661
 662        pcie_write_cmd_nowait(ctrl, cmd, mask);
 663        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 664                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
 665}
 666
 667static void pcie_disable_notification(struct controller *ctrl)
 668{
 669        u16 mask;
 670
 671        mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 672                PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 673                PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 674                PCI_EXP_SLTCTL_DLLSCE);
 675        pcie_write_cmd(ctrl, 0, mask);
 676        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 677                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 678}
 679
 680/*
 681 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
 682 * bus reset of the bridge, but at the same time we want to ensure that it is
 683 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
 684 * disable link state notification and presence detection change notification
 685 * momentarily, if we see that they could interfere. Also, clear any spurious
 686 * events after.
 687 */
 688int pciehp_reset_slot(struct slot *slot, int probe)
 689{
 690        struct controller *ctrl = slot->ctrl;
 691        struct pci_dev *pdev = ctrl_dev(ctrl);
 692        u16 stat_mask = 0, ctrl_mask = 0;
 693
 694        if (probe)
 695                return 0;
 696
 697        if (!ATTN_BUTTN(ctrl)) {
 698                ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
 699                stat_mask |= PCI_EXP_SLTSTA_PDC;
 700        }
 701        ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
 702        stat_mask |= PCI_EXP_SLTSTA_DLLSC;
 703
 704        pcie_write_cmd(ctrl, 0, ctrl_mask);
 705        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 706                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 707        if (pciehp_poll_mode)
 708                del_timer_sync(&ctrl->poll_timer);
 709
 710        pci_reset_bridge_secondary_bus(ctrl->pcie->port);
 711
 712        pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
 713        pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
 714        ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 715                 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
 716        if (pciehp_poll_mode)
 717                int_poll_timeout(ctrl->poll_timer.data);
 718
 719        return 0;
 720}
 721
 722int pcie_init_notification(struct controller *ctrl)
 723{
 724        if (pciehp_request_irq(ctrl))
 725                return -1;
 726        pcie_enable_notification(ctrl);
 727        ctrl->notification_enabled = 1;
 728        return 0;
 729}
 730
 731static void pcie_shutdown_notification(struct controller *ctrl)
 732{
 733        if (ctrl->notification_enabled) {
 734                pcie_disable_notification(ctrl);
 735                pciehp_free_irq(ctrl);
 736                ctrl->notification_enabled = 0;
 737        }
 738}
 739
 740static int pcie_init_slot(struct controller *ctrl)
 741{
 742        struct slot *slot;
 743
 744        slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 745        if (!slot)
 746                return -ENOMEM;
 747
 748        slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
 749        if (!slot->wq)
 750                goto abort;
 751
 752        slot->ctrl = ctrl;
 753        mutex_init(&slot->lock);
 754        mutex_init(&slot->hotplug_lock);
 755        INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 756        ctrl->slot = slot;
 757        return 0;
 758abort:
 759        kfree(slot);
 760        return -ENOMEM;
 761}
 762
 763static void pcie_cleanup_slot(struct controller *ctrl)
 764{
 765        struct slot *slot = ctrl->slot;
 766        cancel_delayed_work(&slot->work);
 767        destroy_workqueue(slot->wq);
 768        kfree(slot);
 769}
 770
 771static inline void dbg_ctrl(struct controller *ctrl)
 772{
 773        struct pci_dev *pdev = ctrl->pcie->port;
 774        u16 reg16;
 775
 776        if (!pciehp_debug)
 777                return;
 778
 779        ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 780        pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
 781        ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 782        pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
 783        ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 784}
 785
 786#define FLAG(x, y)      (((x) & (y)) ? '+' : '-')
 787
 788struct controller *pcie_init(struct pcie_device *dev)
 789{
 790        struct controller *ctrl;
 791        u32 slot_cap, link_cap;
 792        struct pci_dev *pdev = dev->port;
 793
 794        ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 795        if (!ctrl) {
 796                dev_err(&dev->device, "%s: Out of memory\n", __func__);
 797                goto abort;
 798        }
 799        ctrl->pcie = dev;
 800        pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 801        ctrl->slot_cap = slot_cap;
 802        mutex_init(&ctrl->ctrl_lock);
 803        init_waitqueue_head(&ctrl->queue);
 804        dbg_ctrl(ctrl);
 805
 806        /* Check if Data Link Layer Link Active Reporting is implemented */
 807        pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
 808        if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
 809                ctrl->link_active_reporting = 1;
 810
 811        /* Clear all remaining event bits in Slot Status register */
 812        pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 813                PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 814                PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 815                PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
 816
 817        ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
 818                (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
 819                FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
 820                FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
 821                FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
 822                FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
 823                FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
 824                FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
 825                FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
 826                FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
 827                FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
 828                FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
 829
 830        if (pcie_init_slot(ctrl))
 831                goto abort_ctrl;
 832
 833        return ctrl;
 834
 835abort_ctrl:
 836        kfree(ctrl);
 837abort:
 838        return NULL;
 839}
 840
 841void pciehp_release_ctrl(struct controller *ctrl)
 842{
 843        pcie_shutdown_notification(ctrl);
 844        pcie_cleanup_slot(ctrl);
 845        kfree(ctrl);
 846}
 847