1
2
3
4
5
6
7
8
9
10
11#ifndef __SH_PFC_H
12#define __SH_PFC_H
13
14#include <linux/bug.h>
15#include <linux/stringify.h>
16
17enum {
18 PINMUX_TYPE_NONE,
19 PINMUX_TYPE_FUNCTION,
20 PINMUX_TYPE_GPIO,
21 PINMUX_TYPE_OUTPUT,
22 PINMUX_TYPE_INPUT,
23};
24
25#define SH_PFC_PIN_CFG_INPUT (1 << 0)
26#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
27#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
28#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
29#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
30
31struct sh_pfc_pin {
32 u16 pin;
33 u16 enum_id;
34 const char *name;
35 unsigned int configs;
36};
37
38#define SH_PFC_PIN_GROUP(n) \
39 { \
40 .name = #n, \
41 .pins = n##_pins, \
42 .mux = n##_mux, \
43 .nr_pins = ARRAY_SIZE(n##_pins), \
44 }
45
46struct sh_pfc_pin_group {
47 const char *name;
48 const unsigned int *pins;
49 const unsigned int *mux;
50 unsigned int nr_pins;
51};
52
53#define SH_PFC_FUNCTION(n) \
54 { \
55 .name = #n, \
56 .groups = n##_groups, \
57 .nr_groups = ARRAY_SIZE(n##_groups), \
58 }
59
60struct sh_pfc_function {
61 const char *name;
62 const char * const *groups;
63 unsigned int nr_groups;
64};
65
66struct pinmux_func {
67 u16 enum_id;
68 const char *name;
69};
70
71struct pinmux_cfg_reg {
72 u32 reg;
73 u8 reg_width, field_width;
74 const u16 *enum_ids;
75 const u8 *var_field_width;
76};
77
78#define PINMUX_CFG_REG(name, r, r_width, f_width) \
79 .reg = r, .reg_width = r_width, .field_width = f_width, \
80 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
81
82#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
83 .reg = r, .reg_width = r_width, \
84 .var_field_width = (const u8 [r_width]) \
85 { var_fw0, var_fwn, 0 }, \
86 .enum_ids = (const u16 [])
87
88struct pinmux_data_reg {
89 u32 reg;
90 u8 reg_width;
91 const u16 *enum_ids;
92};
93
94#define PINMUX_DATA_REG(name, r, r_width) \
95 .reg = r, .reg_width = r_width, \
96 .enum_ids = (const u16 [r_width]) \
97
98struct pinmux_irq {
99 int irq;
100 const short *gpios;
101};
102
103#ifdef CONFIG_ARCH_MULTIPLATFORM
104#define PINMUX_IRQ(irq_nr, ids...) \
105 { .gpios = (const short []) { ids, -1 } }
106#else
107#define PINMUX_IRQ(irq_nr, ids...) \
108 { .irq = irq_nr, .gpios = (const short []) { ids, -1 } }
109#endif
110
111struct pinmux_range {
112 u16 begin;
113 u16 end;
114 u16 force;
115};
116
117struct sh_pfc;
118
119struct sh_pfc_soc_operations {
120 int (*init)(struct sh_pfc *pfc);
121 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
122 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
123 unsigned int bias);
124};
125
126struct sh_pfc_soc_info {
127 const char *name;
128 const struct sh_pfc_soc_operations *ops;
129
130 struct pinmux_range input;
131 struct pinmux_range output;
132 struct pinmux_range function;
133
134 const struct sh_pfc_pin *pins;
135 unsigned int nr_pins;
136 const struct sh_pfc_pin_group *groups;
137 unsigned int nr_groups;
138 const struct sh_pfc_function *functions;
139 unsigned int nr_functions;
140
141 const struct pinmux_func *func_gpios;
142 unsigned int nr_func_gpios;
143
144 const struct pinmux_cfg_reg *cfg_regs;
145 const struct pinmux_data_reg *data_regs;
146
147 const u16 *gpio_data;
148 unsigned int gpio_data_size;
149
150 const struct pinmux_irq *gpio_irq;
151 unsigned int gpio_irq_size;
152
153 u32 unlock_reg;
154};
155
156
157
158
159
160
161
162
163
164#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
165
166#define PINMUX_IPSR_NOGP(ispr, fn) \
167 PINMUX_DATA(fn##_MARK, FN_##fn)
168#define PINMUX_IPSR_DATA(ipsr, fn) \
169 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
170#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
171 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
172#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
173 PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
174#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
175 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
176#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \
177 PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
178
179
180
181
182
183#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
184
185#define PORT_GP_32(bank, fn, sfx) \
186 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
187 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
188 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
189 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
190 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
191 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
192 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
193 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
194 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
195 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
196 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
197 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
198 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
199 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
200 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
201 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
202
203#define PORT_GP_32_REV(bank, fn, sfx) \
204 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
205 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
206 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
207 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
208 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
209 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
210 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
211 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
212 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
213 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
214 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
215 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
216 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
217 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
218 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
219 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
220
221
222#define _GP_ALL(bank, pin, name, sfx) name##_##sfx
223#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
224
225
226#define _GP_GPIO(bank, _pin, _name, sfx) \
227 { \
228 .pin = (bank * 32) + _pin, \
229 .name = __stringify(_name), \
230 .enum_id = _name##_DATA, \
231 }
232#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
233
234
235#define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN)
236#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
237
238
239
240
241
242#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
243
244#define PORT_10(pn, fn, pfx, sfx) \
245 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
246 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
247 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
248 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
249 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
250
251#define PORT_90(pn, fn, pfx, sfx) \
252 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
253 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
254 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
255 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
256 PORT_10(pn+90, fn, pfx##9, sfx)
257
258
259#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
260#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
261
262
263#define PINMUX_GPIO(_pin) \
264 [GPIO_##_pin] = { \
265 .pin = (u16)-1, \
266 .name = __stringify(GPIO_##_pin), \
267 .enum_id = _pin##_DATA, \
268 }
269
270
271#define SH_PFC_PIN_CFG(_pin, cfgs) \
272 { \
273 .pin = _pin, \
274 .name = __stringify(PORT##_pin), \
275 .enum_id = PORT##_pin##_DATA, \
276 .configs = cfgs, \
277 }
278
279
280#define SH_PFC_PIN_NAMED(row, col, _name) \
281 { \
282 .pin = PIN_NUMBER(row, col), \
283 .name = __stringify(PIN_##_name), \
284 .configs = SH_PFC_PIN_CFG_NO_GPIO, \
285 }
286
287
288
289
290#define _PORT_DATA(pn, pfx, sfx) \
291 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
292 PORT##pfx##_OUT, PORT##pfx##_IN)
293#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
294
295
296#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
297 [gpio - (base)] = { \
298 .name = __stringify(gpio), \
299 .enum_id = data_or_mark, \
300 }
301#define GPIO_FN(str) \
302 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
303
304
305
306
307#define PORTCR(nr, reg) \
308 { \
309 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
310 \
311 0, 0, 0, 0, \
312 \
313 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
314 \
315 0, 0, \
316 \
317 PORT##nr##_FN0, PORT##nr##_FN1, \
318 PORT##nr##_FN2, PORT##nr##_FN3, \
319 PORT##nr##_FN4, PORT##nr##_FN5, \
320 PORT##nr##_FN6, PORT##nr##_FN7 \
321 } \
322 }
323
324#endif
325
