1/* 2 * EMXX FCD (Function Controller Driver) for USB. 3 * 4 * Copyright (C) 2010 Renesas Electronics Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 8 * as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA. 18 */ 19 20 21 22 23#ifndef _LINUX_EMXX_H 24#define _LINUX_EMXX_H 25 26 27 28/*---------------------------------------------------------------------------*/ 29/*----------------- Default undef */ 30#if 0 31#define DEBUG 32#define UDC_DEBUG_DUMP 33#endif 34 35/*----------------- Default define */ 36#define USE_DMA 1 37#define USE_SUSPEND_WAIT 1 38 39 40 41#ifndef TRUE 42#define TRUE 1 43#define FALSE 0 44#endif 45 46 47/*------------ Board dependence(Resource) */ 48#define VBUS_VALUE GPIO_VBUS 49 50/* below hacked up for staging integration */ 51#define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */ 52#define INT_VBUS 0 /* IRQ for GPIO_P153 */ 53 54/*------------ Board dependence(Wait) */ 55 56/* CHATTERING wait time ms */ 57#define VBUS_CHATTERING_MDELAY 1 58/* DMA Abort wait time ms */ 59#define DMA_DISABLE_TIME 10 60 61 62 63/*------------ Controller dependence */ 64#define NUM_ENDPOINTS 14 /* Endpoint */ 65#define REG_EP_NUM 15 /* Endpoint Register */ 66#define DMA_MAX_COUNT 256 /* DMA Block */ 67 68 69 70#define EPC_RST_DISABLE_TIME 1 /* 1 usec */ 71#define EPC_DIRPD_DISABLE_TIME 1 /* 1 msec */ 72#define EPC_PLL_LOCK_COUNT 1000 /* 1000 */ 73#define IN_DATA_EMPTY_COUNT 1000 /* 1000 */ 74 75#define CHATGER_TIME 700 /* 700msec */ 76#define USB_SUSPEND_TIME 2000 /* 2 sec */ 77 78 79/* U2F FLAG */ 80#define U2F_ENABLE 1 81#define U2F_DISABLE 0 82 83 84/*------- BIT */ 85#define BIT00 0x00000001 86#define BIT01 0x00000002 87#define BIT02 0x00000004 88#define BIT03 0x00000008 89#define BIT04 0x00000010 90#define BIT05 0x00000020 91#define BIT06 0x00000040 92#define BIT07 0x00000080 93#define BIT08 0x00000100 94#define BIT09 0x00000200 95#define BIT10 0x00000400 96#define BIT11 0x00000800 97#define BIT12 0x00001000 98#define BIT13 0x00002000 99#define BIT14 0x00004000 100#define BIT15 0x00008000 101#define BIT16 0x00010000 102#define BIT17 0x00020000 103#define BIT18 0x00040000 104#define BIT19 0x00080000 105#define BIT20 0x00100000 106#define BIT21 0x00200000 107#define BIT22 0x00400000 108#define BIT23 0x00800000 109#define BIT24 0x01000000 110#define BIT25 0x02000000 111#define BIT26 0x04000000 112#define BIT27 0x08000000 113#define BIT28 0x10000000 114#define BIT29 0x20000000 115#define BIT30 0x40000000 116#define BIT31 0x80000000 117 118#define TEST_FORCE_ENABLE (BIT18+BIT16) 119 120#define INT_SEL BIT10 121#define CONSTFS BIT09 122#define SOF_RCV BIT08 123#define RSUM_IN BIT07 124#define SUSPEND BIT06 125#define CONF BIT05 126#define DEFAULT BIT04 127#define CONNECTB BIT03 128#define PUE2 BIT02 129 130#define MAX_TEST_MODE_NUM 0x05 131#define TEST_MODE_SHIFT 16 132 133/*------- (0x0004) USB Status Register */ 134#define SPEED_MODE BIT06 135#define HIGH_SPEED BIT06 136 137#define CONF BIT05 138#define DEFAULT BIT04 139#define USB_RST BIT03 140#define SPND_OUT BIT02 141#define RSUM_OUT BIT01 142 143/*------- (0x0008) USB Address Register */ 144#define USB_ADDR 0x007F0000 145#define SOF_STATUS BIT15 146#define UFRAME (BIT14+BIT13+BIT12) 147#define FRAME 0x000007FF 148 149#define USB_ADRS_SHIFT 16 150 151/*------- (0x000C) UTMI Characteristic 1 Register */ 152#define SQUSET (BIT07+BIT06+BIT05+BIT04) 153 154#define USB_SQUSET (BIT06+BIT05+BIT04) 155 156/*------- (0x0010) TEST Control Register */ 157#define FORCEHS BIT02 158#define CS_TESTMODEEN BIT01 159#define LOOPBACK BIT00 160 161/*------- (0x0018) Setup Data 0 Register */ 162/*------- (0x001C) Setup Data 1 Register */ 163 164/*------- (0x0020) USB Interrupt Status Register */ 165#define EPn_INT 0x00FFFF00 166#define EP15_INT BIT23 167#define EP14_INT BIT22 168#define EP13_INT BIT21 169#define EP12_INT BIT20 170#define EP11_INT BIT19 171#define EP10_INT BIT18 172#define EP9_INT BIT17 173#define EP8_INT BIT16 174#define EP7_INT BIT15 175#define EP6_INT BIT14 176#define EP5_INT BIT13 177#define EP4_INT BIT12 178#define EP3_INT BIT11 179#define EP2_INT BIT10 180#define EP1_INT BIT09 181#define EP0_INT BIT08 182#define SPEED_MODE_INT BIT06 183#define SOF_ERROR_INT BIT05 184#define SOF_INT BIT04 185#define USB_RST_INT BIT03 186#define SPND_INT BIT02 187#define RSUM_INT BIT01 188 189#define USB_INT_STA_RW 0x7E 190 191/*------- (0x0024) USB Interrupt Enable Register */ 192#define EP15_0_EN 0x00FFFF00 193#define EP15_EN BIT23 194#define EP14_EN BIT22 195#define EP13_EN BIT21 196#define EP12_EN BIT20 197#define EP11_EN BIT19 198#define EP10_EN BIT18 199#define EP9_EN BIT17 200#define EP8_EN BIT16 201#define EP7_EN BIT15 202#define EP6_EN BIT14 203#define EP5_EN BIT13 204#define EP4_EN BIT12 205#define EP3_EN BIT11 206#define EP2_EN BIT10 207#define EP1_EN BIT09 208#define EP0_EN BIT08 209#define SPEED_MODE_EN BIT06 210#define SOF_ERROR_EN BIT05 211#define SOF_EN BIT04 212#define USB_RST_EN BIT03 213#define SPND_EN BIT02 214#define RSUM_EN BIT01 215 216#define USB_INT_EN_BIT \ 217 (EP0_EN|SPEED_MODE_EN|USB_RST_EN|SPND_EN|RSUM_EN) 218 219/*------- (0x0028) EP0 Control Register */ 220#define EP0_STGSEL BIT18 221#define EP0_OVERSEL BIT17 222#define EP0_AUTO BIT16 223#define EP0_PIDCLR BIT09 224#define EP0_BCLR BIT08 225#define EP0_DEND BIT07 226#define EP0_DW (BIT06+BIT05) 227#define EP0_DW4 0 228#define EP0_DW3 (BIT06+BIT05) 229#define EP0_DW2 BIT06 230#define EP0_DW1 BIT05 231 232#define EP0_INAK_EN BIT04 233#define EP0_PERR_NAK_CLR BIT03 234#define EP0_STL BIT02 235#define EP0_INAK BIT01 236#define EP0_ONAK BIT00 237 238/*------- (0x002C) EP0 Status Register */ 239#define EP0_PID BIT18 240#define EP0_PERR_NAK BIT17 241#define EP0_PERR_NAK_INT BIT16 242#define EP0_OUT_NAK_INT BIT15 243#define EP0_OUT_NULL BIT14 244#define EP0_OUT_FULL BIT13 245#define EP0_OUT_EMPTY BIT12 246#define EP0_IN_NAK_INT BIT11 247#define EP0_IN_DATA BIT10 248#define EP0_IN_FULL BIT09 249#define EP0_IN_EMPTY BIT08 250#define EP0_OUT_NULL_INT BIT07 251#define EP0_OUT_OR_INT BIT06 252#define EP0_OUT_INT BIT05 253#define EP0_IN_INT BIT04 254#define EP0_STALL_INT BIT03 255#define STG_END_INT BIT02 256#define STG_START_INT BIT01 257#define SETUP_INT BIT00 258 259#define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF) 260 261/*------- (0x0030) EP0 Interrupt Enable Register */ 262#define EP0_PERR_NAK_EN BIT16 263#define EP0_OUT_NAK_EN BIT15 264 265#define EP0_IN_NAK_EN BIT11 266 267#define EP0_OUT_NULL_EN BIT07 268#define EP0_OUT_OR_EN BIT06 269#define EP0_OUT_EN BIT05 270#define EP0_IN_EN BIT04 271#define EP0_STALL_EN BIT03 272#define STG_END_EN BIT02 273#define STG_START_EN BIT01 274#define SETUP_EN BIT00 275 276#define EP0_INT_EN_BIT \ 277 (EP0_OUT_OR_EN|EP0_OUT_EN|EP0_IN_EN|STG_END_EN|SETUP_EN) 278 279/*------- (0x0034) EP0 Length Register */ 280#define EP0_LDATA 0x0000007F 281 282/*------- (0x0038) EP0 Read Register */ 283/*------- (0x003C) EP0 Write Register */ 284 285/*------- (0x0040:) EPn Control Register */ 286#define EPn_EN BIT31 287#define EPn_BUF_TYPE BIT30 288#define EPn_BUF_SINGLE BIT30 289 290#define EPn_DIR0 BIT26 291#define EPn_MODE (BIT25+BIT24) 292#define EPn_BULK 0 293#define EPn_INTERRUPT BIT24 294#define EPn_ISO BIT25 295 296#define EPn_OVERSEL BIT17 297#define EPn_AUTO BIT16 298 299#define EPn_IPIDCLR BIT11 300#define EPn_OPIDCLR BIT10 301#define EPn_BCLR BIT09 302#define EPn_CBCLR BIT08 303#define EPn_DEND BIT07 304#define EPn_DW (BIT06+BIT05) 305#define EPn_DW4 0 306#define EPn_DW3 (BIT06+BIT05) 307#define EPn_DW2 BIT06 308#define EPn_DW1 BIT05 309 310#define EPn_OSTL_EN BIT04 311#define EPn_ISTL BIT03 312#define EPn_OSTL BIT02 313 314#define EPn_ONAK BIT00 315 316/*------- (0x0044:) EPn Status Register */ 317#define EPn_ISO_PIDERR BIT29 /* R */ 318#define EPn_OPID BIT28 /* R */ 319#define EPn_OUT_NOTKN BIT27 /* R */ 320#define EPn_ISO_OR BIT26 /* R */ 321 322#define EPn_ISO_CRC BIT24 /* R */ 323#define EPn_OUT_END_INT BIT23 /* RW */ 324#define EPn_OUT_OR_INT BIT22 /* RW */ 325#define EPn_OUT_NAK_ERR_INT BIT21 /* RW */ 326#define EPn_OUT_STALL_INT BIT20 /* RW */ 327#define EPn_OUT_INT BIT19 /* RW */ 328#define EPn_OUT_NULL_INT BIT18 /* RW */ 329#define EPn_OUT_FULL BIT17 /* R */ 330#define EPn_OUT_EMPTY BIT16 /* R */ 331 332#define EPn_IPID BIT10 /* R */ 333#define EPn_IN_NOTKN BIT09 /* R */ 334#define EPn_ISO_UR BIT08 /* R */ 335#define EPn_IN_END_INT BIT07 /* RW */ 336 337#define EPn_IN_NAK_ERR_INT BIT05 /* RW */ 338#define EPn_IN_STALL_INT BIT04 /* RW */ 339#define EPn_IN_INT BIT03 /* RW */ 340#define EPn_IN_DATA BIT02 /* R */ 341#define EPn_IN_FULL BIT01 /* R */ 342#define EPn_IN_EMPTY BIT00 /* R */ 343 344#define EPn_INT_EN \ 345 (EPn_OUT_END_INT|EPn_OUT_INT|EPn_IN_END_INT|EPn_IN_INT) 346 347/*------- (0x0048:) EPn Interrupt Enable Register */ 348#define EPn_OUT_END_EN BIT23 /* RW */ 349#define EPn_OUT_OR_EN BIT22 /* RW */ 350#define EPn_OUT_NAK_ERR_EN BIT21 /* RW */ 351#define EPn_OUT_STALL_EN BIT20 /* RW */ 352#define EPn_OUT_EN BIT19 /* RW */ 353#define EPn_OUT_NULL_EN BIT18 /* RW */ 354 355#define EPn_IN_END_EN BIT07 /* RW */ 356 357#define EPn_IN_NAK_ERR_EN BIT05 /* RW */ 358#define EPn_IN_STALL_EN BIT04 /* RW */ 359#define EPn_IN_EN BIT03 /* RW */ 360 361/*------- (0x004C:) EPn Interrupt Enable Register */ 362#define EPn_STOP_MODE BIT11 363#define EPn_DEND_SET BIT10 364#define EPn_BURST_SET BIT09 365#define EPn_STOP_SET BIT08 366 367#define EPn_DMA_EN BIT04 368 369#define EPn_DMAMODE0 BIT00 370 371/*------- (0x0050:) EPn MaxPacket & BaseAddress Register */ 372#define EPn_BASEAD 0x1FFF0000 373#define EPn_MPKT 0x000007FF 374 375/*------- (0x0054:) EPn Length & DMA Count Register */ 376#define EPn_DMACNT 0x01FF0000 377#define EPn_LDATA 0x000007FF 378 379/*------- (0x0058:) EPn Read Register */ 380/*------- (0x005C:) EPn Write Register */ 381 382/*------- (0x1000) AHBSCTR Register */ 383#define WAIT_MODE BIT00 384 385/*------- (0x1004) AHBMCTR Register */ 386#define ARBITER_CTR BIT31 /* RW */ 387#define MCYCLE_RST BIT12 /* RW */ 388 389#define ENDIAN_CTR (BIT09+BIT08) /* RW */ 390#define ENDIAN_BYTE_SWAP BIT09 391#define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR 392 393#define HBUSREQ_MODE BIT05 /* RW */ 394#define HTRANS_MODE BIT04 /* RW */ 395 396#define WBURST_TYPE BIT02 /* RW */ 397#define BURST_TYPE (BIT01+BIT00) /* RW */ 398#define BURST_MAX_16 0 399#define BURST_MAX_8 BIT00 400#define BURST_MAX_4 BIT01 401#define BURST_SINGLE BURST_TYPE 402 403/*------- (0x1008) AHBBINT Register */ 404#define DMA_ENDINT 0xFFFE0000 /* RW */ 405 406#define AHB_VBUS_INT BIT13 /* RW */ 407 408#define MBUS_ERRINT BIT06 /* RW */ 409 410#define SBUS_ERRINT0 BIT04 /* RW */ 411#define ERR_MASTER 0x0000000F /* R */ 412 413/*------- (0x100C) AHBBINTEN Register */ 414#define DMA_ENDINTEN 0xFFFE0000 /* RW */ 415 416#define VBUS_INTEN BIT13 /* RW */ 417 418#define MBUS_ERRINTEN BIT06 /* RW */ 419 420#define SBUS_ERRINT0EN BIT04 /* RW */ 421 422/*------- (0x1010) EPCTR Register */ 423#define DIRPD BIT12 /* RW */ 424 425#define VBUS_LEVEL BIT08 /* R */ 426 427#define PLL_RESUME BIT05 /* RW */ 428#define PLL_LOCK BIT04 /* R */ 429 430#define EPC_RST BIT00 /* RW */ 431 432/*------- (0x1014) USBF_EPTEST Register */ 433#define LINESTATE (BIT09+BIT08) /* R */ 434#define DM_LEVEL BIT09 /* R */ 435#define DP_LEVEL BIT08 /* R */ 436 437#define PHY_TST BIT01 /* RW */ 438#define PHY_TSTCLK BIT00 /* RW */ 439 440/*------- (0x1020) USBSSVER Register */ 441#define AHBB_VER 0x00FF0000 /* R */ 442#define EPC_VER 0x0000FF00 /* R */ 443#define SS_VER 0x000000FF /* R */ 444 445/*------- (0x1024) USBSSCONF Register */ 446#define EP_AVAILABLE 0xFFFF0000 /* R */ 447#define DMA_AVAILABLE 0x0000FFFF /* R */ 448 449/*------- (0x1110:) EPnDCR1 Register */ 450#define DCR1_EPn_DMACNT 0x00FF0000 /* RW */ 451 452#define DCR1_EPn_DIR0 BIT01 /* RW */ 453#define DCR1_EPn_REQEN BIT00 /* RW */ 454 455/*------- (0x1114:) EPnDCR2 Register */ 456#define DCR2_EPn_LMPKT 0x07FF0000 /* RW */ 457 458#define DCR2_EPn_MPKT 0x000007FF /* RW */ 459 460/*------- (0x1118:) EPnTADR Register */ 461#define EPn_TADR 0xFFFFFFFF /* RW */ 462 463 464 465/*===========================================================================*/ 466/* Struct */ 467/*------- ep_regs */ 468struct ep_regs { 469 u32 EP_CONTROL; /* EP Control */ 470 u32 EP_STATUS; /* EP Status */ 471 u32 EP_INT_ENA; /* EP Interrupt Enable */ 472 u32 EP_DMA_CTRL; /* EP DMA Control */ 473 u32 EP_PCKT_ADRS; /* EP Maxpacket & BaseAddress */ 474 u32 EP_LEN_DCNT; /* EP Length & DMA count */ 475 u32 EP_READ; /* EP Read */ 476 u32 EP_WRITE; /* EP Write */ 477}; 478 479/*------- ep_dcr */ 480struct ep_dcr { 481 u32 EP_DCR1; /* EP_DCR1 */ 482 u32 EP_DCR2; /* EP_DCR2 */ 483 u32 EP_TADR; /* EP_TADR */ 484 u32 Reserved; /* Reserved */ 485}; 486 487/*------- Function Registers */ 488struct fc_regs { 489 u32 USB_CONTROL; /* (0x0000) USB Control */ 490 u32 USB_STATUS; /* (0x0004) USB Status */ 491 u32 USB_ADDRESS; /* (0x0008) USB Address */ 492 u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */ 493 u32 TEST_CONTROL; /* (0x0010) TEST Control */ 494 u32 Reserved_14; /* (0x0014) Reserved */ 495 u32 SETUP_DATA0; /* (0x0018) Setup Data0 */ 496 u32 SETUP_DATA1; /* (0x001C) Setup Data1 */ 497 u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */ 498 u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */ 499 u32 EP0_CONTROL; /* (0x0028) EP0 Control */ 500 u32 EP0_STATUS; /* (0x002C) EP0 Status */ 501 u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */ 502 u32 EP0_LENGTH; /* (0x0034) EP0 Length */ 503 u32 EP0_READ; /* (0x0038) EP0 Read */ 504 u32 EP0_WRITE; /* (0x003C) EP0 Write */ 505 506 struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */ 507 508 u8 Reserved220[0x1000-0x220]; /* (0x0220:0x0FFF) Reserved */ 509 510 u32 AHBSCTR; /* (0x1000) AHBSCTR */ 511 u32 AHBMCTR; /* (0x1004) AHBMCTR */ 512 u32 AHBBINT; /* (0x1008) AHBBINT */ 513 u32 AHBBINTEN; /* (0x100C) AHBBINTEN */ 514 u32 EPCTR; /* (0x1010) EPCTR */ 515 u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */ 516 517 u8 Reserved1018[0x20-0x18]; /* (0x1018:0x101F) Reserved */ 518 519 u32 USBSSVER; /* (0x1020) USBSSVER */ 520 u32 USBSSCONF; /* (0x1024) USBSSCONF */ 521 522 u8 Reserved1028[0x110-0x28]; /* (0x1028:0x110F) Reserved */ 523 524 struct ep_dcr EP_DCR[REG_EP_NUM]; /* */ 525 526 u8 Reserved1200[0x1000-0x200]; /* Reserved */ 527} __aligned(32); 528 529 530 531 532 533 534 535 536#define EP0_PACKETSIZE 64 537#define EP_PACKETSIZE 1024 538 539/* EPn RAM SIZE */ 540#define D_RAM_SIZE_CTRL 64 541 542/* EPn Bulk Endpoint Max Packet Size */ 543#define D_FS_RAM_SIZE_BULK 64 544#define D_HS_RAM_SIZE_BULK 512 545 546 547struct nbu2ss_udc; 548 549 550enum ep0_state { 551 EP0_IDLE, 552 EP0_IN_DATA_PHASE, 553 EP0_OUT_DATA_PHASE, 554 EP0_IN_STATUS_PHASE, 555 EP0_OUT_STATUS_PAHSE, 556 EP0_END_XFER, 557 EP0_SUSPEND, 558 EP0_STALL, 559}; 560 561struct nbu2ss_req { 562 struct usb_request req; 563 struct list_head queue; 564 565 u32 div_len; 566 bool dma_flag; 567 bool zero; 568 569 bool unaligned; 570 571 unsigned mapped:1; 572}; 573 574struct nbu2ss_ep { 575 struct usb_ep ep; 576 struct list_head queue; 577 578 struct nbu2ss_udc *udc; 579 580 const struct usb_endpoint_descriptor *desc; 581 582 u8 epnum; 583 u8 direct; 584 u8 ep_type; 585 586 unsigned wedged:1; 587 unsigned halted:1; 588 unsigned stalled:1; 589 590 u8 *virt_buf; 591 dma_addr_t phys_buf; 592}; 593 594 595struct nbu2ss_udc { 596 struct usb_gadget gadget; 597 struct usb_gadget_driver *driver; 598 struct platform_device *pdev; 599 struct device *dev; 600 spinlock_t lock; 601 struct completion *pdone; 602 603 enum ep0_state ep0state; 604 enum usb_device_state devstate; 605 struct usb_ctrlrequest ctrl; 606 struct nbu2ss_req ep0_req; 607 u8 ep0_buf[EP0_PACKETSIZE]; 608 609 struct nbu2ss_ep ep[NUM_ENDPOINTS]; 610 611 unsigned softconnect:1; 612 unsigned vbus_active:1; 613 unsigned linux_suspended:1; 614 unsigned linux_resume:1; 615 unsigned usb_suspended:1; 616 unsigned remote_wakeup:1; 617 unsigned udc_enabled:1; 618 619 unsigned mA; 620 621 u32 curr_config; /* Current Configuration Number */ 622 623 struct fc_regs *p_regs; 624}; 625 626/* USB register access structure */ 627union usb_reg_access { 628 struct { 629 unsigned char DATA[4]; 630 } byte; 631 unsigned int dw; 632}; 633 634/*-------------------------------------------------------------------------*/ 635 636#endif /* _LINUX_EMXX_H */ 637