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23#include <linux/blkdev.h>
24#include <linux/kthread.h>
25#include <linux/sched.h>
26#include <linux/workqueue.h>
27#include <linux/vmalloc.h>
28
29#include "rtsx.h"
30#include "sd.h"
31#include "xd.h"
32#include "ms.h"
33
34static void rtsx_calibration(struct rtsx_chip *chip)
35{
36 rtsx_write_phy_register(chip, 0x1B, 0x135E);
37 wait_timeout(10);
38 rtsx_write_phy_register(chip, 0x00, 0x0280);
39 rtsx_write_phy_register(chip, 0x01, 0x7112);
40 rtsx_write_phy_register(chip, 0x01, 0x7110);
41 rtsx_write_phy_register(chip, 0x01, 0x7112);
42 rtsx_write_phy_register(chip, 0x01, 0x7113);
43 rtsx_write_phy_register(chip, 0x00, 0x0288);
44}
45
46void rtsx_disable_card_int(struct rtsx_chip *chip)
47{
48 u32 reg = rtsx_readl(chip, RTSX_BIER);
49
50 reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN);
51 rtsx_writel(chip, RTSX_BIER, reg);
52}
53
54void rtsx_enable_card_int(struct rtsx_chip *chip)
55{
56 u32 reg = rtsx_readl(chip, RTSX_BIER);
57 int i;
58
59 for (i = 0; i <= chip->max_lun; i++) {
60 if (chip->lun2card[i] & XD_CARD)
61 reg |= XD_INT_EN;
62 if (chip->lun2card[i] & SD_CARD)
63 reg |= SD_INT_EN;
64 if (chip->lun2card[i] & MS_CARD)
65 reg |= MS_INT_EN;
66 }
67 if (chip->hw_bypass_sd)
68 reg &= ~((u32)SD_INT_EN);
69
70 rtsx_writel(chip, RTSX_BIER, reg);
71}
72
73void rtsx_enable_bus_int(struct rtsx_chip *chip)
74{
75 u32 reg = 0;
76#ifndef DISABLE_CARD_INT
77 int i;
78#endif
79
80 reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
81
82#ifndef DISABLE_CARD_INT
83 for (i = 0; i <= chip->max_lun; i++) {
84 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
85 i, chip->lun2card[i]);
86
87 if (chip->lun2card[i] & XD_CARD)
88 reg |= XD_INT_EN;
89 if (chip->lun2card[i] & SD_CARD)
90 reg |= SD_INT_EN;
91 if (chip->lun2card[i] & MS_CARD)
92 reg |= MS_INT_EN;
93 }
94 if (chip->hw_bypass_sd)
95 reg &= ~((u32)SD_INT_EN);
96#endif
97
98 if (chip->ic_version >= IC_VER_C)
99 reg |= DELINK_INT_EN;
100#ifdef SUPPORT_OCP
101 reg |= OC_INT_EN;
102#endif
103 if (!chip->adma_mode)
104 reg |= DATA_DONE_INT_EN;
105
106
107 rtsx_writel(chip, RTSX_BIER, reg);
108
109 dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
110}
111
112void rtsx_disable_bus_int(struct rtsx_chip *chip)
113{
114 rtsx_writel(chip, RTSX_BIER, 0);
115}
116
117static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
118{
119 int retval;
120
121 if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
122 if (chip->asic_code) {
123 retval = rtsx_write_register(chip, CARD_PULL_CTL5,
124 0xFF,
125 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
126 if (retval) {
127 rtsx_trace(chip);
128 return retval;
129 }
130 } else {
131 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
132 0xFF,
133 FPGA_SD_PULL_CTL_EN);
134 if (retval) {
135 rtsx_trace(chip);
136 return retval;
137 }
138 }
139 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF,
140 CARD_SHARE_48_SD);
141 if (retval) {
142 rtsx_trace(chip);
143 return retval;
144 }
145
146
147 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01);
148 if (retval) {
149 rtsx_trace(chip);
150 return retval;
151 }
152
153 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF,
154 SDIO_BUS_CTRL | SDIO_CD_CTRL);
155 if (retval) {
156 rtsx_trace(chip);
157 return retval;
158 }
159
160 chip->sd_int = 1;
161 chip->sd_io = 1;
162 } else {
163 chip->need_reset |= SD_CARD;
164 }
165
166 return STATUS_SUCCESS;
167}
168
169#ifdef HW_AUTO_SWITCH_SD_BUS
170static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
171{
172 u8 tmp;
173 bool sw_bypass_sd = false;
174 int retval;
175
176 if (chip->driver_first_load) {
177 if (CHECK_PID(chip, 0x5288)) {
178 retval = rtsx_read_register(chip, 0xFE5A, &tmp);
179 if (retval) {
180 rtsx_trace(chip);
181 return retval;
182 }
183 if (tmp & 0x08)
184 sw_bypass_sd = true;
185 } else if (CHECK_PID(chip, 0x5208)) {
186 retval = rtsx_read_register(chip, 0xFE70, &tmp);
187 if (retval) {
188 rtsx_trace(chip);
189 return retval;
190 }
191 if (tmp & 0x80)
192 sw_bypass_sd = true;
193 }
194 } else {
195 if (chip->sdio_in_charge)
196 sw_bypass_sd = true;
197 }
198 dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
199 chip->sdio_in_charge);
200 dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
201 chip->driver_first_load);
202 dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
203 sw_bypass_sd);
204
205 if (sw_bypass_sd) {
206 u8 cd_toggle_mask = 0;
207
208 retval = rtsx_read_register(chip, TLPTISTAT, &tmp);
209 if (retval) {
210 rtsx_trace(chip);
211 return retval;
212 }
213 cd_toggle_mask = 0x08;
214
215 if (tmp & cd_toggle_mask) {
216
217 if (CHECK_PID(chip, 0x5288)) {
218 retval = rtsx_write_register(chip, 0xFE5A,
219 0x08, 0x00);
220 if (retval) {
221 rtsx_trace(chip);
222 return retval;
223 }
224 } else if (CHECK_PID(chip, 0x5208)) {
225 retval = rtsx_write_register(chip, 0xFE70,
226 0x80, 0x00);
227 if (retval) {
228 rtsx_trace(chip);
229 return retval;
230 }
231 }
232
233 retval = rtsx_write_register(chip, TLPTISTAT, 0xFF,
234 tmp);
235 if (retval) {
236 rtsx_trace(chip);
237 return retval;
238 }
239
240 chip->need_reset |= SD_CARD;
241 } else {
242 dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
243
244 if (chip->asic_code) {
245 retval = sd_pull_ctl_enable(chip);
246 if (retval != STATUS_SUCCESS) {
247 rtsx_trace(chip);
248 return STATUS_FAIL;
249 }
250 } else {
251 retval = rtsx_write_register(chip,
252 FPGA_PULL_CTL,
253 FPGA_SD_PULL_CTL_BIT | 0x20,
254 0);
255 if (retval) {
256 rtsx_trace(chip);
257 return retval;
258 }
259 }
260 retval = card_share_mode(chip, SD_CARD);
261 if (retval != STATUS_SUCCESS) {
262 rtsx_trace(chip);
263 return STATUS_FAIL;
264 }
265
266
267 if (CHECK_PID(chip, 0x5288)) {
268 retval = rtsx_write_register(chip, 0xFE5A,
269 0x08, 0x08);
270 if (retval) {
271 rtsx_trace(chip);
272 return retval;
273 }
274 } else if (CHECK_PID(chip, 0x5208)) {
275 retval = rtsx_write_register(chip, 0xFE70,
276 0x80, 0x80);
277 if (retval) {
278 rtsx_trace(chip);
279 return retval;
280 }
281 }
282
283 chip->chip_insert_with_sdio = 1;
284 chip->sd_io = 1;
285 }
286 } else {
287 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
288 if (retval) {
289 rtsx_trace(chip);
290 return retval;
291 }
292
293 chip->need_reset |= SD_CARD;
294 }
295
296 return STATUS_SUCCESS;
297}
298#endif
299
300static int rtsx_reset_aspm(struct rtsx_chip *chip)
301{
302 int ret;
303
304 if (chip->dynamic_aspm) {
305 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
306 return STATUS_SUCCESS;
307
308 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
309 chip->aspm_l0s_l1_en);
310 if (ret != STATUS_SUCCESS) {
311 rtsx_trace(chip);
312 return STATUS_FAIL;
313 }
314
315 return STATUS_SUCCESS;
316 }
317
318 if (CHECK_PID(chip, 0x5208)) {
319 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
320 if (ret) {
321 rtsx_trace(chip);
322 return ret;
323 }
324 }
325 ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
326 if (ret != STATUS_SUCCESS) {
327 rtsx_trace(chip);
328 return STATUS_FAIL;
329 }
330
331 chip->aspm_level[0] = chip->aspm_l0s_l1_en;
332 if (CHK_SDIO_EXIST(chip)) {
333 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
334 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
335 0xC0, 0xFF, chip->aspm_l0s_l1_en);
336 if (ret != STATUS_SUCCESS) {
337 rtsx_trace(chip);
338 return STATUS_FAIL;
339 }
340 }
341
342 chip->aspm_enabled = 1;
343
344 return STATUS_SUCCESS;
345}
346
347static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
348{
349 int ret;
350
351 if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
352 rtsx_enable_bus_int(chip);
353 return STATUS_SUCCESS;
354 }
355
356 if (chip->phy_debug_mode) {
357 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
358 if (ret) {
359 rtsx_trace(chip);
360 return ret;
361 }
362 rtsx_disable_bus_int(chip);
363 } else {
364 rtsx_enable_bus_int(chip);
365 }
366
367 if (chip->ic_version >= IC_VER_D) {
368 u16 reg;
369
370 ret = rtsx_read_phy_register(chip, 0x00, ®);
371 if (ret != STATUS_SUCCESS) {
372 rtsx_trace(chip);
373 return STATUS_FAIL;
374 }
375
376 reg &= 0xFE7F;
377 reg |= 0x80;
378 ret = rtsx_write_phy_register(chip, 0x00, reg);
379 if (ret != STATUS_SUCCESS) {
380 rtsx_trace(chip);
381 return STATUS_FAIL;
382 }
383
384 ret = rtsx_read_phy_register(chip, 0x1C, ®);
385 if (ret != STATUS_SUCCESS) {
386 rtsx_trace(chip);
387 return STATUS_FAIL;
388 }
389
390 reg &= 0xFFF7;
391 ret = rtsx_write_phy_register(chip, 0x1C, reg);
392 if (ret != STATUS_SUCCESS) {
393 rtsx_trace(chip);
394 return STATUS_FAIL;
395 }
396 }
397
398 if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
399 rtsx_calibration(chip);
400
401 return STATUS_SUCCESS;
402}
403
404int rtsx_reset_chip(struct rtsx_chip *chip)
405{
406 int retval;
407
408 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
409
410 rtsx_disable_aspm(chip);
411
412 retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00);
413 if (retval) {
414 rtsx_trace(chip);
415 return retval;
416 }
417
418
419 retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0);
420 if (retval) {
421 rtsx_trace(chip);
422 return retval;
423 }
424
425#ifdef SUPPORT_OCP
426
427 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
428 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0);
429 if (retval) {
430 rtsx_trace(chip);
431 return retval;
432 }
433 } else {
434 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
435 MS_OC_POWER_DOWN);
436 if (retval) {
437 rtsx_trace(chip);
438 return retval;
439 }
440 }
441
442 retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK,
443 OCP_TIME_800);
444 if (retval) {
445 rtsx_trace(chip);
446 return retval;
447 }
448 retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK,
449 OCP_THD_244_946);
450 if (retval) {
451 rtsx_trace(chip);
452 return retval;
453 }
454 retval = rtsx_write_register(chip, OCPCTL, 0xFF,
455 CARD_OC_INT_EN | CARD_DETECT_EN);
456 if (retval) {
457 rtsx_trace(chip);
458 return retval;
459 }
460#else
461
462 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
463 OC_POWER_DOWN);
464 if (retval) {
465 rtsx_trace(chip);
466 return retval;
467 }
468#endif
469
470 if (!CHECK_PID(chip, 0x5288)) {
471 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03);
472 if (retval) {
473 rtsx_trace(chip);
474 return retval;
475 }
476 }
477
478
479 retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03);
480 if (retval) {
481 rtsx_trace(chip);
482 return retval;
483 }
484
485
486 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0);
487 if (retval) {
488 rtsx_trace(chip);
489 return retval;
490 }
491
492
493 retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF,
494 chip->card_drive_sel);
495 if (retval) {
496 rtsx_trace(chip);
497 return retval;
498 }
499
500#ifdef LED_AUTO_BLINK
501 retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF,
502 LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
503 if (retval) {
504 rtsx_trace(chip);
505 return retval;
506 }
507#endif
508
509 if (chip->asic_code) {
510
511 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF,
512 SSC_8X_EN | SSC_SEL_4M);
513 if (retval) {
514 rtsx_trace(chip);
515 return retval;
516 }
517 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12);
518 if (retval) {
519 rtsx_trace(chip);
520 return retval;
521 }
522 }
523
524
525
526
527
528
529
530
531 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10);
532 if (retval) {
533 rtsx_trace(chip);
534 return retval;
535 }
536
537
538 if (chip->aspm_l0s_l1_en) {
539 retval = rtsx_reset_aspm(chip);
540 if (retval != STATUS_SUCCESS) {
541 rtsx_trace(chip);
542 return STATUS_FAIL;
543 }
544 } else {
545 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
546 retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
547 if (retval != STATUS_SUCCESS) {
548 rtsx_trace(chip);
549 return STATUS_FAIL;
550 }
551 }
552 retval = rtsx_write_config_byte(chip, LCTLR,
553 chip->aspm_l0s_l1_en);
554 if (retval != STATUS_SUCCESS) {
555 rtsx_trace(chip);
556 return STATUS_FAIL;
557 }
558 }
559
560 retval = rtsx_write_config_byte(chip, 0x81, 1);
561 if (retval != STATUS_SUCCESS) {
562 rtsx_trace(chip);
563 return STATUS_FAIL;
564 }
565
566 if (CHK_SDIO_EXIST(chip)) {
567 retval = rtsx_write_cfg_dw(chip,
568 CHECK_PID(chip, 0x5288) ? 2 : 1,
569 0xC0, 0xFF00, 0x0100);
570
571 if (retval != STATUS_SUCCESS) {
572 rtsx_trace(chip);
573 return STATUS_FAIL;
574 }
575 }
576
577 if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
578 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
579 if (retval != STATUS_SUCCESS) {
580 rtsx_trace(chip);
581 return STATUS_FAIL;
582 }
583
584 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
585 if (retval != STATUS_SUCCESS) {
586 rtsx_trace(chip);
587 return STATUS_FAIL;
588 }
589 }
590
591 retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT,
592 LINK_RDY_INT);
593 if (retval) {
594 rtsx_trace(chip);
595 return retval;
596 }
597
598 retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
599 if (retval) {
600 rtsx_trace(chip);
601 return retval;
602 }
603
604 retval = rtsx_enable_pcie_intr(chip);
605 if (retval != STATUS_SUCCESS) {
606 rtsx_trace(chip);
607 return STATUS_FAIL;
608 }
609
610 chip->need_reset = 0;
611
612 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
613
614 if (chip->hw_bypass_sd)
615 goto nextcard;
616 dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
617 chip->int_reg);
618 if (chip->int_reg & SD_EXIST) {
619#ifdef HW_AUTO_SWITCH_SD_BUS
620 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
621 retval = rtsx_pre_handle_sdio_old(chip);
622 else
623 retval = rtsx_pre_handle_sdio_new(chip);
624
625 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (rtsx_reset_chip)\n",
626 (unsigned int)(chip->need_reset));
627#else
628 retval = rtsx_pre_handle_sdio_old(chip);
629#endif
630 if (retval != STATUS_SUCCESS) {
631 rtsx_trace(chip);
632 return STATUS_FAIL;
633 }
634
635 } else {
636 chip->sd_io = 0;
637 retval = rtsx_write_register(chip, SDIO_CTRL,
638 SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
639 if (retval) {
640 rtsx_trace(chip);
641 return retval;
642 }
643 }
644
645nextcard:
646 if (chip->int_reg & XD_EXIST)
647 chip->need_reset |= XD_CARD;
648 if (chip->int_reg & MS_EXIST)
649 chip->need_reset |= MS_CARD;
650 if (chip->int_reg & CARD_EXIST) {
651 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB,
652 SSC_RSTB);
653 if (retval) {
654 rtsx_trace(chip);
655 return retval;
656 }
657 }
658
659 dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
660 (unsigned int)(chip->need_reset));
661
662 retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00);
663 if (retval) {
664 rtsx_trace(chip);
665 return retval;
666 }
667
668 if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
669
670 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03,
671 0x03);
672 if (retval) {
673 rtsx_trace(chip);
674 return retval;
675 }
676 }
677
678 if (chip->remote_wakeup_en && !chip->auto_delink_en) {
679 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07);
680 if (retval) {
681 rtsx_trace(chip);
682 return retval;
683 }
684 if (chip->aux_pwr_exist) {
685 retval = rtsx_write_register(chip, PME_FORCE_CTL,
686 0xFF, 0x33);
687 if (retval) {
688 rtsx_trace(chip);
689 return retval;
690 }
691 }
692 } else {
693 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04);
694 if (retval) {
695 rtsx_trace(chip);
696 return retval;
697 }
698 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30);
699 if (retval) {
700 rtsx_trace(chip);
701 return retval;
702 }
703 }
704
705 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
706 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14);
707 if (retval) {
708 rtsx_trace(chip);
709 return retval;
710 }
711 }
712
713 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
714 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
715 if (retval != STATUS_SUCCESS) {
716 rtsx_trace(chip);
717 return STATUS_FAIL;
718 }
719 }
720
721 if (chip->ft2_fast_mode) {
722 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
723 MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
724 if (retval) {
725 rtsx_trace(chip);
726 return retval;
727 }
728 udelay(chip->pmos_pwr_on_interval);
729 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
730 MS_POWER_ON | SD_POWER_ON);
731 if (retval) {
732 rtsx_trace(chip);
733 return retval;
734 }
735
736 wait_timeout(200);
737 }
738
739
740 rtsx_reset_detected_cards(chip, 0);
741
742 chip->driver_first_load = 0;
743
744 return STATUS_SUCCESS;
745}
746
747static inline int check_sd_speed_prior(u32 sd_speed_prior)
748{
749 bool fake_para = false;
750 int i;
751
752 for (i = 0; i < 4; i++) {
753 u8 tmp = (u8)(sd_speed_prior >> (i*8));
754
755 if ((tmp < 0x01) || (tmp > 0x04)) {
756 fake_para = true;
757 break;
758 }
759 }
760
761 return !fake_para;
762}
763
764static inline int check_sd_current_prior(u32 sd_current_prior)
765{
766 bool fake_para = false;
767 int i;
768
769 for (i = 0; i < 4; i++) {
770 u8 tmp = (u8)(sd_current_prior >> (i*8));
771
772 if (tmp > 0x03) {
773 fake_para = true;
774 break;
775 }
776 }
777
778 return !fake_para;
779}
780
781static int rts5208_init(struct rtsx_chip *chip)
782{
783 int retval;
784 u16 reg = 0;
785 u8 val = 0;
786
787 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
788 if (retval) {
789 rtsx_trace(chip);
790 return retval;
791 }
792 retval = rtsx_read_register(chip, CLK_SEL, &val);
793 if (retval) {
794 rtsx_trace(chip);
795 return retval;
796 }
797 chip->asic_code = val == 0 ? 1 : 0;
798
799 if (chip->asic_code) {
800 retval = rtsx_read_phy_register(chip, 0x1C, ®);
801 if (retval != STATUS_SUCCESS) {
802 rtsx_trace(chip);
803 return STATUS_FAIL;
804 }
805
806 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
807 reg);
808 chip->ic_version = (reg >> 4) & 0x07;
809 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0;
810
811 } else {
812 retval = rtsx_read_register(chip, 0xFE80, &val);
813 if (retval) {
814 rtsx_trace(chip);
815 return retval;
816 }
817 chip->ic_version = val;
818 chip->phy_debug_mode = 0;
819 }
820
821 retval = rtsx_read_register(chip, PDINFO, &val);
822 if (retval) {
823 rtsx_trace(chip);
824 return retval;
825 }
826 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
827 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
828
829 retval = rtsx_read_register(chip, 0xFE50, &val);
830 if (retval) {
831 rtsx_trace(chip);
832 return retval;
833 }
834 chip->hw_bypass_sd = val & 0x01 ? 1 : 0;
835
836 rtsx_read_config_byte(chip, 0x0E, &val);
837 if (val & 0x80)
838 SET_SDIO_EXIST(chip);
839 else
840 CLR_SDIO_EXIST(chip);
841
842 if (chip->use_hw_setting) {
843 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
844 if (retval) {
845 rtsx_trace(chip);
846 return retval;
847 }
848 chip->auto_delink_en = val & 0x80 ? 1 : 0;
849 }
850
851 return STATUS_SUCCESS;
852}
853
854static int rts5288_init(struct rtsx_chip *chip)
855{
856 int retval;
857 u8 val = 0, max_func;
858 u32 lval = 0;
859
860 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
861 if (retval) {
862 rtsx_trace(chip);
863 return retval;
864 }
865 retval = rtsx_read_register(chip, CLK_SEL, &val);
866 if (retval) {
867 rtsx_trace(chip);
868 return retval;
869 }
870 chip->asic_code = val == 0 ? 1 : 0;
871
872 chip->ic_version = 0;
873 chip->phy_debug_mode = 0;
874
875 retval = rtsx_read_register(chip, PDINFO, &val);
876 if (retval) {
877 rtsx_trace(chip);
878 return retval;
879 }
880 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
881 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
882
883 retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val);
884 if (retval) {
885 rtsx_trace(chip);
886 return retval;
887 }
888 dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
889 chip->baro_pkg = val & 0x04 ? QFN : LQFP;
890
891 retval = rtsx_read_register(chip, 0xFE5A, &val);
892 if (retval) {
893 rtsx_trace(chip);
894 return retval;
895 }
896 chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
897
898 retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
899 if (retval != STATUS_SUCCESS) {
900 rtsx_trace(chip);
901 return STATUS_FAIL;
902 }
903
904 max_func = (u8)((lval >> 29) & 0x07);
905 dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
906 if (max_func == 0x02)
907 SET_SDIO_EXIST(chip);
908 else
909 CLR_SDIO_EXIST(chip);
910
911 if (chip->use_hw_setting) {
912 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
913 if (retval) {
914 rtsx_trace(chip);
915 return retval;
916 }
917 chip->auto_delink_en = val & 0x80 ? 1 : 0;
918
919 if (CHECK_BARO_PKG(chip, LQFP))
920 chip->lun_mode = SD_MS_1LUN;
921 else
922 chip->lun_mode = DEFAULT_SINGLE;
923 }
924
925 return STATUS_SUCCESS;
926}
927
928int rtsx_init_chip(struct rtsx_chip *chip)
929{
930 struct sd_info *sd_card = &chip->sd_card;
931 struct xd_info *xd_card = &chip->xd_card;
932 struct ms_info *ms_card = &chip->ms_card;
933 int retval;
934 unsigned int i;
935
936 dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
937 chip->vendor_id, chip->product_id);
938
939 chip->ic_version = 0;
940
941#ifdef _MSG_TRACE
942 chip->msg_idx = 0;
943#endif
944
945 memset(xd_card, 0, sizeof(struct xd_info));
946 memset(sd_card, 0, sizeof(struct sd_info));
947 memset(ms_card, 0, sizeof(struct ms_info));
948
949 chip->xd_reset_counter = 0;
950 chip->sd_reset_counter = 0;
951 chip->ms_reset_counter = 0;
952
953 chip->xd_show_cnt = MAX_SHOW_CNT;
954 chip->sd_show_cnt = MAX_SHOW_CNT;
955 chip->ms_show_cnt = MAX_SHOW_CNT;
956
957 chip->sd_io = 0;
958 chip->auto_delink_cnt = 0;
959 chip->auto_delink_allowed = 1;
960 rtsx_set_stat(chip, RTSX_STAT_INIT);
961
962 chip->aspm_enabled = 0;
963 chip->chip_insert_with_sdio = 0;
964 chip->sdio_aspm = 0;
965 chip->sdio_idle = 0;
966 chip->sdio_counter = 0;
967 chip->cur_card = 0;
968 chip->phy_debug_mode = 0;
969 chip->sdio_func_exist = 0;
970 memset(chip->sdio_raw_data, 0, 12);
971
972 for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
973 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
974 chip->rw_fail_cnt[i] = 0;
975 }
976
977 if (!check_sd_speed_prior(chip->sd_speed_prior))
978 chip->sd_speed_prior = 0x01040203;
979
980 dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
981 chip->sd_speed_prior);
982
983 if (!check_sd_current_prior(chip->sd_current_prior))
984 chip->sd_current_prior = 0x00010203;
985
986 dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
987 chip->sd_current_prior);
988
989 if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
990 chip->sd_ddr_tx_phase = 0;
991
992 if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
993 chip->mmc_ddr_tx_phase = 0;
994
995 retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0);
996 if (retval) {
997 rtsx_trace(chip);
998 return retval;
999 }
1000 wait_timeout(200);
1001 retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07);
1002 if (retval) {
1003 rtsx_trace(chip);
1004 return retval;
1005 }
1006 dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
1007 chip->use_hw_setting);
1008
1009 if (CHECK_PID(chip, 0x5208)) {
1010 retval = rts5208_init(chip);
1011 if (retval != STATUS_SUCCESS) {
1012 rtsx_trace(chip);
1013 return STATUS_FAIL;
1014 }
1015
1016 } else if (CHECK_PID(chip, 0x5288)) {
1017 retval = rts5288_init(chip);
1018 if (retval != STATUS_SUCCESS) {
1019 rtsx_trace(chip);
1020 return STATUS_FAIL;
1021 }
1022 }
1023
1024 if (chip->ss_en == 2)
1025 chip->ss_en = 0;
1026
1027 dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
1028 dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
1029 dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
1030 chip->phy_debug_mode);
1031 dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
1032 chip->aux_pwr_exist);
1033 dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
1034 chip->sdio_func_exist);
1035 dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
1036 chip->hw_bypass_sd);
1037 dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
1038 chip->aspm_l0s_l1_en);
1039 dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
1040 dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
1041 chip->auto_delink_en);
1042 dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
1043 dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
1044
1045 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1046 chip->card2lun[SD_CARD] = 0;
1047 chip->card2lun[MS_CARD] = 1;
1048 chip->card2lun[XD_CARD] = 0xFF;
1049 chip->lun2card[0] = SD_CARD;
1050 chip->lun2card[1] = MS_CARD;
1051 chip->max_lun = 1;
1052 SET_SDIO_IGNORED(chip);
1053 } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
1054 chip->card2lun[SD_CARD] = 0;
1055 chip->card2lun[MS_CARD] = 0;
1056 chip->card2lun[XD_CARD] = 0xFF;
1057 chip->lun2card[0] = SD_CARD | MS_CARD;
1058 chip->max_lun = 0;
1059 } else {
1060 chip->card2lun[XD_CARD] = 0;
1061 chip->card2lun[SD_CARD] = 0;
1062 chip->card2lun[MS_CARD] = 0;
1063 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
1064 chip->max_lun = 0;
1065 }
1066
1067 retval = rtsx_reset_chip(chip);
1068 if (retval != STATUS_SUCCESS) {
1069 rtsx_trace(chip);
1070 return STATUS_FAIL;
1071 }
1072
1073 return STATUS_SUCCESS;
1074}
1075
1076void rtsx_release_chip(struct rtsx_chip *chip)
1077{
1078 xd_free_l2p_tbl(chip);
1079 ms_free_l2p_tbl(chip);
1080 chip->card_exist = 0;
1081 chip->card_ready = 0;
1082}
1083
1084#if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1085static inline void rtsx_blink_led(struct rtsx_chip *chip)
1086{
1087 if (chip->card_exist && chip->blink_led) {
1088 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
1089 chip->led_toggle_counter++;
1090 } else {
1091 chip->led_toggle_counter = 0;
1092 toggle_gpio(chip, LED_GPIO);
1093 }
1094 }
1095}
1096#endif
1097
1098static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1099{
1100 bool reg_changed, maybe_support_aspm;
1101 u32 tmp = 0;
1102 u8 reg0 = 0, reg1 = 0;
1103
1104 maybe_support_aspm = false;
1105 reg_changed = false;
1106 rtsx_read_config_byte(chip, LCTLR, ®0);
1107 if (chip->aspm_level[0] != reg0) {
1108 reg_changed = true;
1109 chip->aspm_level[0] = reg0;
1110 }
1111 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1112 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1113 reg1 = (u8)tmp;
1114 if (chip->aspm_level[1] != reg1) {
1115 reg_changed = true;
1116 chip->aspm_level[1] = reg1;
1117 }
1118
1119 if ((reg0 & 0x03) && (reg1 & 0x03))
1120 maybe_support_aspm = true;
1121
1122 } else {
1123 if (reg0 & 0x03)
1124 maybe_support_aspm = true;
1125 }
1126
1127 if (reg_changed) {
1128 if (maybe_support_aspm)
1129 chip->aspm_l0s_l1_en = 0x03;
1130
1131 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1132 chip->aspm_level[0], chip->aspm_level[1]);
1133
1134 if (chip->aspm_l0s_l1_en) {
1135 chip->aspm_enabled = 1;
1136 } else {
1137 chip->aspm_enabled = 0;
1138 chip->sdio_aspm = 0;
1139 }
1140 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1141 0x30 | chip->aspm_level[0] |
1142 (chip->aspm_level[1] << 2));
1143 }
1144}
1145
1146static void rtsx_manage_ocp(struct rtsx_chip *chip)
1147{
1148#ifdef SUPPORT_OCP
1149 if (!chip->ocp_int)
1150 return;
1151
1152 rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat);
1153
1154 if (chip->card_exist & SD_CARD)
1155 sd_power_off_card3v3(chip);
1156 else if (chip->card_exist & MS_CARD)
1157 ms_power_off_card3v3(chip);
1158 else if (chip->card_exist & XD_CARD)
1159 xd_power_off_card3v3(chip);
1160
1161 chip->ocp_int = 0;
1162#endif
1163}
1164
1165static void rtsx_manage_sd_lock(struct rtsx_chip *chip)
1166{
1167#ifdef SUPPORT_SD_LOCK
1168 struct sd_info *sd_card = &chip->sd_card;
1169 u8 val;
1170
1171 if (!sd_card->sd_erase_status)
1172 return;
1173
1174 if (chip->card_exist & SD_CARD) {
1175 rtsx_read_register(chip, 0xFD30, &val);
1176 if (val & 0x02) {
1177 sd_card->sd_erase_status = SD_NOT_ERASE;
1178 sd_card->sd_lock_notify = 1;
1179 chip->need_reinit |= SD_CARD;
1180 }
1181 } else {
1182 sd_card->sd_erase_status = SD_NOT_ERASE;
1183 }
1184#endif
1185}
1186
1187static bool rtsx_is_ss_allowed(struct rtsx_chip *chip)
1188{
1189 u32 val;
1190
1191 if (!chip->ss_en || CHECK_PID(chip, 0x5288))
1192 return false;
1193
1194 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1195 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1196 if (val & 0x07)
1197 return false;
1198 }
1199
1200 return true;
1201}
1202
1203static void rtsx_manage_ss(struct rtsx_chip *chip)
1204{
1205 if (!rtsx_is_ss_allowed(chip) || chip->sd_io)
1206 return;
1207
1208 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1209 chip->ss_counter = 0;
1210 return;
1211 }
1212
1213 if (chip->ss_counter < (chip->ss_idle_period / POLLING_INTERVAL))
1214 chip->ss_counter++;
1215 else
1216 rtsx_exclusive_enter_ss(chip);
1217}
1218
1219static void rtsx_manage_aspm(struct rtsx_chip *chip)
1220{
1221 u8 data;
1222
1223 if (!CHECK_PID(chip, 0x5208))
1224 return;
1225
1226 rtsx_monitor_aspm_config(chip);
1227
1228#ifdef SUPPORT_SDIO_ASPM
1229 if (!CHK_SDIO_EXIST(chip) || CHK_SDIO_IGNORED(chip) ||
1230 !chip->aspm_l0s_l1_en || !chip->dynamic_aspm)
1231 return;
1232
1233 if (chip->sd_io) {
1234 dynamic_configure_sdio_aspm(chip);
1235 return;
1236 }
1237
1238 if (chip->sdio_aspm)
1239 return;
1240
1241 dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
1242 data = 0x30 | (chip->aspm_level[1] << 2);
1243 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data);
1244 chip->sdio_aspm = 1;
1245#endif
1246}
1247
1248static void rtsx_manage_idle(struct rtsx_chip *chip)
1249{
1250 if (chip->idle_counter < IDLE_MAX_COUNT) {
1251 chip->idle_counter++;
1252 return;
1253 }
1254
1255 if (rtsx_get_stat(chip) == RTSX_STAT_IDLE)
1256 return;
1257
1258 dev_dbg(rtsx_dev(chip), "Idle state!\n");
1259 rtsx_set_stat(chip, RTSX_STAT_IDLE);
1260
1261#if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1262 chip->led_toggle_counter = 0;
1263#endif
1264 rtsx_force_power_on(chip, SSC_PDCTL);
1265
1266 turn_off_led(chip, LED_GPIO);
1267
1268 if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
1269 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1270}
1271
1272static void rtsx_manage_2lun_mode(struct rtsx_chip *chip)
1273{
1274#ifdef SUPPORT_OCP
1275 u8 sd_oc, ms_oc;
1276
1277 sd_oc = chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER);
1278 ms_oc = chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER);
1279
1280 if (sd_oc || ms_oc)
1281 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1282 chip->ocp_stat);
1283
1284 if (sd_oc && (chip->card_exist & SD_CARD)) {
1285 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1286 card_power_off(chip, SD_CARD);
1287 chip->card_fail |= SD_CARD;
1288 }
1289
1290 if (ms_oc && (chip->card_exist & MS_CARD)) {
1291 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1292 card_power_off(chip, MS_CARD);
1293 chip->card_fail |= MS_CARD;
1294 }
1295#endif
1296}
1297
1298static void rtsx_manage_1lun_mode(struct rtsx_chip *chip)
1299{
1300#ifdef SUPPORT_OCP
1301 if (!(chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)))
1302 return;
1303
1304 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1305 chip->ocp_stat);
1306
1307 if (chip->card_exist & SD_CARD) {
1308 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1309 chip->card_fail |= SD_CARD;
1310 } else if (chip->card_exist & MS_CARD) {
1311 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1312 chip->card_fail |= MS_CARD;
1313 } else if (chip->card_exist & XD_CARD) {
1314 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1315 chip->card_fail |= XD_CARD;
1316 }
1317 card_power_off(chip, SD_CARD);
1318#endif
1319}
1320
1321static void rtsx_delink_stage1(struct rtsx_chip *chip, int enter_L1,
1322 int stage3_cnt)
1323{
1324 u8 val;
1325
1326 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1327
1328 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1329 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1330
1331 if (chip->card_exist)
1332 dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1333 else
1334 dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1335
1336 if (enter_L1)
1337 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1338
1339 if (chip->card_exist)
1340 val = 0x02;
1341 else
1342 val = 0x0A;
1343
1344 rtsx_write_register(chip, CHANGE_LINK_STATE, val, val);
1345
1346 if (enter_L1)
1347 rtsx_enter_L1(chip);
1348
1349 if (chip->card_exist)
1350 chip->auto_delink_cnt = stage3_cnt + 1;
1351}
1352
1353static void rtsx_delink_stage(struct rtsx_chip *chip)
1354{
1355 int delink_stage1_cnt, delink_stage2_cnt, delink_stage3_cnt;
1356 int enter_L1;
1357
1358 if (!chip->auto_delink_en || !chip->auto_delink_allowed ||
1359 chip->card_ready || chip->card_ejected || chip->sd_io) {
1360 chip->auto_delink_cnt = 0;
1361 return;
1362 }
1363
1364 enter_L1 = chip->auto_delink_in_L1 &&
1365 (chip->aspm_l0s_l1_en || chip->ss_en);
1366
1367 delink_stage1_cnt = chip->delink_stage1_step;
1368 delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1369 delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1370
1371 if (chip->auto_delink_cnt > delink_stage3_cnt)
1372 return;
1373
1374 if (chip->auto_delink_cnt == delink_stage1_cnt)
1375 rtsx_delink_stage1(chip, enter_L1, delink_stage3_cnt);
1376
1377 if (chip->auto_delink_cnt == delink_stage2_cnt) {
1378 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1379
1380 if (enter_L1)
1381 rtsx_exit_L1(chip);
1382
1383 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1384 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1385
1386 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1387 }
1388
1389 chip->auto_delink_cnt++;
1390}
1391
1392void rtsx_polling_func(struct rtsx_chip *chip)
1393{
1394 if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1395 return;
1396
1397 if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1398 goto delink_stage;
1399
1400 if (chip->polling_config) {
1401 u8 val;
1402
1403 rtsx_read_config_byte(chip, 0, &val);
1404 }
1405
1406 if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1407 return;
1408
1409 rtsx_manage_ocp(chip);
1410
1411 rtsx_manage_sd_lock(chip);
1412
1413 rtsx_init_cards(chip);
1414
1415 rtsx_manage_ss(chip);
1416
1417 rtsx_manage_aspm(chip);
1418
1419 rtsx_manage_idle(chip);
1420
1421 switch (rtsx_get_stat(chip)) {
1422 case RTSX_STAT_RUN:
1423#if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1424 rtsx_blink_led(chip);
1425#endif
1426 do_remaining_work(chip);
1427 break;
1428
1429 case RTSX_STAT_IDLE:
1430 if (chip->sd_io && !chip->sd_int)
1431 try_to_switch_sdio_ctrl(chip);
1432
1433 rtsx_enable_aspm(chip);
1434 break;
1435
1436 default:
1437 break;
1438 }
1439
1440 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1441 rtsx_manage_2lun_mode(chip);
1442 else
1443 rtsx_manage_1lun_mode(chip);
1444
1445delink_stage:
1446 rtsx_delink_stage(chip);
1447}
1448
1449void rtsx_undo_delink(struct rtsx_chip *chip)
1450{
1451 chip->auto_delink_allowed = 0;
1452 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00);
1453}
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1464{
1465 int i;
1466
1467 for (i = 0; i <= 8; i++) {
1468 int addr = RTSX_HCBAR + i * 4;
1469 u32 reg;
1470
1471 reg = rtsx_readl(chip, addr);
1472 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1473 }
1474 rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1475 rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1476
1477 for (i = 0; i < 16; i++) {
1478 u16 addr = 0xFE20 + (u16)i;
1479 u8 val;
1480
1481 rtsx_read_register(chip, addr, &val);
1482 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1483 }
1484
1485 rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1486 rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1487}
1488
1489#define MAX_RW_REG_CNT 1024
1490
1491int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1492{
1493 int i;
1494 u32 val = 3 << 30;
1495
1496 val |= (u32)(addr & 0x3FFF) << 16;
1497 val |= (u32)mask << 8;
1498 val |= (u32)data;
1499
1500 rtsx_writel(chip, RTSX_HAIMR, val);
1501
1502 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1503 val = rtsx_readl(chip, RTSX_HAIMR);
1504 if ((val & (1 << 31)) == 0) {
1505 if (data != (u8)val) {
1506 rtsx_trace(chip);
1507 return STATUS_FAIL;
1508 }
1509
1510 return STATUS_SUCCESS;
1511 }
1512 }
1513
1514 rtsx_trace(chip);
1515 return STATUS_TIMEDOUT;
1516}
1517
1518int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1519{
1520 u32 val = 2 << 30;
1521 int i;
1522
1523 if (data)
1524 *data = 0;
1525
1526 val |= (u32)(addr & 0x3FFF) << 16;
1527
1528 rtsx_writel(chip, RTSX_HAIMR, val);
1529
1530 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1531 val = rtsx_readl(chip, RTSX_HAIMR);
1532 if ((val & (1 << 31)) == 0)
1533 break;
1534 }
1535
1536 if (i >= MAX_RW_REG_CNT) {
1537 rtsx_trace(chip);
1538 return STATUS_TIMEDOUT;
1539 }
1540
1541 if (data)
1542 *data = (u8)(val & 0xFF);
1543
1544 return STATUS_SUCCESS;
1545}
1546
1547int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1548 u32 val)
1549{
1550 int retval;
1551 u8 mode = 0, tmp;
1552 int i;
1553
1554 for (i = 0; i < 4; i++) {
1555 if (mask & 0xFF) {
1556 retval = rtsx_write_register(chip, CFGDATA0 + i,
1557 0xFF,
1558 (u8)(val & mask & 0xFF));
1559 if (retval) {
1560 rtsx_trace(chip);
1561 return retval;
1562 }
1563 mode |= (1 << i);
1564 }
1565 mask >>= 8;
1566 val >>= 8;
1567 }
1568
1569 if (mode) {
1570 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1571 if (retval) {
1572 rtsx_trace(chip);
1573 return retval;
1574 }
1575 retval = rtsx_write_register(chip, CFGADDR1, 0xFF,
1576 (u8)(addr >> 8));
1577 if (retval) {
1578 rtsx_trace(chip);
1579 return retval;
1580 }
1581
1582 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1583 0x80 | mode | ((func_no & 0x03) << 4));
1584 if (retval) {
1585 rtsx_trace(chip);
1586 return retval;
1587 }
1588
1589 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1590 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1591 if (retval) {
1592 rtsx_trace(chip);
1593 return retval;
1594 }
1595 if ((tmp & 0x80) == 0)
1596 break;
1597 }
1598 }
1599
1600 return STATUS_SUCCESS;
1601}
1602
1603int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1604{
1605 int retval;
1606 int i;
1607 u8 tmp;
1608 u32 data = 0;
1609
1610 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1611 if (retval) {
1612 rtsx_trace(chip);
1613 return retval;
1614 }
1615 retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1616 if (retval) {
1617 rtsx_trace(chip);
1618 return retval;
1619 }
1620 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1621 0x80 | ((func_no & 0x03) << 4));
1622 if (retval) {
1623 rtsx_trace(chip);
1624 return retval;
1625 }
1626
1627 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1628 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1629 if (retval) {
1630 rtsx_trace(chip);
1631 return retval;
1632 }
1633 if ((tmp & 0x80) == 0)
1634 break;
1635 }
1636
1637 for (i = 0; i < 4; i++) {
1638 retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp);
1639 if (retval) {
1640 rtsx_trace(chip);
1641 return retval;
1642 }
1643 data |= (u32)tmp << (i * 8);
1644 }
1645
1646 if (val)
1647 *val = data;
1648
1649 return STATUS_SUCCESS;
1650}
1651
1652int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1653 int len)
1654{
1655 u32 *data, *mask;
1656 u16 offset = addr % 4;
1657 u16 aligned_addr = addr - offset;
1658 int dw_len, i, j;
1659 int retval;
1660
1661 if (!buf) {
1662 rtsx_trace(chip);
1663 return STATUS_NOMEM;
1664 }
1665
1666 if ((len + offset) % 4)
1667 dw_len = (len + offset) / 4 + 1;
1668 else
1669 dw_len = (len + offset) / 4;
1670
1671 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1672
1673 data = vzalloc(dw_len * 4);
1674 if (!data) {
1675 rtsx_trace(chip);
1676 return STATUS_NOMEM;
1677 }
1678
1679 mask = vzalloc(dw_len * 4);
1680 if (!mask) {
1681 vfree(data);
1682 rtsx_trace(chip);
1683 return STATUS_NOMEM;
1684 }
1685
1686 j = 0;
1687 for (i = 0; i < len; i++) {
1688 mask[j] |= 0xFF << (offset * 8);
1689 data[j] |= buf[i] << (offset * 8);
1690 if (++offset == 4) {
1691 j++;
1692 offset = 0;
1693 }
1694 }
1695
1696 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask,
1697 dw_len * 4);
1698 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data,
1699 dw_len * 4);
1700
1701 for (i = 0; i < dw_len; i++) {
1702 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1703 mask[i], data[i]);
1704 if (retval != STATUS_SUCCESS) {
1705 vfree(data);
1706 vfree(mask);
1707 rtsx_trace(chip);
1708 return STATUS_FAIL;
1709 }
1710 }
1711
1712 vfree(data);
1713 vfree(mask);
1714
1715 return STATUS_SUCCESS;
1716}
1717
1718int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1719 int len)
1720{
1721 u32 *data;
1722 u16 offset = addr % 4;
1723 u16 aligned_addr = addr - offset;
1724 int dw_len, i, j;
1725 int retval;
1726
1727 if ((len + offset) % 4)
1728 dw_len = (len + offset) / 4 + 1;
1729 else
1730 dw_len = (len + offset) / 4;
1731
1732 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1733
1734 data = vmalloc(dw_len * 4);
1735 if (!data) {
1736 rtsx_trace(chip);
1737 return STATUS_NOMEM;
1738 }
1739
1740 for (i = 0; i < dw_len; i++) {
1741 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1742 data + i);
1743 if (retval != STATUS_SUCCESS) {
1744 vfree(data);
1745 rtsx_trace(chip);
1746 return STATUS_FAIL;
1747 }
1748 }
1749
1750 if (buf) {
1751 j = 0;
1752
1753 for (i = 0; i < len; i++) {
1754 buf[i] = (u8)(data[j] >> (offset * 8));
1755 if (++offset == 4) {
1756 j++;
1757 offset = 0;
1758 }
1759 }
1760 }
1761
1762 vfree(data);
1763
1764 return STATUS_SUCCESS;
1765}
1766
1767int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1768{
1769 int retval;
1770 bool finished = false;
1771 int i;
1772 u8 tmp;
1773
1774 retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val);
1775 if (retval) {
1776 rtsx_trace(chip);
1777 return retval;
1778 }
1779 retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1780 if (retval) {
1781 rtsx_trace(chip);
1782 return retval;
1783 }
1784 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1785 if (retval) {
1786 rtsx_trace(chip);
1787 return retval;
1788 }
1789 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81);
1790 if (retval) {
1791 rtsx_trace(chip);
1792 return retval;
1793 }
1794
1795 for (i = 0; i < 100000; i++) {
1796 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1797 if (retval) {
1798 rtsx_trace(chip);
1799 return retval;
1800 }
1801 if (!(tmp & 0x80)) {
1802 finished = true;
1803 break;
1804 }
1805 }
1806
1807 if (!finished) {
1808 rtsx_trace(chip);
1809 return STATUS_FAIL;
1810 }
1811
1812 return STATUS_SUCCESS;
1813}
1814
1815int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1816{
1817 int retval;
1818 bool finished = false;
1819 int i;
1820 u16 data = 0;
1821 u8 tmp;
1822
1823 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1824 if (retval) {
1825 rtsx_trace(chip);
1826 return retval;
1827 }
1828 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80);
1829 if (retval) {
1830 rtsx_trace(chip);
1831 return retval;
1832 }
1833
1834 for (i = 0; i < 100000; i++) {
1835 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1836 if (retval) {
1837 rtsx_trace(chip);
1838 return retval;
1839 }
1840 if (!(tmp & 0x80)) {
1841 finished = true;
1842 break;
1843 }
1844 }
1845
1846 if (!finished) {
1847 rtsx_trace(chip);
1848 return STATUS_FAIL;
1849 }
1850
1851 retval = rtsx_read_register(chip, PHYDATA0, &tmp);
1852 if (retval) {
1853 rtsx_trace(chip);
1854 return retval;
1855 }
1856 data = tmp;
1857 retval = rtsx_read_register(chip, PHYDATA1, &tmp);
1858 if (retval) {
1859 rtsx_trace(chip);
1860 return retval;
1861 }
1862 data |= (u16)tmp << 8;
1863
1864 if (val)
1865 *val = data;
1866
1867 return STATUS_SUCCESS;
1868}
1869
1870int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1871{
1872 int retval;
1873 int i;
1874 u8 data = 0;
1875
1876 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr);
1877 if (retval) {
1878 rtsx_trace(chip);
1879 return retval;
1880 }
1881
1882 for (i = 0; i < 100; i++) {
1883 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1884 if (retval) {
1885 rtsx_trace(chip);
1886 return retval;
1887 }
1888 if (!(data & 0x80))
1889 break;
1890 udelay(1);
1891 }
1892
1893 if (data & 0x80) {
1894 rtsx_trace(chip);
1895 return STATUS_TIMEDOUT;
1896 }
1897
1898 retval = rtsx_read_register(chip, EFUSE_DATA, &data);
1899 if (retval) {
1900 rtsx_trace(chip);
1901 return retval;
1902 }
1903 if (val)
1904 *val = data;
1905
1906 return STATUS_SUCCESS;
1907}
1908
1909int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1910{
1911 int retval;
1912 int i, j;
1913 u8 data = 0, tmp = 0xFF;
1914
1915 for (i = 0; i < 8; i++) {
1916 if (val & (u8)(1 << i))
1917 continue;
1918
1919 tmp &= (~(u8)(1 << i));
1920 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1921
1922 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp);
1923 if (retval) {
1924 rtsx_trace(chip);
1925 return retval;
1926 }
1927 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF,
1928 0xA0 | addr);
1929 if (retval) {
1930 rtsx_trace(chip);
1931 return retval;
1932 }
1933
1934 for (j = 0; j < 100; j++) {
1935 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1936 if (retval) {
1937 rtsx_trace(chip);
1938 return retval;
1939 }
1940 if (!(data & 0x80))
1941 break;
1942 wait_timeout(3);
1943 }
1944
1945 if (data & 0x80) {
1946 rtsx_trace(chip);
1947 return STATUS_TIMEDOUT;
1948 }
1949
1950 wait_timeout(5);
1951 }
1952
1953 return STATUS_SUCCESS;
1954}
1955
1956int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1957{
1958 int retval;
1959 u16 value;
1960
1961 retval = rtsx_read_phy_register(chip, reg, &value);
1962 if (retval != STATUS_SUCCESS) {
1963 rtsx_trace(chip);
1964 return STATUS_FAIL;
1965 }
1966
1967 if (value & (1 << bit)) {
1968 value &= ~(1 << bit);
1969 retval = rtsx_write_phy_register(chip, reg, value);
1970 if (retval != STATUS_SUCCESS) {
1971 rtsx_trace(chip);
1972 return STATUS_FAIL;
1973 }
1974 }
1975
1976 return STATUS_SUCCESS;
1977}
1978
1979int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1980{
1981 int retval;
1982 u16 value;
1983
1984 retval = rtsx_read_phy_register(chip, reg, &value);
1985 if (retval != STATUS_SUCCESS) {
1986 rtsx_trace(chip);
1987 return STATUS_FAIL;
1988 }
1989
1990 if ((value & (1 << bit)) == 0) {
1991 value |= (1 << bit);
1992 retval = rtsx_write_phy_register(chip, reg, value);
1993 if (retval != STATUS_SUCCESS) {
1994 rtsx_trace(chip);
1995 return STATUS_FAIL;
1996 }
1997 }
1998
1999 return STATUS_SUCCESS;
2000}
2001
2002int rtsx_check_link_ready(struct rtsx_chip *chip)
2003{
2004 int retval;
2005 u8 val;
2006
2007 retval = rtsx_read_register(chip, IRQSTAT0, &val);
2008 if (retval) {
2009 rtsx_trace(chip);
2010 return retval;
2011 }
2012
2013 dev_dbg(rtsx_dev(chip), "IRQSTAT0: 0x%x\n", val);
2014 if (val & LINK_RDY_INT) {
2015 dev_dbg(rtsx_dev(chip), "Delinked!\n");
2016 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
2017 return STATUS_FAIL;
2018 }
2019
2020 return STATUS_SUCCESS;
2021}
2022
2023static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
2024{
2025 u32 ultmp;
2026
2027 dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
2028 chip->product_id, dstate);
2029
2030 if (CHK_SDIO_EXIST(chip)) {
2031 u8 func_no;
2032
2033 if (CHECK_PID(chip, 0x5288))
2034 func_no = 2;
2035 else
2036 func_no = 1;
2037
2038 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
2039 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
2040 (int)func_no, ultmp);
2041 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
2042 }
2043
2044 rtsx_write_config_byte(chip, 0x44, dstate);
2045 rtsx_write_config_byte(chip, 0x45, 0);
2046}
2047
2048void rtsx_enter_L1(struct rtsx_chip *chip)
2049{
2050 rtsx_handle_pm_dstate(chip, 2);
2051}
2052
2053void rtsx_exit_L1(struct rtsx_chip *chip)
2054{
2055 rtsx_write_config_byte(chip, 0x44, 0);
2056 rtsx_write_config_byte(chip, 0x45, 0);
2057}
2058
2059void rtsx_enter_ss(struct rtsx_chip *chip)
2060{
2061 dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
2062
2063 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
2064
2065 if (chip->power_down_in_ss) {
2066 rtsx_power_off_card(chip);
2067 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2068 }
2069
2070 if (CHK_SDIO_EXIST(chip))
2071 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2072 0xC0, 0xFF00, 0x0100);
2073
2074 if (chip->auto_delink_en) {
2075 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
2076 } else {
2077 if (!chip->phy_debug_mode) {
2078 u32 tmp;
2079
2080 tmp = rtsx_readl(chip, RTSX_BIER);
2081 tmp |= CARD_INT;
2082 rtsx_writel(chip, RTSX_BIER, tmp);
2083 }
2084
2085 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
2086 }
2087
2088 rtsx_enter_L1(chip);
2089
2090 RTSX_CLR_DELINK(chip);
2091 rtsx_set_stat(chip, RTSX_STAT_SS);
2092}
2093
2094void rtsx_exit_ss(struct rtsx_chip *chip)
2095{
2096 dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
2097
2098 rtsx_exit_L1(chip);
2099
2100 if (chip->power_down_in_ss) {
2101 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
2102 udelay(1000);
2103 }
2104
2105 if (RTSX_TST_DELINK(chip)) {
2106 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2107 rtsx_reinit_cards(chip, 1);
2108 RTSX_CLR_DELINK(chip);
2109 } else if (chip->power_down_in_ss) {
2110 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2111 rtsx_reinit_cards(chip, 0);
2112 }
2113}
2114
2115int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
2116{
2117 u32 status, int_enable;
2118 bool exit_ss = false;
2119#ifdef SUPPORT_OCP
2120 u32 ocp_int = 0;
2121
2122 ocp_int = OC_INT;
2123#endif
2124
2125 if (chip->ss_en) {
2126 chip->ss_counter = 0;
2127 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
2128 exit_ss = true;
2129 rtsx_exit_L1(chip);
2130 rtsx_set_stat(chip, RTSX_STAT_RUN);
2131 }
2132 }
2133
2134 int_enable = rtsx_readl(chip, RTSX_BIER);
2135 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
2136
2137 if (((chip->int_reg & int_enable) == 0) ||
2138 (chip->int_reg == 0xFFFFFFFF))
2139 return STATUS_FAIL;
2140
2141 status = chip->int_reg &= (int_enable | 0x7FFFFF);
2142
2143 if (status & CARD_INT) {
2144 chip->auto_delink_cnt = 0;
2145
2146 if (status & SD_INT) {
2147 if (status & SD_EXIST) {
2148 set_bit(SD_NR, &chip->need_reset);
2149 } else {
2150 set_bit(SD_NR, &chip->need_release);
2151 chip->sd_reset_counter = 0;
2152 chip->sd_show_cnt = 0;
2153 clear_bit(SD_NR, &chip->need_reset);
2154 }
2155 } else {
2156
2157
2158
2159
2160
2161
2162 if (exit_ss && (status & SD_EXIST))
2163 set_bit(SD_NR, &chip->need_reinit);
2164 }
2165 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
2166 if (status & XD_INT) {
2167 if (status & XD_EXIST) {
2168 set_bit(XD_NR, &chip->need_reset);
2169 } else {
2170 set_bit(XD_NR, &chip->need_release);
2171 chip->xd_reset_counter = 0;
2172 chip->xd_show_cnt = 0;
2173 clear_bit(XD_NR, &chip->need_reset);
2174 }
2175 } else {
2176 if (exit_ss && (status & XD_EXIST))
2177 set_bit(XD_NR, &chip->need_reinit);
2178 }
2179 }
2180 if (status & MS_INT) {
2181 if (status & MS_EXIST) {
2182 set_bit(MS_NR, &chip->need_reset);
2183 } else {
2184 set_bit(MS_NR, &chip->need_release);
2185 chip->ms_reset_counter = 0;
2186 chip->ms_show_cnt = 0;
2187 clear_bit(MS_NR, &chip->need_reset);
2188 }
2189 } else {
2190 if (exit_ss && (status & MS_EXIST))
2191 set_bit(MS_NR, &chip->need_reinit);
2192 }
2193 }
2194
2195#ifdef SUPPORT_OCP
2196 chip->ocp_int = ocp_int & status;
2197#endif
2198
2199 if (chip->sd_io && (chip->int_reg & DATA_DONE_INT))
2200 chip->int_reg &= ~(u32)DATA_DONE_INT;
2201
2202 return STATUS_SUCCESS;
2203}
2204
2205void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2206{
2207 int retval;
2208
2209 dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
2210
2211 rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2212
2213 retval = rtsx_force_power_on(chip, SSC_PDCTL);
2214 if (retval != STATUS_SUCCESS)
2215 return;
2216
2217 rtsx_release_cards(chip);
2218 rtsx_disable_bus_int(chip);
2219 turn_off_led(chip, LED_GPIO);
2220
2221#ifdef HW_AUTO_SWITCH_SD_BUS
2222 if (chip->sd_io) {
2223 chip->sdio_in_charge = 1;
2224 if (CHECK_PID(chip, 0x5208)) {
2225 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2226
2227 rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2228 } else if (CHECK_PID(chip, 0x5288)) {
2229 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2230
2231 rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2232 }
2233 }
2234#endif
2235
2236 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2237
2238 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2239 }
2240
2241 if (pm_stat == PM_S1) {
2242 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
2243 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2244 HOST_ENTER_S1);
2245 } else if (pm_stat == PM_S3) {
2246 if (chip->s3_pwr_off_delay > 0)
2247 wait_timeout(chip->s3_pwr_off_delay);
2248
2249 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
2250 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2251 HOST_ENTER_S3);
2252 }
2253
2254 if (chip->do_delink_before_power_down && chip->auto_delink_en)
2255 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2256
2257 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2258
2259 chip->cur_clk = 0;
2260 chip->cur_card = 0;
2261 chip->card_exist = 0;
2262}
2263
2264void rtsx_enable_aspm(struct rtsx_chip *chip)
2265{
2266 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) {
2267 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
2268 chip->aspm_enabled = 1;
2269
2270 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2271 rtsx_write_phy_register(chip, 0x07, 0);
2272 if (CHECK_PID(chip, 0x5208)) {
2273 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2274 0x30 | chip->aspm_level[0]);
2275 } else {
2276 rtsx_write_config_byte(chip, LCTLR,
2277 chip->aspm_l0s_l1_en);
2278 }
2279
2280 if (CHK_SDIO_EXIST(chip)) {
2281 u16 val = chip->aspm_l0s_l1_en | 0x0100;
2282
2283 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2284 0xC0, 0xFFF, val);
2285 }
2286 }
2287}
2288
2289void rtsx_disable_aspm(struct rtsx_chip *chip)
2290{
2291 if (CHECK_PID(chip, 0x5208))
2292 rtsx_monitor_aspm_config(chip);
2293
2294 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) {
2295 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
2296 chip->aspm_enabled = 0;
2297
2298 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2299 rtsx_write_phy_register(chip, 0x07, 0x0129);
2300 if (CHECK_PID(chip, 0x5208))
2301 rtsx_write_register(chip, ASPM_FORCE_CTL,
2302 0xF3, 0x30);
2303 else
2304 rtsx_write_config_byte(chip, LCTLR, 0x00);
2305
2306 wait_timeout(1);
2307 }
2308}
2309
2310int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2311{
2312 int retval;
2313 int i, j;
2314 u16 reg_addr;
2315 u8 *ptr;
2316
2317 if (!buf) {
2318 rtsx_trace(chip);
2319 return STATUS_ERROR;
2320 }
2321
2322 ptr = buf;
2323 reg_addr = PPBUF_BASE2;
2324 for (i = 0; i < buf_len/256; i++) {
2325 rtsx_init_cmd(chip);
2326
2327 for (j = 0; j < 256; j++)
2328 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2329
2330 retval = rtsx_send_cmd(chip, 0, 250);
2331 if (retval < 0) {
2332 rtsx_trace(chip);
2333 return STATUS_FAIL;
2334 }
2335
2336 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2337 ptr += 256;
2338 }
2339
2340 if (buf_len%256) {
2341 rtsx_init_cmd(chip);
2342
2343 for (j = 0; j < buf_len%256; j++)
2344 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2345
2346 retval = rtsx_send_cmd(chip, 0, 250);
2347 if (retval < 0) {
2348 rtsx_trace(chip);
2349 return STATUS_FAIL;
2350 }
2351 }
2352
2353 memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256);
2354
2355 return STATUS_SUCCESS;
2356}
2357
2358int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2359{
2360 int retval;
2361 int i, j;
2362 u16 reg_addr;
2363 u8 *ptr;
2364
2365 if (!buf) {
2366 rtsx_trace(chip);
2367 return STATUS_ERROR;
2368 }
2369
2370 ptr = buf;
2371 reg_addr = PPBUF_BASE2;
2372 for (i = 0; i < buf_len/256; i++) {
2373 rtsx_init_cmd(chip);
2374
2375 for (j = 0; j < 256; j++) {
2376 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2377 *ptr);
2378 ptr++;
2379 }
2380
2381 retval = rtsx_send_cmd(chip, 0, 250);
2382 if (retval < 0) {
2383 rtsx_trace(chip);
2384 return STATUS_FAIL;
2385 }
2386 }
2387
2388 if (buf_len%256) {
2389 rtsx_init_cmd(chip);
2390
2391 for (j = 0; j < buf_len%256; j++) {
2392 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2393 *ptr);
2394 ptr++;
2395 }
2396
2397 retval = rtsx_send_cmd(chip, 0, 250);
2398 if (retval < 0) {
2399 rtsx_trace(chip);
2400 return STATUS_FAIL;
2401 }
2402 }
2403
2404 return STATUS_SUCCESS;
2405}
2406
2407int rtsx_check_chip_exist(struct rtsx_chip *chip)
2408{
2409 if (rtsx_readl(chip, 0) == 0xFFFFFFFF) {
2410 rtsx_trace(chip);
2411 return STATUS_FAIL;
2412 }
2413
2414 return STATUS_SUCCESS;
2415}
2416
2417int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2418{
2419 int retval;
2420 u8 mask = 0;
2421
2422 if (ctl & SSC_PDCTL)
2423 mask |= SSC_POWER_DOWN;
2424
2425#ifdef SUPPORT_OCP
2426 if (ctl & OC_PDCTL) {
2427 mask |= SD_OC_POWER_DOWN;
2428 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2429 mask |= MS_OC_POWER_DOWN;
2430 }
2431#endif
2432
2433 if (mask) {
2434 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2435 if (retval != STATUS_SUCCESS) {
2436 rtsx_trace(chip);
2437 return STATUS_FAIL;
2438 }
2439
2440 if (CHECK_PID(chip, 0x5288))
2441 wait_timeout(200);
2442 }
2443
2444 return STATUS_SUCCESS;
2445}
2446
2447int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2448{
2449 int retval;
2450 u8 mask = 0, val = 0;
2451
2452 if (ctl & SSC_PDCTL)
2453 mask |= SSC_POWER_DOWN;
2454
2455#ifdef SUPPORT_OCP
2456 if (ctl & OC_PDCTL) {
2457 mask |= SD_OC_POWER_DOWN;
2458 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2459 mask |= MS_OC_POWER_DOWN;
2460 }
2461#endif
2462
2463 if (mask) {
2464 val = mask;
2465 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2466 if (retval != STATUS_SUCCESS) {
2467 rtsx_trace(chip);
2468 return STATUS_FAIL;
2469 }
2470 }
2471
2472 return STATUS_SUCCESS;
2473}
2474
