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13#ifndef __M66592_UDC_H__
14#define __M66592_UDC_H__
15
16#include <linux/clk.h>
17#include <linux/usb/m66592.h>
18
19#define M66592_SYSCFG 0x00
20#define M66592_XTAL 0xC000
21#define M66592_XTAL48 0x8000
22#define M66592_XTAL24 0x4000
23#define M66592_XTAL12 0x0000
24#define M66592_XCKE 0x2000
25#define M66592_RCKE 0x1000
26#define M66592_PLLC 0x0800
27#define M66592_SCKE 0x0400
28#define M66592_ATCKM 0x0100
29#define M66592_HSE 0x0080
30#define M66592_DCFM 0x0040
31#define M66592_DMRPD 0x0020
32#define M66592_DPRPU 0x0010
33#define M66592_FSRPC 0x0004
34#define M66592_PCUT 0x0002
35#define M66592_USBE 0x0001
36
37#define M66592_SYSSTS 0x02
38#define M66592_LNST 0x0003
39#define M66592_SE1 0x0003
40#define M66592_KSTS 0x0002
41#define M66592_JSTS 0x0001
42#define M66592_SE0 0x0000
43
44#define M66592_DVSTCTR 0x04
45#define M66592_WKUP 0x0100
46#define M66592_RWUPE 0x0080
47#define M66592_USBRST 0x0040
48#define M66592_RESUME 0x0020
49#define M66592_UACT 0x0010
50#define M66592_RHST 0x0003
51#define M66592_HSMODE 0x0003
52#define M66592_FSMODE 0x0002
53#define M66592_HSPROC 0x0001
54
55#define M66592_TESTMODE 0x06
56#define M66592_UTST 0x000F
57#define M66592_H_TST_PACKET 0x000C
58#define M66592_H_TST_SE0_NAK 0x000B
59#define M66592_H_TST_K 0x000A
60#define M66592_H_TST_J 0x0009
61#define M66592_H_TST_NORMAL 0x0000
62#define M66592_P_TST_PACKET 0x0004
63#define M66592_P_TST_SE0_NAK 0x0003
64#define M66592_P_TST_K 0x0002
65#define M66592_P_TST_J 0x0001
66#define M66592_P_TST_NORMAL 0x0000
67
68
69#define M66592_CFBCFG 0x0A
70#define M66592_D0FBCFG 0x0C
71#define M66592_LITTLE 0x0100
72
73#define M66592_PINCFG 0x0A
74#define M66592_LDRV 0x8000
75#define M66592_BIGEND 0x0100
76
77#define M66592_DMA0CFG 0x0C
78#define M66592_DMA1CFG 0x0E
79#define M66592_DREQA 0x4000
80#define M66592_BURST 0x2000
81#define M66592_DACKA 0x0400
82#define M66592_DFORM 0x0380
83#define M66592_CPU_ADR_RD_WR 0x0000
84#define M66592_CPU_DACK_RD_WR 0x0100
85#define M66592_CPU_DACK_ONLY 0x0180
86#define M66592_SPLIT_DACK_ONLY 0x0200
87#define M66592_SPLIT_DACK_DSTB 0x0300
88#define M66592_DENDA 0x0040
89#define M66592_PKTM 0x0020
90#define M66592_DENDE 0x0010
91#define M66592_OBUS 0x0004
92
93
94#define M66592_CFIFO 0x10
95#define M66592_D0FIFO 0x14
96#define M66592_D1FIFO 0x18
97
98#define M66592_CFIFOSEL 0x1E
99#define M66592_D0FIFOSEL 0x24
100#define M66592_D1FIFOSEL 0x2A
101#define M66592_RCNT 0x8000
102#define M66592_REW 0x4000
103#define M66592_DCLRM 0x2000
104#define M66592_DREQE 0x1000
105#define M66592_MBW_8 0x0000
106#define M66592_MBW_16 0x0400
107#define M66592_MBW_32 0x0800
108#define M66592_TRENB 0x0200
109#define M66592_TRCLR 0x0100
110#define M66592_DEZPM 0x0080
111#define M66592_ISEL 0x0020
112#define M66592_CURPIPE 0x0007
113
114#define M66592_CFIFOCTR 0x20
115#define M66592_D0FIFOCTR 0x26
116#define M66592_D1FIFOCTR 0x2c
117#define M66592_BVAL 0x8000
118#define M66592_BCLR 0x4000
119#define M66592_FRDY 0x2000
120#define M66592_DTLN 0x0FFF
121
122#define M66592_CFIFOSIE 0x22
123#define M66592_TGL 0x8000
124#define M66592_SCLR 0x4000
125#define M66592_SBUSY 0x2000
126
127#define M66592_D0FIFOTRN 0x28
128#define M66592_D1FIFOTRN 0x2E
129#define M66592_TRNCNT 0xFFFF
130
131#define M66592_INTENB0 0x30
132#define M66592_VBSE 0x8000
133#define M66592_RSME 0x4000
134#define M66592_SOFE 0x2000
135#define M66592_DVSE 0x1000
136#define M66592_CTRE 0x0800
137#define M66592_BEMPE 0x0400
138#define M66592_NRDYE 0x0200
139#define M66592_BRDYE 0x0100
140#define M66592_URST 0x0080
141#define M66592_SADR 0x0040
142#define M66592_SCFG 0x0020
143#define M66592_SUSP 0x0010
144#define M66592_WDST 0x0008
145#define M66592_RDST 0x0004
146#define M66592_CMPL 0x0002
147#define M66592_SERR 0x0001
148
149#define M66592_INTENB1 0x32
150#define M66592_BCHGE 0x4000
151#define M66592_DTCHE 0x1000
152#define M66592_SIGNE 0x0020
153#define M66592_SACKE 0x0010
154#define M66592_BRDYM 0x0004
155#define M66592_INTL 0x0002
156#define M66592_PCSE 0x0001
157
158#define M66592_BRDYENB 0x36
159#define M66592_BRDYSTS 0x46
160#define M66592_BRDY7 0x0080
161#define M66592_BRDY6 0x0040
162#define M66592_BRDY5 0x0020
163#define M66592_BRDY4 0x0010
164#define M66592_BRDY3 0x0008
165#define M66592_BRDY2 0x0004
166#define M66592_BRDY1 0x0002
167#define M66592_BRDY0 0x0001
168
169#define M66592_NRDYENB 0x38
170#define M66592_NRDYSTS 0x48
171#define M66592_NRDY7 0x0080
172#define M66592_NRDY6 0x0040
173#define M66592_NRDY5 0x0020
174#define M66592_NRDY4 0x0010
175#define M66592_NRDY3 0x0008
176#define M66592_NRDY2 0x0004
177#define M66592_NRDY1 0x0002
178#define M66592_NRDY0 0x0001
179
180#define M66592_BEMPENB 0x3A
181#define M66592_BEMPSTS 0x4A
182#define M66592_BEMP7 0x0080
183#define M66592_BEMP6 0x0040
184#define M66592_BEMP5 0x0020
185#define M66592_BEMP4 0x0010
186#define M66592_BEMP3 0x0008
187#define M66592_BEMP2 0x0004
188#define M66592_BEMP1 0x0002
189#define M66592_BEMP0 0x0001
190
191#define M66592_SOFCFG 0x3C
192#define M66592_SOFM 0x000C
193#define M66592_SOF_125US 0x0008
194#define M66592_SOF_1MS 0x0004
195#define M66592_SOF_DISABLE 0x0000
196
197#define M66592_INTSTS0 0x40
198#define M66592_VBINT 0x8000
199#define M66592_RESM 0x4000
200#define M66592_SOFR 0x2000
201#define M66592_DVST 0x1000
202#define M66592_CTRT 0x0800
203#define M66592_BEMP 0x0400
204#define M66592_NRDY 0x0200
205#define M66592_BRDY 0x0100
206#define M66592_VBSTS 0x0080
207#define M66592_DVSQ 0x0070
208#define M66592_DS_SPD_CNFG 0x0070
209#define M66592_DS_SPD_ADDR 0x0060
210#define M66592_DS_SPD_DFLT 0x0050
211#define M66592_DS_SPD_POWR 0x0040
212#define M66592_DS_SUSP 0x0040
213#define M66592_DS_CNFG 0x0030
214#define M66592_DS_ADDS 0x0020
215#define M66592_DS_DFLT 0x0010
216#define M66592_DS_POWR 0x0000
217#define M66592_DVSQS 0x0030
218#define M66592_VALID 0x0008
219#define M66592_CTSQ 0x0007
220#define M66592_CS_SQER 0x0006
221#define M66592_CS_WRND 0x0005
222#define M66592_CS_WRSS 0x0004
223#define M66592_CS_WRDS 0x0003
224#define M66592_CS_RDSS 0x0002
225#define M66592_CS_RDDS 0x0001
226#define M66592_CS_IDST 0x0000
227
228#define M66592_INTSTS1 0x42
229#define M66592_BCHG 0x4000
230#define M66592_DTCH 0x1000
231#define M66592_SIGN 0x0020
232#define M66592_SACK 0x0010
233
234#define M66592_FRMNUM 0x4C
235#define M66592_OVRN 0x8000
236#define M66592_CRCE 0x4000
237#define M66592_SOFRM 0x0800
238#define M66592_FRNM 0x07FF
239
240#define M66592_UFRMNUM 0x4E
241#define M66592_UFRNM 0x0007
242
243#define M66592_RECOVER 0x50
244#define M66592_STSRECOV 0x0700
245#define M66592_STSR_HI 0x0400
246#define M66592_STSR_DEFAULT 0x0100
247#define M66592_STSR_ADDRESS 0x0200
248#define M66592_STSR_CONFIG 0x0300
249#define M66592_USBADDR 0x007F
250
251#define M66592_USBREQ 0x54
252#define M66592_bRequest 0xFF00
253#define M66592_GET_STATUS 0x0000
254#define M66592_CLEAR_FEATURE 0x0100
255#define M66592_ReqRESERVED 0x0200
256#define M66592_SET_FEATURE 0x0300
257#define M66592_ReqRESERVED1 0x0400
258#define M66592_SET_ADDRESS 0x0500
259#define M66592_GET_DESCRIPTOR 0x0600
260#define M66592_SET_DESCRIPTOR 0x0700
261#define M66592_GET_CONFIGURATION 0x0800
262#define M66592_SET_CONFIGURATION 0x0900
263#define M66592_GET_INTERFACE 0x0A00
264#define M66592_SET_INTERFACE 0x0B00
265#define M66592_SYNCH_FRAME 0x0C00
266#define M66592_bmRequestType 0x00FF
267#define M66592_bmRequestTypeDir 0x0080
268#define M66592_HOST_TO_DEVICE 0x0000
269#define M66592_DEVICE_TO_HOST 0x0080
270#define M66592_bmRequestTypeType 0x0060
271#define M66592_STANDARD 0x0000
272#define M66592_CLASS 0x0020
273#define M66592_VENDOR 0x0040
274#define M66592_bmRequestTypeRecip 0x001F
275#define M66592_DEVICE 0x0000
276#define M66592_INTERFACE 0x0001
277#define M66592_ENDPOINT 0x0002
278
279#define M66592_USBVAL 0x56
280#define M66592_wValue 0xFFFF
281
282#define M66592_ENDPOINT_HALT 0x0000
283#define M66592_DEVICE_REMOTE_WAKEUP 0x0001
284#define M66592_TEST_MODE 0x0002
285
286#define M66592_DT_TYPE 0xFF00
287#define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8)
288#define M66592_DT_DEVICE 0x01
289#define M66592_DT_CONFIGURATION 0x02
290#define M66592_DT_STRING 0x03
291#define M66592_DT_INTERFACE 0x04
292#define M66592_DT_ENDPOINT 0x05
293#define M66592_DT_DEVICE_QUALIFIER 0x06
294#define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07
295#define M66592_DT_INTERFACE_POWER 0x08
296#define M66592_DT_INDEX 0x00FF
297#define M66592_CONF_NUM 0x00FF
298#define M66592_ALT_SET 0x00FF
299
300#define M66592_USBINDEX 0x58
301#define M66592_wIndex 0xFFFF
302#define M66592_TEST_SELECT 0xFF00
303#define M66592_TEST_J 0x0100
304#define M66592_TEST_K 0x0200
305#define M66592_TEST_SE0_NAK 0x0300
306#define M66592_TEST_PACKET 0x0400
307#define M66592_TEST_FORCE_ENABLE 0x0500
308#define M66592_TEST_STSelectors 0x0600
309#define M66592_TEST_Reserved 0x4000
310#define M66592_TEST_VSTModes 0xC000
311#define M66592_EP_DIR 0x0080
312#define M66592_EP_DIR_IN 0x0080
313#define M66592_EP_DIR_OUT 0x0000
314
315#define M66592_USBLENG 0x5A
316#define M66592_wLength 0xFFFF
317
318#define M66592_DCPCFG 0x5C
319#define M66592_CNTMD 0x0100
320#define M66592_DIR 0x0010
321
322#define M66592_DCPMAXP 0x5E
323#define M66592_DEVSEL 0xC000
324#define M66592_DEVICE_0 0x0000
325#define M66592_DEVICE_1 0x4000
326#define M66592_DEVICE_2 0x8000
327#define M66592_DEVICE_3 0xC000
328#define M66592_MAXP 0x007F
329
330#define M66592_DCPCTR 0x60
331#define M66592_BSTS 0x8000
332#define M66592_SUREQ 0x4000
333#define M66592_SQCLR 0x0100
334#define M66592_SQSET 0x0080
335#define M66592_SQMON 0x0040
336#define M66592_CCPL 0x0004
337#define M66592_PID 0x0003
338#define M66592_PID_STALL 0x0002
339#define M66592_PID_BUF 0x0001
340#define M66592_PID_NAK 0x0000
341
342#define M66592_PIPESEL 0x64
343#define M66592_PIPENM 0x0007
344#define M66592_PIPE0 0x0000
345#define M66592_PIPE1 0x0001
346#define M66592_PIPE2 0x0002
347#define M66592_PIPE3 0x0003
348#define M66592_PIPE4 0x0004
349#define M66592_PIPE5 0x0005
350#define M66592_PIPE6 0x0006
351#define M66592_PIPE7 0x0007
352
353#define M66592_PIPECFG 0x66
354#define M66592_TYP 0xC000
355#define M66592_ISO 0xC000
356#define M66592_INT 0x8000
357#define M66592_BULK 0x4000
358#define M66592_BFRE 0x0400
359#define M66592_DBLB 0x0200
360#define M66592_CNTMD 0x0100
361#define M66592_SHTNAK 0x0080
362#define M66592_DIR 0x0010
363#define M66592_DIR_H_OUT 0x0010
364#define M66592_DIR_P_IN 0x0010
365#define M66592_DIR_H_IN 0x0000
366#define M66592_DIR_P_OUT 0x0000
367#define M66592_EPNUM 0x000F
368#define M66592_EP1 0x0001
369#define M66592_EP2 0x0002
370#define M66592_EP3 0x0003
371#define M66592_EP4 0x0004
372#define M66592_EP5 0x0005
373#define M66592_EP6 0x0006
374#define M66592_EP7 0x0007
375#define M66592_EP8 0x0008
376#define M66592_EP9 0x0009
377#define M66592_EP10 0x000A
378#define M66592_EP11 0x000B
379#define M66592_EP12 0x000C
380#define M66592_EP13 0x000D
381#define M66592_EP14 0x000E
382#define M66592_EP15 0x000F
383
384#define M66592_PIPEBUF 0x68
385#define M66592_BUFSIZE 0x7C00
386#define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10)
387#define M66592_BUFNMB 0x00FF
388
389#define M66592_PIPEMAXP 0x6A
390#define M66592_MXPS 0x07FF
391
392#define M66592_PIPEPERI 0x6C
393#define M66592_IFIS 0x1000
394#define M66592_IITV 0x0007
395
396#define M66592_PIPE1CTR 0x70
397#define M66592_PIPE2CTR 0x72
398#define M66592_PIPE3CTR 0x74
399#define M66592_PIPE4CTR 0x76
400#define M66592_PIPE5CTR 0x78
401#define M66592_PIPE6CTR 0x7A
402#define M66592_PIPE7CTR 0x7C
403#define M66592_BSTS 0x8000
404#define M66592_INBUFM 0x4000
405#define M66592_ACLRM 0x0200
406#define M66592_SQCLR 0x0100
407#define M66592_SQSET 0x0080
408#define M66592_SQMON 0x0040
409#define M66592_PID 0x0003
410
411#define M66592_INVALID_REG 0x7E
412
413
414#define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2)
415
416#define M66592_MAX_SAMPLING 10
417
418#define M66592_MAX_NUM_PIPE 8
419#define M66592_MAX_NUM_BULK 3
420#define M66592_MAX_NUM_ISOC 2
421#define M66592_MAX_NUM_INT 2
422
423#define M66592_BASE_PIPENUM_BULK 3
424#define M66592_BASE_PIPENUM_ISOC 1
425#define M66592_BASE_PIPENUM_INT 6
426
427#define M66592_BASE_BUFNUM 6
428#define M66592_MAX_BUFNUM 0x4F
429
430struct m66592_pipe_info {
431 u16 pipe;
432 u16 epnum;
433 u16 maxpacket;
434 u16 type;
435 u16 interval;
436 u16 dir_in;
437};
438
439struct m66592_request {
440 struct usb_request req;
441 struct list_head queue;
442};
443
444struct m66592_ep {
445 struct usb_ep ep;
446 struct m66592 *m66592;
447
448 struct list_head queue;
449 unsigned busy:1;
450 unsigned internal_ccpl:1;
451
452
453 unsigned use_dma:1;
454 u16 pipenum;
455 u16 type;
456
457
458 unsigned long fifoaddr;
459 unsigned long fifosel;
460 unsigned long fifoctr;
461 unsigned long fifotrn;
462 unsigned long pipectr;
463};
464
465struct m66592 {
466 spinlock_t lock;
467 void __iomem *reg;
468 struct clk *clk;
469 struct m66592_platdata *pdata;
470 unsigned long irq_trigger;
471
472 struct usb_gadget gadget;
473 struct usb_gadget_driver *driver;
474
475 struct m66592_ep ep[M66592_MAX_NUM_PIPE];
476 struct m66592_ep *pipenum2ep[M66592_MAX_NUM_PIPE];
477 struct m66592_ep *epaddr2ep[16];
478
479 struct usb_request *ep0_req;
480 __le16 ep0_data;
481 u16 old_vbus;
482
483 struct timer_list timer;
484
485 int scount;
486
487 int old_dvsq;
488
489
490 int bulk;
491 int interrupt;
492 int isochronous;
493 int num_dma;
494};
495#define to_m66592(g) (container_of((g), struct m66592, gadget))
496
497#define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget)
498#define m66592_to_gadget(m66592) (&m66592->gadget)
499
500#define is_bulk_pipe(pipenum) \
501 ((pipenum >= M66592_BASE_PIPENUM_BULK) && \
502 (pipenum < (M66592_BASE_PIPENUM_BULK + M66592_MAX_NUM_BULK)))
503#define is_interrupt_pipe(pipenum) \
504 ((pipenum >= M66592_BASE_PIPENUM_INT) && \
505 (pipenum < (M66592_BASE_PIPENUM_INT + M66592_MAX_NUM_INT)))
506#define is_isoc_pipe(pipenum) \
507 ((pipenum >= M66592_BASE_PIPENUM_ISOC) && \
508 (pipenum < (M66592_BASE_PIPENUM_ISOC + M66592_MAX_NUM_ISOC)))
509
510#define enable_irq_ready(m66592, pipenum) \
511 enable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
512#define disable_irq_ready(m66592, pipenum) \
513 disable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
514#define enable_irq_empty(m66592, pipenum) \
515 enable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
516#define disable_irq_empty(m66592, pipenum) \
517 disable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
518#define enable_irq_nrdy(m66592, pipenum) \
519 enable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
520#define disable_irq_nrdy(m66592, pipenum) \
521 disable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
522
523
524static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
525{
526 return ioread16(m66592->reg + offset);
527}
528
529static inline void m66592_read_fifo(struct m66592 *m66592,
530 unsigned long offset,
531 void *buf, unsigned long len)
532{
533 void __iomem *fifoaddr = m66592->reg + offset;
534
535 if (m66592->pdata->on_chip) {
536 len = (len + 3) / 4;
537 ioread32_rep(fifoaddr, buf, len);
538 } else {
539 len = (len + 1) / 2;
540 ioread16_rep(fifoaddr, buf, len);
541 }
542}
543
544static inline void m66592_write(struct m66592 *m66592, u16 val,
545 unsigned long offset)
546{
547 iowrite16(val, m66592->reg + offset);
548}
549
550static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
551 unsigned long offset)
552{
553 u16 tmp;
554 tmp = m66592_read(m66592, offset);
555 tmp = tmp & (~pat);
556 tmp = tmp | val;
557 m66592_write(m66592, tmp, offset);
558}
559
560#define m66592_bclr(m66592, val, offset) \
561 m66592_mdfy(m66592, 0, val, offset)
562#define m66592_bset(m66592, val, offset) \
563 m66592_mdfy(m66592, val, 0, offset)
564
565static inline void m66592_write_fifo(struct m66592 *m66592,
566 struct m66592_ep *ep,
567 void *buf, unsigned long len)
568{
569 void __iomem *fifoaddr = m66592->reg + ep->fifoaddr;
570
571 if (m66592->pdata->on_chip) {
572 unsigned long count;
573 unsigned char *pb;
574 int i;
575
576 count = len / 4;
577 iowrite32_rep(fifoaddr, buf, count);
578
579 if (len & 0x00000003) {
580 pb = buf + count * 4;
581 for (i = 0; i < (len & 0x00000003); i++) {
582 if (m66592_read(m66592, M66592_CFBCFG))
583 iowrite8(pb[i], fifoaddr + (3 - i));
584 else
585 iowrite8(pb[i], fifoaddr + i);
586 }
587 }
588 } else {
589 unsigned long odd = len & 0x0001;
590
591 len = len / 2;
592 iowrite16_rep(fifoaddr, buf, len);
593 if (odd) {
594 unsigned char *p = buf + len*2;
595 if (m66592->pdata->wr0_shorted_to_wr1)
596 m66592_bclr(m66592, M66592_MBW_16, ep->fifosel);
597 iowrite8(*p, fifoaddr);
598 if (m66592->pdata->wr0_shorted_to_wr1)
599 m66592_bset(m66592, M66592_MBW_16, ep->fifosel);
600 }
601 }
602}
603
604#endif
605
606
607