LXR linux/drivers/usb/musb/musb

   1/*
   2 * MUSB OTG driver defines
   3 *
   4 * Copyright 2005 Mentor Graphics Corporation
   5 * Copyright (C) 2005-2006 by Texas Instruments
   6 * Copyright (C) 2006-2007 Nokia Corporation
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License
  10 * version 2 as published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope that it will be useful, but
  13 * WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20 * 02110-1301 USA
  21 *
  22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 *
  33 */
  34
  35#ifndef __MUSB_CORE_H__
  36#define __MUSB_CORE_H__
  37
  38#include <linux/slab.h>
  39#include <linux/list.h>
  40#include <linux/interrupt.h>
  41#include <linux/errno.h>
  42#include <linux/timer.h>
  43#include <linux/device.h>
  44#include <linux/usb/ch9.h>
  45#include <linux/usb/gadget.h>
  46#include <linux/usb.h>
  47#include <linux/usb/otg.h>
  48#include <linux/usb/musb.h>
  49#include <linux/phy/phy.h>
  50#include <linux/workqueue.h>
  51
  52struct musb;
  53struct musb_hw_ep;
  54struct musb_ep;
  55
  56/* Helper defines for struct musb->hwvers */
  57#define MUSB_HWVERS_MAJOR(x)    ((x >> 10) & 0x1f)
  58#define MUSB_HWVERS_MINOR(x)    (x & 0x3ff)
  59#define MUSB_HWVERS_RC          0x8000
  60#define MUSB_HWVERS_1300        0x52C
  61#define MUSB_HWVERS_1400        0x590
  62#define MUSB_HWVERS_1800        0x720
  63#define MUSB_HWVERS_1900        0x784
  64#define MUSB_HWVERS_2000        0x800
  65
  66#include "musb_debug.h"
  67#include "musb_dma.h"
  68
  69#include "musb_io.h"
  70
  71#include "musb_gadget.h"
  72#include <linux/usb/hcd.h>
  73#include "musb_host.h"
  74
  75/* NOTE:  otg and peripheral-only state machines start at B_IDLE.
  76 * OTG or host-only go to A_IDLE when ID is sensed.
  77 */
  78#define is_peripheral_active(m)         (!(m)->is_host)
  79#define is_host_active(m)               ((m)->is_host)
  80
  81enum {
  82        MUSB_PORT_MODE_HOST     = 1,
  83        MUSB_PORT_MODE_GADGET,
  84        MUSB_PORT_MODE_DUAL_ROLE,
  85};
  86
  87/****************************** CONSTANTS ********************************/
  88
  89#ifndef MUSB_C_NUM_EPS
  90#define MUSB_C_NUM_EPS ((u8)16)
  91#endif
  92
  93#ifndef MUSB_MAX_END0_PACKET
  94#define MUSB_MAX_END0_PACKET ((u16)MUSB_EP0_FIFOSIZE)
  95#endif
  96
  97/* host side ep0 states */
  98enum musb_h_ep0_state {
  99        MUSB_EP0_IDLE,
 100        MUSB_EP0_START,                 /* expect ack of setup */
 101        MUSB_EP0_IN,                    /* expect IN DATA */
 102        MUSB_EP0_OUT,                   /* expect ack of OUT DATA */
 103        MUSB_EP0_STATUS,                /* expect ack of STATUS */
 104} __attribute__ ((packed));
 105
 106/* peripheral side ep0 states */
 107enum musb_g_ep0_state {
 108        MUSB_EP0_STAGE_IDLE,            /* idle, waiting for SETUP */
 109        MUSB_EP0_STAGE_SETUP,           /* received SETUP */
 110        MUSB_EP0_STAGE_TX,              /* IN data */
 111        MUSB_EP0_STAGE_RX,              /* OUT data */
 112        MUSB_EP0_STAGE_STATUSIN,        /* (after OUT data) */
 113        MUSB_EP0_STAGE_STATUSOUT,       /* (after IN data) */
 114        MUSB_EP0_STAGE_ACKWAIT,         /* after zlp, before statusin */
 115} __attribute__ ((packed));
 116
 117/*
 118 * OTG protocol constants.  See USB OTG 1.3 spec,
 119 * sections 5.5 "Device Timings" and 6.6.5 "Timers".
 120 */
 121#define OTG_TIME_A_WAIT_VRISE   100             /* msec (max) */
 122#define OTG_TIME_A_WAIT_BCON    1100            /* min 1 second */
 123#define OTG_TIME_A_AIDL_BDIS    200             /* min 200 msec */
 124#define OTG_TIME_B_ASE0_BRST    100             /* min 3.125 ms */
 125
 126/****************************** FUNCTIONS ********************************/
 127
 128#define MUSB_HST_MODE(_musb)\
 129        { (_musb)->is_host = true; }
 130#define MUSB_DEV_MODE(_musb) \
 131        { (_musb)->is_host = false; }
 132
 133#define test_devctl_hst_mode(_x) \
 134        (musb_readb((_x)->mregs, MUSB_DEVCTL)&MUSB_DEVCTL_HM)
 135
 136#define MUSB_MODE(musb) ((musb)->is_host ? "Host" : "Peripheral")
 137
 138/******************************** TYPES *************************************/
 139
 140struct musb_io;
 141
 142/**
 143 * struct musb_platform_ops - Operations passed to musb_core by HW glue layer
 144 * @quirks:     flags for platform specific quirks
 145 * @enable:     enable device
 146 * @disable:    disable device
 147 * @ep_offset:  returns the end point offset
 148 * @ep_select:  selects the specified end point
 149 * @fifo_mode:  sets the fifo mode
 150 * @fifo_offset: returns the fifo offset
 151 * @readb:      read 8 bits
 152 * @writeb:     write 8 bits
 153 * @readw:      read 16 bits
 154 * @writew:     write 16 bits
 155 * @readl:      read 32 bits
 156 * @writel:     write 32 bits
 157 * @read_fifo:  reads the fifo
 158 * @write_fifo: writes to fifo
 159 * @dma_init:   platform specific dma init function
 160 * @dma_exit:   platform specific dma exit function
 161 * @init:       turns on clocks, sets up platform-specific registers, etc
 162 * @exit:       undoes @init
 163 * @set_mode:   forcefully changes operating mode
 164 * @try_idle:   tries to idle the IP
 165 * @recover:    platform-specific babble recovery
 166 * @vbus_status: returns vbus status if possible
 167 * @set_vbus:   forces vbus status
 168 * @adjust_channel_params: pre check for standard dma channel_program func
 169 * @pre_root_reset_end: called before the root usb port reset flag gets cleared
 170 * @post_root_reset_end: called after the root usb port reset flag gets cleared
 171 */
 172struct musb_platform_ops {
 173
 174#define MUSB_DMA_UX500          BIT(6)
 175#define MUSB_DMA_CPPI41         BIT(5)
 176#define MUSB_DMA_CPPI           BIT(4)
 177#define MUSB_DMA_TUSB_OMAP      BIT(3)
 178#define MUSB_DMA_INVENTRA       BIT(2)
 179#define MUSB_IN_TUSB            BIT(1)
 180#define MUSB_INDEXED_EP         BIT(0)
 181        u32     quirks;
 182
 183        int     (*init)(struct musb *musb);
 184        int     (*exit)(struct musb *musb);
 185
 186        void    (*enable)(struct musb *musb);
 187        void    (*disable)(struct musb *musb);
 188
 189        u32     (*ep_offset)(u8 epnum, u16 offset);
 190        void    (*ep_select)(void __iomem *mbase, u8 epnum);
 191        u16     fifo_mode;
 192        u32     (*fifo_offset)(u8 epnum);
 193        u32     (*busctl_offset)(u8 epnum, u16 offset);
 194        u8      (*readb)(const void __iomem *addr, unsigned offset);
 195        void    (*writeb)(void __iomem *addr, unsigned offset, u8 data);
 196        u16     (*readw)(const void __iomem *addr, unsigned offset);
 197        void    (*writew)(void __iomem *addr, unsigned offset, u16 data);
 198        u32     (*readl)(const void __iomem *addr, unsigned offset);
 199        void    (*writel)(void __iomem *addr, unsigned offset, u32 data);
 200        void    (*read_fifo)(struct musb_hw_ep *hw_ep, u16 len, u8 *buf);
 201        void    (*write_fifo)(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf);
 202        struct dma_controller *
 203                (*dma_init) (struct musb *musb, void __iomem *base);
 204        void    (*dma_exit)(struct dma_controller *c);
 205        int     (*set_mode)(struct musb *musb, u8 mode);
 206        void    (*try_idle)(struct musb *musb, unsigned long timeout);
 207        int     (*recover)(struct musb *musb);
 208
 209        int     (*vbus_status)(struct musb *musb);
 210        void    (*set_vbus)(struct musb *musb, int on);
 211
 212        int     (*adjust_channel_params)(struct dma_channel *channel,
 213                                u16 packet_sz, u8 *mode,
 214                                dma_addr_t *dma_addr, u32 *len);
 215        void    (*pre_root_reset_end)(struct musb *musb);
 216        void    (*post_root_reset_end)(struct musb *musb);
 217};
 218
 219/*
 220 * struct musb_hw_ep - endpoint hardware (bidirectional)
 221 *
 222 * Ordered slightly for better cacheline locality.
 223 */
 224struct musb_hw_ep {
 225        struct musb             *musb;
 226        void __iomem            *fifo;
 227        void __iomem            *regs;
 228
 229#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
 230        void __iomem            *conf;
 231#endif
 232
 233        /* index in musb->endpoints[]  */
 234        u8                      epnum;
 235
 236        /* hardware configuration, possibly dynamic */
 237        bool                    is_shared_fifo;
 238        bool                    tx_double_buffered;
 239        bool                    rx_double_buffered;
 240        u16                     max_packet_sz_tx;
 241        u16                     max_packet_sz_rx;
 242
 243        struct dma_channel      *tx_channel;
 244        struct dma_channel      *rx_channel;
 245
 246#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
 247        /* TUSB has "asynchronous" and "synchronous" dma modes */
 248        dma_addr_t              fifo_async;
 249        dma_addr_t              fifo_sync;
 250        void __iomem            *fifo_sync_va;
 251#endif
 252
 253        /* currently scheduled peripheral endpoint */
 254        struct musb_qh          *in_qh;
 255        struct musb_qh          *out_qh;
 256
 257        u8                      rx_reinit;
 258        u8                      tx_reinit;
 259
 260        /* peripheral side */
 261        struct musb_ep          ep_in;                  /* TX */
 262        struct musb_ep          ep_out;                 /* RX */
 263};
 264
 265static inline struct musb_request *next_in_request(struct musb_hw_ep *hw_ep)
 266{
 267        return next_request(&hw_ep->ep_in);
 268}
 269
 270static inline struct musb_request *next_out_request(struct musb_hw_ep *hw_ep)
 271{
 272        return next_request(&hw_ep->ep_out);
 273}
 274
 275struct musb_csr_regs {
 276        /* FIFO registers */
 277        u16 txmaxp, txcsr, rxmaxp, rxcsr;
 278        u16 rxfifoadd, txfifoadd;
 279        u8 txtype, txinterval, rxtype, rxinterval;
 280        u8 rxfifosz, txfifosz;
 281        u8 txfunaddr, txhubaddr, txhubport;
 282        u8 rxfunaddr, rxhubaddr, rxhubport;
 283};
 284
 285struct musb_context_registers {
 286
 287        u8 power;
 288        u8 intrusbe;
 289        u16 frame;
 290        u8 index, testmode;
 291
 292        u8 devctl, busctl, misc;
 293        u32 otg_interfsel;
 294
 295        struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
 296};
 297
 298/*
 299 * struct musb - Driver instance data.
 300 */
 301struct musb {
 302        /* device lock */
 303        spinlock_t              lock;
 304
 305        struct musb_io          io;
 306        const struct musb_platform_ops *ops;
 307        struct musb_context_registers context;
 308
 309        irqreturn_t             (*isr)(int, void *);
 310        struct work_struct      irq_work;
 311        struct delayed_work     deassert_reset_work;
 312        struct delayed_work     finish_resume_work;
 313        u16                     hwvers;
 314
 315        u16                     intrrxe;
 316        u16                     intrtxe;
 317/* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
 318#define MUSB_PORT_STAT_RESUME   (1 << 31)
 319
 320        u32                     port1_status;
 321
 322        unsigned long           rh_timer;
 323
 324        enum musb_h_ep0_state   ep0_stage;
 325
 326        /* bulk traffic normally dedicates endpoint hardware, and each
 327         * direction has its own ring of host side endpoints.
 328         * we try to progress the transfer at the head of each endpoint's
 329         * queue until it completes or NAKs too much; then we try the next
 330         * endpoint.
 331         */
 332        struct musb_hw_ep       *bulk_ep;
 333
 334        struct list_head        control;        /* of musb_qh */
 335        struct list_head        in_bulk;        /* of musb_qh */
 336        struct list_head        out_bulk;       /* of musb_qh */
 337
 338        struct timer_list       otg_timer;
 339        struct notifier_block   nb;
 340
 341        struct dma_controller   *dma_controller;
 342
 343        struct device           *controller;
 344        void __iomem            *ctrl_base;
 345        void __iomem            *mregs;
 346
 347#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
 348        dma_addr_t              async;
 349        dma_addr_t              sync;
 350        void __iomem            *sync_va;
 351        u8                      tusb_revision;
 352#endif
 353
 354        /* passed down from chip/board specific irq handlers */
 355        u8                      int_usb;
 356        u16                     int_rx;
 357        u16                     int_tx;
 358
 359        struct usb_phy          *xceiv;
 360        struct phy              *phy;
 361
 362        int nIrq;
 363        unsigned                irq_wake:1;
 364
 365        struct musb_hw_ep        endpoints[MUSB_C_NUM_EPS];
 366#define control_ep              endpoints
 367
 368#define VBUSERR_RETRY_COUNT     3
 369        u16                     vbuserr_retry;
 370        u16 epmask;
 371        u8 nr_endpoints;
 372
 373        int                     (*board_set_power)(int state);
 374
 375        u8                      min_power;      /* vbus for periph, in mA/2 */
 376
 377        int                     port_mode;      /* MUSB_PORT_MODE_* */
 378        bool                    is_host;
 379
 380        int                     a_wait_bcon;    /* VBUS timeout in msecs */
 381        unsigned long           idle_timeout;   /* Next timeout in jiffies */
 382
 383        /* active means connected and not suspended */
 384        unsigned                is_active:1;
 385
 386        unsigned is_multipoint:1;
 387
 388        unsigned                hb_iso_rx:1;    /* high bandwidth iso rx? */
 389        unsigned                hb_iso_tx:1;    /* high bandwidth iso tx? */
 390        unsigned                dyn_fifo:1;     /* dynamic FIFO supported? */
 391
 392        unsigned                bulk_split:1;
 393#define can_bulk_split(musb,type) \
 394        (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split)
 395
 396        unsigned                bulk_combine:1;
 397#define can_bulk_combine(musb,type) \
 398        (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine)
 399
 400        /* is_suspended means USB B_PERIPHERAL suspend */
 401        unsigned                is_suspended:1;
 402        unsigned                need_finish_resume :1;
 403
 404        /* may_wakeup means remote wakeup is enabled */
 405        unsigned                may_wakeup:1;
 406
 407        /* is_self_powered is reported in device status and the
 408         * config descriptor.  is_bus_powered means B_PERIPHERAL
 409         * draws some VBUS current; both can be true.
 410         */
 411        unsigned                is_self_powered:1;
 412        unsigned                is_bus_powered:1;
 413
 414        unsigned                set_address:1;
 415        unsigned                test_mode:1;
 416        unsigned                softconnect:1;
 417
 418        u8                      address;
 419        u8                      test_mode_nr;
 420        u16                     ackpend;                /* ep0 */
 421        enum musb_g_ep0_state   ep0_state;
 422        struct usb_gadget       g;                      /* the gadget */
 423        struct usb_gadget_driver *gadget_driver;        /* its driver */
 424        struct usb_hcd          *hcd;                   /* the usb hcd */
 425
 426        /*
 427         * FIXME: Remove this flag.
 428         *
 429         * This is only added to allow Blackfin to work
 430         * with current driver. For some unknown reason
 431         * Blackfin doesn't work with double buffering
 432         * and that's enabled by default.
 433         *
 434         * We added this flag to forcefully disable double
 435         * buffering until we get it working.
 436         */
 437        unsigned                double_buffer_not_ok:1;
 438
 439        struct musb_hdrc_config *config;
 440
 441        int                     xceiv_old_state;
 442#ifdef CONFIG_DEBUG_FS
 443        struct dentry           *debugfs_root;
 444#endif
 445};
 446
 447/* This must be included after struct musb is defined */
 448#include "musb_regs.h"
 449
 450static inline struct musb *gadget_to_musb(struct usb_gadget *g)
 451{
 452        return container_of(g, struct musb, g);
 453}
 454
 455#ifdef CONFIG_BLACKFIN
 456static inline int musb_read_fifosize(struct musb *musb,
 457                struct musb_hw_ep *hw_ep, u8 epnum)
 458{
 459        musb->nr_endpoints++;
 460        musb->epmask |= (1 << epnum);
 461
 462        if (epnum < 5) {
 463                hw_ep->max_packet_sz_tx = 128;
 464                hw_ep->max_packet_sz_rx = 128;
 465        } else {
 466                hw_ep->max_packet_sz_tx = 1024;
 467                hw_ep->max_packet_sz_rx = 1024;
 468        }
 469        hw_ep->is_shared_fifo = false;
 470
 471        return 0;
 472}
 473
 474static inline void musb_configure_ep0(struct musb *musb)
 475{
 476        musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
 477        musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
 478        musb->endpoints[0].is_shared_fifo = true;
 479}
 480
 481#else
 482
 483static inline int musb_read_fifosize(struct musb *musb,
 484                struct musb_hw_ep *hw_ep, u8 epnum)
 485{
 486        void __iomem *mbase = musb->mregs;
 487        u8 reg = 0;
 488
 489        /* read from core using indexed model */
 490        reg = musb_readb(mbase, musb->io.ep_offset(epnum, MUSB_FIFOSIZE));
 491        /* 0's returned when no more endpoints */
 492        if (!reg)
 493                return -ENODEV;
 494
 495        musb->nr_endpoints++;
 496        musb->epmask |= (1 << epnum);
 497
 498        hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
 499
 500        /* shared TX/RX FIFO? */
 501        if ((reg & 0xf0) == 0xf0) {
 502                hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
 503                hw_ep->is_shared_fifo = true;
 504                return 0;
 505        } else {
 506                hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
 507                hw_ep->is_shared_fifo = false;
 508        }
 509
 510        return 0;
 511}
 512
 513static inline void musb_configure_ep0(struct musb *musb)
 514{
 515        musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
 516        musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
 517        musb->endpoints[0].is_shared_fifo = true;
 518}
 519#endif /* CONFIG_BLACKFIN */
 520
 521
 522/***************************** Glue it together *****************************/
 523
 524extern const char musb_driver_name[];
 525
 526extern void musb_stop(struct musb *musb);
 527extern void musb_start(struct musb *musb);
 528
 529extern void musb_write_fifo(struct musb_hw_ep *ep, u16 len, const u8 *src);
 530extern void musb_read_fifo(struct musb_hw_ep *ep, u16 len, u8 *dst);
 531
 532extern void musb_load_testpacket(struct musb *);
 533
 534extern irqreturn_t musb_interrupt(struct musb *);
 535
 536extern void musb_hnp_stop(struct musb *musb);
 537
 538static inline void musb_platform_set_vbus(struct musb *musb, int is_on)
 539{
 540        if (musb->ops->set_vbus)
 541                musb->ops->set_vbus(musb, is_on);
 542}
 543
 544static inline void musb_platform_enable(struct musb *musb)
 545{
 546        if (musb->ops->enable)
 547                musb->ops->enable(musb);
 548}
 549
 550static inline void musb_platform_disable(struct musb *musb)
 551{
 552        if (musb->ops->disable)
 553                musb->ops->disable(musb);
 554}
 555
 556static inline int musb_platform_set_mode(struct musb *musb, u8 mode)
 557{
 558        if (!musb->ops->set_mode)
 559                return 0;
 560
 561        return musb->ops->set_mode(musb, mode);
 562}
 563
 564static inline void musb_platform_try_idle(struct musb *musb,
 565                unsigned long timeout)
 566{
 567        if (musb->ops->try_idle)
 568                musb->ops->try_idle(musb, timeout);
 569}
 570
 571static inline int  musb_platform_recover(struct musb *musb)
 572{
 573        if (!musb->ops->recover)
 574                return 0;
 575
 576        return musb->ops->recover(musb);
 577}
 578
 579static inline int musb_platform_get_vbus_status(struct musb *musb)
 580{
 581        if (!musb->ops->vbus_status)
 582                return 0;
 583
 584        return musb->ops->vbus_status(musb);
 585}
 586
 587static inline int musb_platform_init(struct musb *musb)
 588{
 589        if (!musb->ops->init)
 590                return -EINVAL;
 591
 592        return musb->ops->init(musb);
 593}
 594
 595static inline int musb_platform_exit(struct musb *musb)
 596{
 597        if (!musb->ops->exit)
 598                return -EINVAL;
 599
 600        return musb->ops->exit(musb);
 601}
 602
 603static inline void musb_platform_pre_root_reset_end(struct musb *musb)
 604{
 605        if (musb->ops->pre_root_reset_end)
 606                musb->ops->pre_root_reset_end(musb);
 607}
 608
 609static inline void musb_platform_post_root_reset_end(struct musb *musb)
 610{
 611        if (musb->ops->post_root_reset_end)
 612                musb->ops->post_root_reset_end(musb);
 613}
 614
 615#endif  /* __MUSB_CORE_H__ */
 616