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53#define RADEON_VERSION "0.2.0"
54
55#include "radeonfb.h"
56
57#include <linux/module.h>
58#include <linux/moduleparam.h>
59#include <linux/kernel.h>
60#include <linux/errno.h>
61#include <linux/string.h>
62#include <linux/ctype.h>
63#include <linux/mm.h>
64#include <linux/slab.h>
65#include <linux/delay.h>
66#include <linux/time.h>
67#include <linux/fb.h>
68#include <linux/ioport.h>
69#include <linux/init.h>
70#include <linux/pci.h>
71#include <linux/vmalloc.h>
72#include <linux/device.h>
73
74#include <asm/io.h>
75#include <linux/uaccess.h>
76
77#ifdef CONFIG_PPC
78
79#include <asm/pci-bridge.h>
80#include "../macmodes.h"
81
82#ifdef CONFIG_BOOTX_TEXT
83#include <asm/btext.h>
84#endif
85
86#endif
87
88#include <video/radeon.h>
89#include <linux/radeonfb.h>
90
91#include "../edid.h"
92#include "ati_ids.h"
93
94#define MAX_MAPPED_VRAM (2048*2048*4)
95#define MIN_MAPPED_VRAM (1024*768*1)
96
97#define CHIP_DEF(id, family, flags) \
98 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
99
100static struct pci_device_id radeonfb_pci_table[] = {
101
102 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
103 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
104
105 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
106 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
107
108 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
109 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
110 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
111
112 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
113
114 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
115
116 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117
118 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119
120 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121
122 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123
124 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
125 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
126
127 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
128
129 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
130
131 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
132
133 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
134 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
135
136 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
137 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
138
139 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
143
144 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
145 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
146
147 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
148
149 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
150 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
151
152 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
153 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
154
155 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
156 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
157
158 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
159 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
160 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
162
163 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
165
166 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
168
169 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
172 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
173
174 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180
181 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
182 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
184 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
187
188 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
196
197 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
200 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
201 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
204 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
207 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
208 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
215 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
224
225 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
226 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
227 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
229 { 0, }
230};
231MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
232
233
234typedef struct {
235 u16 reg;
236 u32 val;
237} reg_val;
238
239
240
241
242
243static reg_val common_regs[] = {
244 { OVR_CLR, 0 },
245 { OVR_WID_LEFT_RIGHT, 0 },
246 { OVR_WID_TOP_BOTTOM, 0 },
247 { OV0_SCALE_CNTL, 0 },
248 { SUBPIC_CNTL, 0 },
249 { VIPH_CONTROL, 0 },
250 { I2C_CNTL_1, 0 },
251 { GEN_INT_CNTL, 0 },
252 { CAP0_TRIG_CNTL, 0 },
253 { CAP1_TRIG_CNTL, 0 },
254};
255
256
257
258
259
260static char *mode_option;
261static char *monitor_layout;
262static bool noaccel = 0;
263static int default_dynclk = -2;
264static bool nomodeset = 0;
265static bool ignore_edid = 0;
266static bool mirror = 0;
267static int panel_yres = 0;
268static bool force_dfp = 0;
269static bool force_measure_pll = 0;
270static bool nomtrr = 0;
271static bool force_sleep;
272static bool ignore_devlist;
273#ifdef CONFIG_PMAC_BACKLIGHT
274static int backlight = 1;
275#else
276static int backlight = 0;
277#endif
278
279
280
281
282
283static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
284{
285 if (!rinfo->bios_seg)
286 return;
287 pci_unmap_rom(dev, rinfo->bios_seg);
288}
289
290static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
291{
292 void __iomem *rom;
293 u16 dptr;
294 u8 rom_type;
295 size_t rom_size;
296
297
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299
300
301
302
303 unsigned int temp;
304 temp = INREG(MPP_TB_CONFIG);
305 temp &= 0x00ffffffu;
306 temp |= 0x04 << 24;
307 OUTREG(MPP_TB_CONFIG, temp);
308 temp = INREG(MPP_TB_CONFIG);
309
310 rom = pci_map_rom(dev, &rom_size);
311 if (!rom) {
312 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
313 pci_name(rinfo->pdev));
314 return -ENOMEM;
315 }
316
317 rinfo->bios_seg = rom;
318
319
320 if (BIOS_IN16(0) != 0xaa55) {
321 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
322 "should be 0xaa55\n",
323 pci_name(rinfo->pdev), BIOS_IN16(0));
324 goto failed;
325 }
326
327 dptr = BIOS_IN16(0x18);
328
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352
353 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
354 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
355 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
356 goto anyway;
357 }
358 rom_type = BIOS_IN8(dptr + 0x14);
359 switch(rom_type) {
360 case 0:
361 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
362 break;
363 case 1:
364 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
365 goto failed;
366 case 2:
367 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
368 goto failed;
369 default:
370 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
371 goto failed;
372 }
373 anyway:
374
375 rinfo->fp_bios_start = BIOS_IN16(0x48);
376 return 0;
377
378 failed:
379 rinfo->bios_seg = NULL;
380 radeon_unmap_ROM(rinfo, dev);
381 return -ENXIO;
382}
383
384#ifdef CONFIG_X86
385static int radeon_find_mem_vbios(struct radeonfb_info *rinfo)
386{
387
388
389
390
391
392 u32 segstart;
393 void __iomem *rom_base = NULL;
394
395 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
396 rom_base = ioremap(segstart, 0x10000);
397 if (rom_base == NULL)
398 return -ENOMEM;
399 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
400 break;
401 iounmap(rom_base);
402 rom_base = NULL;
403 }
404 if (rom_base == NULL)
405 return -ENXIO;
406
407
408 rinfo->bios_seg = rom_base;
409 rinfo->fp_bios_start = BIOS_IN16(0x48);
410
411 return 0;
412}
413#endif
414
415#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
416
417
418
419
420static int radeon_read_xtal_OF(struct radeonfb_info *rinfo)
421{
422 struct device_node *dp = rinfo->of_node;
423 const u32 *val;
424
425 if (dp == NULL)
426 return -ENODEV;
427 val = of_get_property(dp, "ATY,RefCLK", NULL);
428 if (!val || !*val) {
429 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
430 return -EINVAL;
431 }
432
433 rinfo->pll.ref_clk = (*val) / 10;
434
435 val = of_get_property(dp, "ATY,SCLK", NULL);
436 if (val && *val)
437 rinfo->pll.sclk = (*val) / 10;
438
439 val = of_get_property(dp, "ATY,MCLK", NULL);
440 if (val && *val)
441 rinfo->pll.mclk = (*val) / 10;
442
443 return 0;
444}
445#endif
446
447
448
449
450static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
451{
452 unsigned char ppll_div_sel;
453 unsigned Ns, Nm, M;
454 unsigned sclk, mclk, tmp, ref_div;
455 int hTotal, vTotal, num, denom, m, n;
456 unsigned long long hz, vclk;
457 long xtal;
458 struct timeval start_tv, stop_tv;
459 long total_secs, total_usecs;
460 int i;
461
462
463
464
465
466
467 tmp = INREG16(DEVICE_ID);
468
469 local_irq_disable();
470
471 for(i=0; i<1000000; i++)
472 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
473 break;
474
475 do_gettimeofday(&start_tv);
476
477 for(i=0; i<1000000; i++)
478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
479 break;
480
481 for(i=0; i<1000000; i++)
482 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
483 break;
484
485 do_gettimeofday(&stop_tv);
486
487 local_irq_enable();
488
489 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
490 if (total_secs > 10)
491 return -1;
492 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
493 total_usecs += total_secs * 1000000;
494 if (total_usecs < 0)
495 total_usecs = -total_usecs;
496 hz = 1000000/total_usecs;
497
498 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
499 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
500 vclk = (long long)hTotal * (long long)vTotal * hz;
501
502 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
503 case 0:
504 default:
505 num = 1;
506 denom = 1;
507 break;
508 case 1:
509 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
510 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
511 num = 2*n;
512 denom = 2*m;
513 break;
514 case 2:
515 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
516 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
517 num = 2*n;
518 denom = 2*m;
519 break;
520 }
521
522 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
523 radeon_pll_errata_after_index(rinfo);
524
525 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
526 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
527
528 num *= n;
529 denom *= m;
530
531 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
532 case 1:
533 denom *= 2;
534 break;
535 case 2:
536 denom *= 4;
537 break;
538 case 3:
539 denom *= 8;
540 break;
541 case 4:
542 denom *= 3;
543 break;
544 case 6:
545 denom *= 6;
546 break;
547 case 7:
548 denom *= 12;
549 break;
550 }
551
552 vclk *= denom;
553 do_div(vclk, 1000 * num);
554 xtal = vclk;
555
556 if ((xtal > 26900) && (xtal < 27100))
557 xtal = 2700;
558 else if ((xtal > 14200) && (xtal < 14400))
559 xtal = 1432;
560 else if ((xtal > 29400) && (xtal < 29600))
561 xtal = 2950;
562 else {
563 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
564 return -1;
565 }
566
567 tmp = INPLL(M_SPLL_REF_FB_DIV);
568 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
569
570 Ns = (tmp & 0xff0000) >> 16;
571 Nm = (tmp & 0xff00) >> 8;
572 M = (tmp & 0xff);
573 sclk = round_div((2 * Ns * xtal), (2 * M));
574 mclk = round_div((2 * Nm * xtal), (2 * M));
575
576
577 rinfo->pll.ref_clk = xtal;
578 rinfo->pll.ref_div = ref_div;
579 rinfo->pll.sclk = sclk;
580 rinfo->pll.mclk = mclk;
581
582 return 0;
583}
584
585
586
587
588static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
589{
590
591
592
593
594
595 switch (rinfo->chipset) {
596 case PCI_DEVICE_ID_ATI_RADEON_QW:
597 case PCI_DEVICE_ID_ATI_RADEON_QX:
598 rinfo->pll.ppll_max = 35000;
599 rinfo->pll.ppll_min = 12000;
600 rinfo->pll.mclk = 23000;
601 rinfo->pll.sclk = 23000;
602 rinfo->pll.ref_clk = 2700;
603 break;
604 case PCI_DEVICE_ID_ATI_RADEON_QL:
605 case PCI_DEVICE_ID_ATI_RADEON_QN:
606 case PCI_DEVICE_ID_ATI_RADEON_QO:
607 case PCI_DEVICE_ID_ATI_RADEON_Ql:
608 case PCI_DEVICE_ID_ATI_RADEON_BB:
609 rinfo->pll.ppll_max = 35000;
610 rinfo->pll.ppll_min = 12000;
611 rinfo->pll.mclk = 27500;
612 rinfo->pll.sclk = 27500;
613 rinfo->pll.ref_clk = 2700;
614 break;
615 case PCI_DEVICE_ID_ATI_RADEON_Id:
616 case PCI_DEVICE_ID_ATI_RADEON_Ie:
617 case PCI_DEVICE_ID_ATI_RADEON_If:
618 case PCI_DEVICE_ID_ATI_RADEON_Ig:
619 rinfo->pll.ppll_max = 35000;
620 rinfo->pll.ppll_min = 12000;
621 rinfo->pll.mclk = 25000;
622 rinfo->pll.sclk = 25000;
623 rinfo->pll.ref_clk = 2700;
624 break;
625 case PCI_DEVICE_ID_ATI_RADEON_ND:
626 case PCI_DEVICE_ID_ATI_RADEON_NE:
627 case PCI_DEVICE_ID_ATI_RADEON_NF:
628 case PCI_DEVICE_ID_ATI_RADEON_NG:
629 rinfo->pll.ppll_max = 40000;
630 rinfo->pll.ppll_min = 20000;
631 rinfo->pll.mclk = 27000;
632 rinfo->pll.sclk = 27000;
633 rinfo->pll.ref_clk = 2700;
634 break;
635 case PCI_DEVICE_ID_ATI_RADEON_QD:
636 case PCI_DEVICE_ID_ATI_RADEON_QE:
637 case PCI_DEVICE_ID_ATI_RADEON_QF:
638 case PCI_DEVICE_ID_ATI_RADEON_QG:
639 default:
640 rinfo->pll.ppll_max = 35000;
641 rinfo->pll.ppll_min = 12000;
642 rinfo->pll.mclk = 16600;
643 rinfo->pll.sclk = 16600;
644 rinfo->pll.ref_clk = 2700;
645 break;
646 }
647 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
648
649
650#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
651
652
653
654 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
655 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
656 goto found;
657 }
658#endif
659
660
661
662
663
664 if (!force_measure_pll && rinfo->bios_seg) {
665 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
666
667 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
668 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
669 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
670 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
671 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
672 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
673
674 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
675 goto found;
676 }
677
678
679
680
681
682 if (radeon_probe_pll_params(rinfo) == 0) {
683 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
684 goto found;
685 }
686
687
688
689
690 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
691
692found:
693
694
695
696
697
698 if (rinfo->pll.mclk == 0)
699 rinfo->pll.mclk = 20000;
700 if (rinfo->pll.sclk == 0)
701 rinfo->pll.sclk = 20000;
702
703 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
704 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
705 rinfo->pll.ref_div,
706 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
707 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
708 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
709}
710
711static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
712{
713 struct radeonfb_info *rinfo = info->par;
714 struct fb_var_screeninfo v;
715 int nom, den;
716 unsigned int pitch;
717
718 if (radeon_match_mode(rinfo, &v, var))
719 return -EINVAL;
720
721 switch (v.bits_per_pixel) {
722 case 0 ... 8:
723 v.bits_per_pixel = 8;
724 break;
725 case 9 ... 16:
726 v.bits_per_pixel = 16;
727 break;
728 case 17 ... 24:
729#if 0
730 v.bits_per_pixel = 24;
731 break;
732#endif
733 return -EINVAL;
734 case 25 ... 32:
735 v.bits_per_pixel = 32;
736 break;
737 default:
738 return -EINVAL;
739 }
740
741 switch (var_to_depth(&v)) {
742 case 8:
743 nom = den = 1;
744 v.red.offset = v.green.offset = v.blue.offset = 0;
745 v.red.length = v.green.length = v.blue.length = 8;
746 v.transp.offset = v.transp.length = 0;
747 break;
748 case 15:
749 nom = 2;
750 den = 1;
751 v.red.offset = 10;
752 v.green.offset = 5;
753 v.blue.offset = 0;
754 v.red.length = v.green.length = v.blue.length = 5;
755 v.transp.offset = v.transp.length = 0;
756 break;
757 case 16:
758 nom = 2;
759 den = 1;
760 v.red.offset = 11;
761 v.green.offset = 5;
762 v.blue.offset = 0;
763 v.red.length = 5;
764 v.green.length = 6;
765 v.blue.length = 5;
766 v.transp.offset = v.transp.length = 0;
767 break;
768 case 24:
769 nom = 4;
770 den = 1;
771 v.red.offset = 16;
772 v.green.offset = 8;
773 v.blue.offset = 0;
774 v.red.length = v.blue.length = v.green.length = 8;
775 v.transp.offset = v.transp.length = 0;
776 break;
777 case 32:
778 nom = 4;
779 den = 1;
780 v.red.offset = 16;
781 v.green.offset = 8;
782 v.blue.offset = 0;
783 v.red.length = v.blue.length = v.green.length = 8;
784 v.transp.offset = 24;
785 v.transp.length = 8;
786 break;
787 default:
788 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
789 var->xres, var->yres, var->bits_per_pixel);
790 return -EINVAL;
791 }
792
793 if (v.yres_virtual < v.yres)
794 v.yres_virtual = v.yres;
795 if (v.xres_virtual < v.xres)
796 v.xres_virtual = v.xres;
797
798
799
800
801
802 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
803 v.xres_virtual = v.xres_virtual & ~7ul;
804 } else {
805 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
806 & ~(0x3f)) >> 6;
807 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
808 }
809
810 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
811 return -EINVAL;
812
813 if (v.xres_virtual < v.xres)
814 v.xres = v.xres_virtual;
815
816 if (v.xoffset > v.xres_virtual - v.xres)
817 v.xoffset = v.xres_virtual - v.xres - 1;
818
819 if (v.yoffset > v.yres_virtual - v.yres)
820 v.yoffset = v.yres_virtual - v.yres - 1;
821
822 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
823 v.transp.offset = v.transp.length =
824 v.transp.msb_right = 0;
825
826 memcpy(var, &v, sizeof(v));
827
828 return 0;
829}
830
831
832static int radeonfb_pan_display (struct fb_var_screeninfo *var,
833 struct fb_info *info)
834{
835 struct radeonfb_info *rinfo = info->par;
836
837 if ((var->xoffset + info->var.xres > info->var.xres_virtual)
838 || (var->yoffset + info->var.yres > info->var.yres_virtual))
839 return -EINVAL;
840
841 if (rinfo->asleep)
842 return 0;
843
844 radeon_fifo_wait(2);
845 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +
846 var->xoffset * info->var.bits_per_pixel / 8) & ~7);
847 return 0;
848}
849
850
851static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
852 unsigned long arg)
853{
854 struct radeonfb_info *rinfo = info->par;
855 unsigned int tmp;
856 u32 value = 0;
857 int rc;
858
859 switch (cmd) {
860
861
862
863
864
865 case FBIO_RADEON_SET_MIRROR:
866 if (!rinfo->is_mobility)
867 return -EINVAL;
868
869 rc = get_user(value, (__u32 __user *)arg);
870
871 if (rc)
872 return rc;
873
874 radeon_fifo_wait(2);
875 if (value & 0x01) {
876 tmp = INREG(LVDS_GEN_CNTL);
877
878 tmp |= (LVDS_ON | LVDS_BLON);
879 } else {
880 tmp = INREG(LVDS_GEN_CNTL);
881
882 tmp &= ~(LVDS_ON | LVDS_BLON);
883 }
884
885 OUTREG(LVDS_GEN_CNTL, tmp);
886
887 if (value & 0x02) {
888 tmp = INREG(CRTC_EXT_CNTL);
889 tmp |= CRTC_CRT_ON;
890
891 mirror = 1;
892 } else {
893 tmp = INREG(CRTC_EXT_CNTL);
894 tmp &= ~CRTC_CRT_ON;
895
896 mirror = 0;
897 }
898
899 OUTREG(CRTC_EXT_CNTL, tmp);
900
901 return 0;
902 case FBIO_RADEON_GET_MIRROR:
903 if (!rinfo->is_mobility)
904 return -EINVAL;
905
906 tmp = INREG(LVDS_GEN_CNTL);
907 if ((LVDS_ON | LVDS_BLON) & tmp)
908 value |= 0x01;
909
910 tmp = INREG(CRTC_EXT_CNTL);
911 if (CRTC_CRT_ON & tmp)
912 value |= 0x02;
913
914 return put_user(value, (__u32 __user *)arg);
915 default:
916 return -EINVAL;
917 }
918
919 return -EINVAL;
920}
921
922
923int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
924{
925 u32 val;
926 u32 tmp_pix_clks;
927 int unblank = 0;
928
929 if (rinfo->lock_blank)
930 return 0;
931
932 radeon_engine_idle();
933
934 val = INREG(CRTC_EXT_CNTL);
935 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
936 CRTC_VSYNC_DIS);
937 switch (blank) {
938 case FB_BLANK_VSYNC_SUSPEND:
939 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
940 break;
941 case FB_BLANK_HSYNC_SUSPEND:
942 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
943 break;
944 case FB_BLANK_POWERDOWN:
945 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
946 CRTC_HSYNC_DIS);
947 break;
948 case FB_BLANK_NORMAL:
949 val |= CRTC_DISPLAY_DIS;
950 break;
951 case FB_BLANK_UNBLANK:
952 default:
953 unblank = 1;
954 }
955 OUTREG(CRTC_EXT_CNTL, val);
956
957
958 switch (rinfo->mon1_type) {
959 case MT_DFP:
960 if (unblank)
961 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
962 ~(FP_FPON | FP_TMDS_EN));
963 else {
964 if (mode_switch || blank == FB_BLANK_NORMAL)
965 break;
966 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
967 }
968 break;
969 case MT_LCD:
970 del_timer_sync(&rinfo->lvds_timer);
971 val = INREG(LVDS_GEN_CNTL);
972 if (unblank) {
973 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
974 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
975 & (LVDS_DIGON | LVDS_BL_MOD_EN));
976 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
977 OUTREG(LVDS_GEN_CNTL, target_val);
978 else if ((val ^ target_val) != 0) {
979 OUTREG(LVDS_GEN_CNTL, target_val
980 & ~(LVDS_ON | LVDS_BL_MOD_EN));
981 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
982 rinfo->init_state.lvds_gen_cntl |=
983 target_val & LVDS_STATE_MASK;
984 if (mode_switch) {
985 radeon_msleep(rinfo->panel_info.pwr_delay);
986 OUTREG(LVDS_GEN_CNTL, target_val);
987 }
988 else {
989 rinfo->pending_lvds_gen_cntl = target_val;
990 mod_timer(&rinfo->lvds_timer,
991 jiffies +
992 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
993 }
994 }
995 } else {
996 val |= LVDS_DISPLAY_DIS;
997 OUTREG(LVDS_GEN_CNTL, val);
998
999
1000 if (mode_switch || blank == FB_BLANK_NORMAL)
1001 break;
1002
1003
1004
1005
1006 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1007 if (rinfo->is_mobility || rinfo->is_IGP)
1008 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1009 val &= ~(LVDS_BL_MOD_EN);
1010 OUTREG(LVDS_GEN_CNTL, val);
1011 udelay(100);
1012 val &= ~(LVDS_ON | LVDS_EN);
1013 OUTREG(LVDS_GEN_CNTL, val);
1014 val &= ~LVDS_DIGON;
1015 rinfo->pending_lvds_gen_cntl = val;
1016 mod_timer(&rinfo->lvds_timer,
1017 jiffies +
1018 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1019 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1020 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1021 if (rinfo->is_mobility || rinfo->is_IGP)
1022 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1023 }
1024 break;
1025 case MT_CRT:
1026
1027 default:
1028 break;
1029 }
1030
1031 return 0;
1032}
1033
1034static int radeonfb_blank (int blank, struct fb_info *info)
1035{
1036 struct radeonfb_info *rinfo = info->par;
1037
1038 if (rinfo->asleep)
1039 return 0;
1040
1041 return radeon_screen_blank(rinfo, blank, 0);
1042}
1043
1044static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1045 unsigned blue, unsigned transp,
1046 struct radeonfb_info *rinfo)
1047{
1048 u32 pindex;
1049 unsigned int i;
1050
1051
1052 if (regno > 255)
1053 return -EINVAL;
1054
1055 red >>= 8;
1056 green >>= 8;
1057 blue >>= 8;
1058 rinfo->palette[regno].red = red;
1059 rinfo->palette[regno].green = green;
1060 rinfo->palette[regno].blue = blue;
1061
1062
1063 pindex = regno;
1064
1065 if (!rinfo->asleep) {
1066 radeon_fifo_wait(9);
1067
1068 if (rinfo->bpp == 16) {
1069 pindex = regno * 8;
1070
1071 if (rinfo->depth == 16 && regno > 63)
1072 return -EINVAL;
1073 if (rinfo->depth == 15 && regno > 31)
1074 return -EINVAL;
1075
1076
1077
1078
1079 if (rinfo->depth == 16) {
1080 OUTREG(PALETTE_INDEX, pindex>>1);
1081 OUTREG(PALETTE_DATA,
1082 (rinfo->palette[regno>>1].red << 16) |
1083 (green << 8) |
1084 (rinfo->palette[regno>>1].blue));
1085 green = rinfo->palette[regno<<1].green;
1086 }
1087 }
1088
1089 if (rinfo->depth != 16 || regno < 32) {
1090 OUTREG(PALETTE_INDEX, pindex);
1091 OUTREG(PALETTE_DATA, (red << 16) |
1092 (green << 8) | blue);
1093 }
1094 }
1095 if (regno < 16) {
1096 u32 *pal = rinfo->info->pseudo_palette;
1097 switch (rinfo->depth) {
1098 case 15:
1099 pal[regno] = (regno << 10) | (regno << 5) | regno;
1100 break;
1101 case 16:
1102 pal[regno] = (regno << 11) | (regno << 5) | regno;
1103 break;
1104 case 24:
1105 pal[regno] = (regno << 16) | (regno << 8) | regno;
1106 break;
1107 case 32:
1108 i = (regno << 8) | regno;
1109 pal[regno] = (i << 16) | i;
1110 break;
1111 }
1112 }
1113 return 0;
1114}
1115
1116static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1117 unsigned blue, unsigned transp,
1118 struct fb_info *info)
1119{
1120 struct radeonfb_info *rinfo = info->par;
1121 u32 dac_cntl2, vclk_cntl = 0;
1122 int rc;
1123
1124 if (!rinfo->asleep) {
1125 if (rinfo->is_mobility) {
1126 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1127 OUTPLL(VCLK_ECP_CNTL,
1128 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1129 }
1130
1131
1132 if (rinfo->has_CRTC2) {
1133 dac_cntl2 = INREG(DAC_CNTL2);
1134 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1135 OUTREG(DAC_CNTL2, dac_cntl2);
1136 }
1137 }
1138
1139 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1140
1141 if (!rinfo->asleep && rinfo->is_mobility)
1142 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1143
1144 return rc;
1145}
1146
1147static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1148{
1149 struct radeonfb_info *rinfo = info->par;
1150 u16 *red, *green, *blue, *transp;
1151 u32 dac_cntl2, vclk_cntl = 0;
1152 int i, start, rc = 0;
1153
1154 if (!rinfo->asleep) {
1155 if (rinfo->is_mobility) {
1156 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1157 OUTPLL(VCLK_ECP_CNTL,
1158 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1159 }
1160
1161
1162 if (rinfo->has_CRTC2) {
1163 dac_cntl2 = INREG(DAC_CNTL2);
1164 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1165 OUTREG(DAC_CNTL2, dac_cntl2);
1166 }
1167 }
1168
1169 red = cmap->red;
1170 green = cmap->green;
1171 blue = cmap->blue;
1172 transp = cmap->transp;
1173 start = cmap->start;
1174
1175 for (i = 0; i < cmap->len; i++) {
1176 u_int hred, hgreen, hblue, htransp = 0xffff;
1177
1178 hred = *red++;
1179 hgreen = *green++;
1180 hblue = *blue++;
1181 if (transp)
1182 htransp = *transp++;
1183 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1184 rinfo);
1185 if (rc)
1186 break;
1187 }
1188
1189 if (!rinfo->asleep && rinfo->is_mobility)
1190 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1191
1192 return rc;
1193}
1194
1195static void radeon_save_state (struct radeonfb_info *rinfo,
1196 struct radeon_regs *save)
1197{
1198
1199 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1200 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1201 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1202 save->dac_cntl = INREG(DAC_CNTL);
1203 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1204 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1205 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1206 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1207 save->crtc_pitch = INREG(CRTC_PITCH);
1208 save->surface_cntl = INREG(SURFACE_CNTL);
1209
1210
1211 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1212 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1213 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1214 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1215 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1216 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1217 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1218 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1219 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1220 save->tmds_crc = INREG(TMDS_CRC);
1221 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1222 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1223
1224
1225 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1226 radeon_pll_errata_after_index(rinfo);
1227 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1228 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1229}
1230
1231
1232static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1233{
1234 int i;
1235
1236 radeon_fifo_wait(20);
1237
1238
1239 if (rinfo->is_mobility) {
1240
1241
1242
1243
1244
1245
1246
1247 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1248 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1249 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1250
1251
1252
1253 OUTREGP(CLOCK_CNTL_INDEX,
1254 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1255 ~PPLL_DIV_SEL_MASK);
1256 radeon_pll_errata_after_index(rinfo);
1257 radeon_pll_errata_after_data(rinfo);
1258 return;
1259 }
1260 }
1261
1262
1263 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1264
1265
1266 OUTPLLP(PPLL_CNTL,
1267 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1268 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1269
1270
1271 OUTREGP(CLOCK_CNTL_INDEX,
1272 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1273 ~PPLL_DIV_SEL_MASK);
1274 radeon_pll_errata_after_index(rinfo);
1275 radeon_pll_errata_after_data(rinfo);
1276
1277
1278 if (IS_R300_VARIANT(rinfo) ||
1279 rinfo->family == CHIP_FAMILY_RS300 ||
1280 rinfo->family == CHIP_FAMILY_RS400 ||
1281 rinfo->family == CHIP_FAMILY_RS480) {
1282 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1283
1284
1285
1286 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1287 } else {
1288
1289 OUTPLLP(PPLL_REF_DIV,
1290 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1291 ~R300_PPLL_REF_DIV_ACC_MASK);
1292 }
1293 } else
1294 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1295
1296
1297 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1298 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1299
1300
1301 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1302 ;
1303 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1304
1305
1306
1307
1308
1309
1310 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1311 ;
1312
1313 OUTPLL(HTOTAL_CNTL, 0);
1314
1315
1316 OUTPLLP(PPLL_CNTL, 0,
1317 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1318
1319
1320 radeon_msleep(5);
1321
1322
1323 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1324}
1325
1326
1327
1328
1329static void radeon_lvds_timer_func(unsigned long data)
1330{
1331 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1332
1333 radeon_engine_idle();
1334
1335 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1336}
1337
1338
1339
1340
1341
1342void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1343 int regs_only)
1344{
1345 int i;
1346 int primary_mon = PRIMARY_MONITOR(rinfo);
1347
1348 if (nomodeset)
1349 return;
1350
1351 if (!regs_only)
1352 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1353
1354 radeon_fifo_wait(31);
1355 for (i=0; i<10; i++)
1356 OUTREG(common_regs[i].reg, common_regs[i].val);
1357
1358
1359 for (i=0; i<8; i++) {
1360 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1361 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1362 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1363 }
1364
1365 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1366 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1367 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1368 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1369 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1370 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1371 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1372 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1373 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1374 OUTREG(CRTC_OFFSET, 0);
1375 OUTREG(CRTC_OFFSET_CNTL, 0);
1376 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1377 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1378
1379 radeon_write_pll_regs(rinfo, mode);
1380
1381 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1382 radeon_fifo_wait(10);
1383 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1384 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1385 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1386 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1387 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1388 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1389 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1390 OUTREG(TMDS_CRC, mode->tmds_crc);
1391 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1392 }
1393
1394 if (!regs_only)
1395 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1396
1397 radeon_fifo_wait(2);
1398 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1399
1400 return;
1401}
1402
1403
1404
1405
1406static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1407 unsigned long freq)
1408{
1409 const struct {
1410 int divider;
1411 int bitvalue;
1412 } *post_div,
1413 post_divs[] = {
1414 { 1, 0 },
1415 { 2, 1 },
1416 { 4, 2 },
1417 { 8, 3 },
1418 { 3, 4 },
1419 { 16, 5 },
1420 { 6, 6 },
1421 { 12, 7 },
1422 { 0, 0 },
1423 };
1424 int fb_div, pll_output_freq = 0;
1425 int uses_dvo = 0;
1426
1427
1428
1429
1430
1431#if 1
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441 while (rinfo->has_CRTC2) {
1442 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1443 u32 disp_output_cntl;
1444 int source;
1445
1446
1447 if ((fp2_gen_cntl & FP2_ON) == 0)
1448 break;
1449
1450
1451
1452 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1453 source = (fp2_gen_cntl >> 10) & 0x3;
1454
1455
1456
1457 if (source == 3) {
1458 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1459 source = (disp_output_cntl >> 12) & 0x3;
1460 }
1461 } else
1462 source = (fp2_gen_cntl >> 13) & 0x1;
1463
1464 if (source == 1)
1465 break;
1466
1467
1468 uses_dvo = 1;
1469 break;
1470 }
1471#else
1472 uses_dvo = 1;
1473#endif
1474 if (freq > rinfo->pll.ppll_max)
1475 freq = rinfo->pll.ppll_max;
1476 if (freq*12 < rinfo->pll.ppll_min)
1477 freq = rinfo->pll.ppll_min / 12;
1478 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1479 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1480
1481 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1482 pll_output_freq = post_div->divider * freq;
1483
1484
1485
1486 if (uses_dvo && (post_div->divider & 1))
1487 continue;
1488 if (pll_output_freq >= rinfo->pll.ppll_min &&
1489 pll_output_freq <= rinfo->pll.ppll_max)
1490 break;
1491 }
1492
1493
1494
1495 if ( !post_div->divider ) {
1496 post_div = &post_divs[post_div->bitvalue];
1497 pll_output_freq = post_div->divider * freq;
1498 }
1499 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1500 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1501 pll_output_freq);
1502
1503
1504
1505 if ( !post_div->divider ) {
1506 post_div = &post_divs[post_div->bitvalue];
1507 pll_output_freq = post_div->divider * freq;
1508 }
1509 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1510 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1511 pll_output_freq);
1512
1513 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1514 rinfo->pll.ref_clk);
1515 regs->ppll_ref_div = rinfo->pll.ref_div;
1516 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1517
1518 pr_debug("post div = 0x%x\n", post_div->bitvalue);
1519 pr_debug("fb_div = 0x%x\n", fb_div);
1520 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1521}
1522
1523static int radeonfb_set_par(struct fb_info *info)
1524{
1525 struct radeonfb_info *rinfo = info->par;
1526 struct fb_var_screeninfo *mode = &info->var;
1527 struct radeon_regs *newmode;
1528 int hTotal, vTotal, hSyncStart, hSyncEnd,
1529 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1530 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1531 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1532 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1533 int i, freq;
1534 int format = 0;
1535 int nopllcalc = 0;
1536 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1537 int primary_mon = PRIMARY_MONITOR(rinfo);
1538 int depth = var_to_depth(mode);
1539 int use_rmx = 0;
1540
1541 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1542 if (!newmode)
1543 return -ENOMEM;
1544
1545
1546
1547
1548 radeon_engine_idle();
1549
1550 hSyncStart = mode->xres + mode->right_margin;
1551 hSyncEnd = hSyncStart + mode->hsync_len;
1552 hTotal = hSyncEnd + mode->left_margin;
1553
1554 vSyncStart = mode->yres + mode->lower_margin;
1555 vSyncEnd = vSyncStart + mode->vsync_len;
1556 vTotal = vSyncEnd + mode->upper_margin;
1557 pixClock = mode->pixclock;
1558
1559 sync = mode->sync;
1560 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1561 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1562
1563 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1564 if (rinfo->panel_info.xres < mode->xres)
1565 mode->xres = rinfo->panel_info.xres;
1566 if (rinfo->panel_info.yres < mode->yres)
1567 mode->yres = rinfo->panel_info.yres;
1568
1569 hTotal = mode->xres + rinfo->panel_info.hblank;
1570 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1571 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1572
1573 vTotal = mode->yres + rinfo->panel_info.vblank;
1574 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1575 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1576
1577 h_sync_pol = !rinfo->panel_info.hAct_high;
1578 v_sync_pol = !rinfo->panel_info.vAct_high;
1579
1580 pixClock = 100000000 / rinfo->panel_info.clock;
1581
1582 if (rinfo->panel_info.use_bios_dividers) {
1583 nopllcalc = 1;
1584 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1585 (rinfo->panel_info.post_divider << 16);
1586 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1587 }
1588 }
1589 dotClock = 1000000000 / pixClock;
1590 freq = dotClock / 10;
1591
1592 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1593 hSyncStart, hSyncEnd, hTotal);
1594 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1595 vSyncStart, vSyncEnd, vTotal);
1596
1597 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1598 vsync_wid = vSyncEnd - vSyncStart;
1599 if (hsync_wid == 0)
1600 hsync_wid = 1;
1601 else if (hsync_wid > 0x3f)
1602 hsync_wid = 0x3f;
1603
1604 if (vsync_wid == 0)
1605 vsync_wid = 1;
1606 else if (vsync_wid > 0x1f)
1607 vsync_wid = 0x1f;
1608
1609 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1610 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1611
1612 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1613
1614 format = radeon_get_dstbpp(depth);
1615 bytpp = mode->bits_per_pixel >> 3;
1616
1617 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1618 hsync_fudge = hsync_fudge_fp[format-1];
1619 else
1620 hsync_fudge = hsync_adj_tab[format-1];
1621
1622 hsync_start = hSyncStart - 8 + hsync_fudge;
1623
1624 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1625 (format << 8);
1626
1627
1628 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1629 newmode->crtc_more_cntl &= 0xfffffff0;
1630
1631 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1632 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1633 if (mirror)
1634 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1635
1636 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1637 CRTC_INTERLACE_EN);
1638 } else {
1639 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1640 CRTC_CRT_ON;
1641 }
1642
1643 newmode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN |
1644 DAC_8BIT_EN;
1645
1646 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1647 (((mode->xres / 8) - 1) << 16));
1648
1649 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1650 (hsync_wid << 16) | (h_sync_pol << 23));
1651
1652 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1653 ((mode->yres - 1) << 16);
1654
1655 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1656 (vsync_wid << 16) | (v_sync_pol << 23));
1657
1658 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1659
1660 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1661 & ~(0x3f)) >> 6;
1662
1663
1664 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1665 } else
1666 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1667
1668 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1669
1670
1671
1672
1673
1674
1675 newmode->surface_cntl = 0;
1676
1677#if defined(__BIG_ENDIAN)
1678
1679
1680
1681
1682
1683 switch (mode->bits_per_pixel) {
1684 case 16:
1685 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1686 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1687 break;
1688 case 24:
1689 case 32:
1690 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1691 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1692 break;
1693 }
1694#endif
1695
1696
1697 for (i=0; i<8; i++) {
1698 newmode->surf_lower_bound[i] = 0;
1699 newmode->surf_upper_bound[i] = 0x1f;
1700 newmode->surf_info[i] = 0;
1701 }
1702
1703 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1704 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1705 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1706 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1707
1708 rinfo->bpp = mode->bits_per_pixel;
1709 rinfo->depth = depth;
1710
1711 pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1712 pr_debug("freq = %lu\n", (unsigned long)freq);
1713
1714
1715 newmode->clk_cntl_index = 0x300;
1716
1717
1718 if (!nopllcalc)
1719 radeon_calc_pll_regs(rinfo, newmode, freq);
1720
1721 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1722
1723 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1724 unsigned int hRatio, vRatio;
1725
1726 if (mode->xres > rinfo->panel_info.xres)
1727 mode->xres = rinfo->panel_info.xres;
1728 if (mode->yres > rinfo->panel_info.yres)
1729 mode->yres = rinfo->panel_info.yres;
1730
1731 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1732 << HORZ_PANEL_SHIFT);
1733 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1734 << VERT_PANEL_SHIFT);
1735
1736 if (mode->xres != rinfo->panel_info.xres) {
1737 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1738 rinfo->panel_info.xres);
1739 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1740 (newmode->fp_horz_stretch &
1741 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1742 HORZ_AUTO_RATIO_INC)));
1743 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1744 HORZ_STRETCH_ENABLE);
1745 use_rmx = 1;
1746 }
1747 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1748
1749 if (mode->yres != rinfo->panel_info.yres) {
1750 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1751 rinfo->panel_info.yres);
1752 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1753 (newmode->fp_vert_stretch &
1754 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1755 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1756 VERT_STRETCH_ENABLE);
1757 use_rmx = 1;
1758 }
1759 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1760
1761 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1762 ~(FP_SEL_CRTC2 |
1763 FP_RMX_HVSYNC_CONTROL_EN |
1764 FP_DFP_SYNC_SEL |
1765 FP_CRT_SYNC_SEL |
1766 FP_CRTC_LOCK_8DOT |
1767 FP_USE_SHADOW_EN |
1768 FP_CRTC_USE_SHADOW_VEND |
1769 FP_CRT_SYNC_ALT));
1770
1771 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1772 FP_CRTC_DONT_SHADOW_HEND |
1773 FP_PANEL_FORMAT);
1774
1775 if (IS_R300_VARIANT(rinfo) ||
1776 (rinfo->family == CHIP_FAMILY_R200)) {
1777 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1778 if (use_rmx)
1779 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1780 else
1781 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1782 } else
1783 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1784
1785 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1786 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1787 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1788 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1789
1790 if (primary_mon == MT_LCD) {
1791 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1792 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1793 } else {
1794
1795 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1796 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1797
1798 if (IS_R300_VARIANT(rinfo) ||
1799 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1800 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1801 else
1802 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1803 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1804 }
1805
1806 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1807 (((mode->xres / 8) - 1) << 16));
1808 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1809 ((mode->yres - 1) << 16);
1810 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1811 (hsync_wid << 16) | (h_sync_pol << 23));
1812 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1813 (vsync_wid << 16) | (v_sync_pol << 23));
1814 }
1815
1816
1817 if (!rinfo->asleep) {
1818 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1819 radeon_write_mode (rinfo, newmode, 0);
1820
1821 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1822 radeonfb_engine_init (rinfo);
1823 }
1824
1825 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1826 info->fix.line_length = rinfo->pitch*64;
1827 else
1828 info->fix.line_length = mode->xres_virtual
1829 * ((mode->bits_per_pixel + 1) / 8);
1830 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1831 : FB_VISUAL_DIRECTCOLOR;
1832
1833#ifdef CONFIG_BOOTX_TEXT
1834
1835 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1836 rinfo->depth, info->fix.line_length);
1837#endif
1838
1839 kfree(newmode);
1840 return 0;
1841}
1842
1843
1844static struct fb_ops radeonfb_ops = {
1845 .owner = THIS_MODULE,
1846 .fb_check_var = radeonfb_check_var,
1847 .fb_set_par = radeonfb_set_par,
1848 .fb_setcolreg = radeonfb_setcolreg,
1849 .fb_setcmap = radeonfb_setcmap,
1850 .fb_pan_display = radeonfb_pan_display,
1851 .fb_blank = radeonfb_blank,
1852 .fb_ioctl = radeonfb_ioctl,
1853 .fb_sync = radeonfb_sync,
1854 .fb_fillrect = radeonfb_fillrect,
1855 .fb_copyarea = radeonfb_copyarea,
1856 .fb_imageblit = radeonfb_imageblit,
1857};
1858
1859
1860static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
1861{
1862 struct fb_info *info = rinfo->info;
1863
1864 info->par = rinfo;
1865 info->pseudo_palette = rinfo->pseudo_palette;
1866 info->flags = FBINFO_DEFAULT
1867 | FBINFO_HWACCEL_COPYAREA
1868 | FBINFO_HWACCEL_FILLRECT
1869 | FBINFO_HWACCEL_XPAN
1870 | FBINFO_HWACCEL_YPAN;
1871 info->fbops = &radeonfb_ops;
1872 info->screen_base = rinfo->fb_base;
1873 info->screen_size = rinfo->mapped_vram;
1874
1875 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1876 info->fix.smem_start = rinfo->fb_base_phys;
1877 info->fix.smem_len = rinfo->video_ram;
1878 info->fix.type = FB_TYPE_PACKED_PIXELS;
1879 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1880 info->fix.xpanstep = 8;
1881 info->fix.ypanstep = 1;
1882 info->fix.ywrapstep = 0;
1883 info->fix.type_aux = 0;
1884 info->fix.mmio_start = rinfo->mmio_base_phys;
1885 info->fix.mmio_len = RADEON_REGSIZE;
1886 info->fix.accel = FB_ACCEL_ATI_RADEON;
1887
1888 fb_alloc_cmap(&info->cmap, 256, 0);
1889
1890 if (noaccel)
1891 info->flags |= FBINFO_HWACCEL_DISABLED;
1892
1893 return 0;
1894}
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907#ifdef CONFIG_PPC
1908#undef SET_MC_FB_FROM_APERTURE
1909static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1910{
1911 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1912 u32 save_crtc_ext_cntl;
1913 u32 aper_base, aper_size;
1914 u32 agp_base;
1915
1916
1917 if (rinfo->has_CRTC2) {
1918 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1919 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1920 }
1921 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1922 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1923
1924 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1925 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1926 mdelay(100);
1927
1928 aper_base = INREG(CNFG_APER_0_BASE);
1929 aper_size = INREG(CNFG_APER_SIZE);
1930
1931#ifdef SET_MC_FB_FROM_APERTURE
1932
1933 OUTREG(MC_FB_LOCATION,
1934 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1935 rinfo->fb_local_base = aper_base;
1936#else
1937 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1938 rinfo->fb_local_base = 0;
1939#endif
1940 agp_base = aper_base + aper_size;
1941 if (agp_base & 0xf0000000)
1942 agp_base = (aper_base | 0x0fffffff) + 1;
1943
1944
1945
1946
1947
1948#ifdef SET_MC_FB_FROM_APERTURE
1949 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1950#else
1951 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1952#endif
1953
1954
1955
1956
1957#ifdef SET_MC_FB_FROM_APERTURE
1958 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1959 if (rinfo->has_CRTC2)
1960 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1961 OUTREG(OV0_BASE_ADDR, aper_base);
1962#else
1963 OUTREG(DISPLAY_BASE_ADDR, 0);
1964 if (rinfo->has_CRTC2)
1965 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1966 OUTREG(OV0_BASE_ADDR, 0);
1967#endif
1968 mdelay(100);
1969
1970
1971 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1972 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1973 if (rinfo->has_CRTC2)
1974 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1975
1976 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1977 aper_base,
1978 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1979 0xffff0000 | (agp_base >> 16));
1980}
1981#endif
1982
1983
1984static void radeon_identify_vram(struct radeonfb_info *rinfo)
1985{
1986 u32 tmp;
1987
1988
1989 if ((rinfo->family == CHIP_FAMILY_RS100) ||
1990 (rinfo->family == CHIP_FAMILY_RS200) ||
1991 (rinfo->family == CHIP_FAMILY_RS300) ||
1992 (rinfo->family == CHIP_FAMILY_RC410) ||
1993 (rinfo->family == CHIP_FAMILY_RS400) ||
1994 (rinfo->family == CHIP_FAMILY_RS480) ) {
1995 u32 tom = INREG(NB_TOM);
1996 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
1997
1998 radeon_fifo_wait(6);
1999 OUTREG(MC_FB_LOCATION, tom);
2000 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2001 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2002 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2003
2004
2005 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2006
2007 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2008 (rinfo->family == CHIP_FAMILY_RS200)) {
2009
2010
2011
2012 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2013 ~CRTC_H_CUTOFF_ACTIVE_EN);
2014 }
2015 } else {
2016 tmp = INREG(CNFG_MEMSIZE);
2017 }
2018
2019
2020 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
2021
2022
2023
2024
2025
2026 if (rinfo->video_ram == 0) {
2027 switch (rinfo->pdev->device) {
2028 case PCI_CHIP_RADEON_LY:
2029 case PCI_CHIP_RADEON_LZ:
2030 rinfo->video_ram = 8192 * 1024;
2031 break;
2032 default:
2033 break;
2034 }
2035 }
2036
2037
2038
2039
2040
2041 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2042 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2043 rinfo->vram_ddr = 1;
2044 else
2045 rinfo->vram_ddr = 0;
2046
2047 tmp = INREG(MEM_CNTL);
2048 if (IS_R300_VARIANT(rinfo)) {
2049 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2050 switch (tmp) {
2051 case 0: rinfo->vram_width = 64; break;
2052 case 1: rinfo->vram_width = 128; break;
2053 case 2: rinfo->vram_width = 256; break;
2054 default: rinfo->vram_width = 128; break;
2055 }
2056 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2057 (rinfo->family == CHIP_FAMILY_RS100) ||
2058 (rinfo->family == CHIP_FAMILY_RS200)){
2059 if (tmp & RV100_MEM_HALF_MODE)
2060 rinfo->vram_width = 32;
2061 else
2062 rinfo->vram_width = 64;
2063 } else {
2064 if (tmp & MEM_NUM_CHANNELS_MASK)
2065 rinfo->vram_width = 128;
2066 else
2067 rinfo->vram_width = 64;
2068 }
2069
2070
2071
2072
2073
2074 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2075 pci_name(rinfo->pdev),
2076 rinfo->video_ram / 1024,
2077 rinfo->vram_ddr ? "DDR" : "SDRAM",
2078 rinfo->vram_width);
2079}
2080
2081
2082
2083
2084
2085static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2086{
2087 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
2088}
2089
2090
2091static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj,
2092 struct bin_attribute *bin_attr,
2093 char *buf, loff_t off, size_t count)
2094{
2095 struct device *dev = container_of(kobj, struct device, kobj);
2096 struct pci_dev *pdev = to_pci_dev(dev);
2097 struct fb_info *info = pci_get_drvdata(pdev);
2098 struct radeonfb_info *rinfo = info->par;
2099
2100 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2101}
2102
2103
2104static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj,
2105 struct bin_attribute *bin_attr,
2106 char *buf, loff_t off, size_t count)
2107{
2108 struct device *dev = container_of(kobj, struct device, kobj);
2109 struct pci_dev *pdev = to_pci_dev(dev);
2110 struct fb_info *info = pci_get_drvdata(pdev);
2111 struct radeonfb_info *rinfo = info->par;
2112
2113 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2114}
2115
2116static struct bin_attribute edid1_attr = {
2117 .attr = {
2118 .name = "edid1",
2119 .mode = 0444,
2120 },
2121 .size = EDID_LENGTH,
2122 .read = radeon_show_edid1,
2123};
2124
2125static struct bin_attribute edid2_attr = {
2126 .attr = {
2127 .name = "edid2",
2128 .mode = 0444,
2129 },
2130 .size = EDID_LENGTH,
2131 .read = radeon_show_edid2,
2132};
2133
2134
2135static int radeonfb_pci_register(struct pci_dev *pdev,
2136 const struct pci_device_id *ent)
2137{
2138 struct fb_info *info;
2139 struct radeonfb_info *rinfo;
2140 int ret;
2141 unsigned char c1, c2;
2142 int err = 0;
2143
2144 pr_debug("radeonfb_pci_register BEGIN\n");
2145
2146
2147 ret = pci_enable_device(pdev);
2148 if (ret < 0) {
2149 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2150 pci_name(pdev));
2151 goto err_out;
2152 }
2153
2154 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2155 if (!info) {
2156 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2157 pci_name(pdev));
2158 ret = -ENOMEM;
2159 goto err_disable;
2160 }
2161 rinfo = info->par;
2162 rinfo->info = info;
2163 rinfo->pdev = pdev;
2164
2165 spin_lock_init(&rinfo->reg_lock);
2166 init_timer(&rinfo->lvds_timer);
2167 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2168 rinfo->lvds_timer.data = (unsigned long)rinfo;
2169
2170 c1 = ent->device >> 8;
2171 c2 = ent->device & 0xff;
2172 if (isprint(c1) && isprint(c2))
2173 snprintf(rinfo->name, sizeof(rinfo->name),
2174 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2175 else
2176 snprintf(rinfo->name, sizeof(rinfo->name),
2177 "ATI Radeon %x", ent->device & 0xffff);
2178
2179 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2180 rinfo->chipset = pdev->device;
2181 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2182 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2183 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2184
2185
2186 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2187 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2188
2189
2190 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2191 if (ret < 0) {
2192 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2193 pci_name(rinfo->pdev));
2194 goto err_release_fb;
2195 }
2196
2197 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2198 if (ret < 0) {
2199 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2200 pci_name(rinfo->pdev));
2201 goto err_release_pci0;
2202 }
2203
2204
2205 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2206 if (!rinfo->mmio_base) {
2207 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2208 pci_name(rinfo->pdev));
2209 ret = -EIO;
2210 goto err_release_pci2;
2211 }
2212
2213 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2214
2215
2216
2217
2218 rinfo->errata = 0;
2219 if (rinfo->family == CHIP_FAMILY_R300 &&
2220 (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
2221 == CFG_ATI_REV_A11)
2222 rinfo->errata |= CHIP_ERRATA_R300_CG;
2223
2224 if (rinfo->family == CHIP_FAMILY_RV200 ||
2225 rinfo->family == CHIP_FAMILY_RS200)
2226 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2227
2228 if (rinfo->family == CHIP_FAMILY_RV100 ||
2229 rinfo->family == CHIP_FAMILY_RS100 ||
2230 rinfo->family == CHIP_FAMILY_RS200)
2231 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2232
2233#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
2234
2235
2236
2237 rinfo->of_node = pci_device_to_OF_node(pdev);
2238 if (rinfo->of_node == NULL)
2239 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2240 pci_name(rinfo->pdev));
2241
2242#endif
2243#ifdef CONFIG_PPC
2244
2245
2246
2247
2248 fixup_memory_mappings(rinfo);
2249#endif
2250
2251
2252 radeon_identify_vram(rinfo);
2253
2254 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2255
2256 do {
2257 rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys,
2258 rinfo->mapped_vram);
2259 } while (rinfo->fb_base == NULL &&
2260 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2261
2262 if (rinfo->fb_base == NULL) {
2263 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2264 pci_name(rinfo->pdev));
2265 ret = -EIO;
2266 goto err_unmap_rom;
2267 }
2268
2269 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2270 rinfo->mapped_vram/1024);
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283 if (!rinfo->is_mobility)
2284 radeon_map_ROM(rinfo, pdev);
2285
2286
2287
2288
2289
2290
2291
2292#ifdef CONFIG_X86
2293 if (rinfo->bios_seg == NULL)
2294 radeon_find_mem_vbios(rinfo);
2295#endif
2296
2297
2298
2299
2300 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2301 radeon_map_ROM(rinfo, pdev);
2302
2303
2304 radeon_get_pllinfo(rinfo);
2305
2306#ifdef CONFIG_FB_RADEON_I2C
2307
2308 radeon_create_i2c_busses(rinfo);
2309#endif
2310
2311
2312 radeon_set_fbinfo (rinfo);
2313
2314
2315 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2316
2317
2318 radeon_check_modes(rinfo, mode_option);
2319
2320
2321 if (rinfo->mon1_EDID)
2322 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2323 &edid1_attr);
2324 if (rinfo->mon2_EDID)
2325 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2326 &edid2_attr);
2327 if (err)
2328 pr_warning("%s() Creating sysfs files failed, continuing\n",
2329 __func__);
2330
2331
2332
2333
2334 radeon_save_state (rinfo, &rinfo->init_state);
2335 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2336
2337
2338 if (default_dynclk < -1) {
2339
2340
2341
2342 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2343 } else
2344 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2345
2346 pci_set_drvdata(pdev, info);
2347
2348
2349 ret = register_framebuffer(info);
2350 if (ret < 0) {
2351 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2352 pci_name(rinfo->pdev));
2353 goto err_unmap_fb;
2354 }
2355
2356 if (!nomtrr)
2357 rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys,
2358 rinfo->video_ram);
2359
2360 if (backlight)
2361 radeonfb_bl_init(rinfo);
2362
2363 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2364
2365 if (rinfo->bios_seg)
2366 radeon_unmap_ROM(rinfo, pdev);
2367 pr_debug("radeonfb_pci_register END\n");
2368
2369 return 0;
2370err_unmap_fb:
2371 iounmap(rinfo->fb_base);
2372err_unmap_rom:
2373 kfree(rinfo->mon1_EDID);
2374 kfree(rinfo->mon2_EDID);
2375 if (rinfo->mon1_modedb)
2376 fb_destroy_modedb(rinfo->mon1_modedb);
2377 fb_dealloc_cmap(&info->cmap);
2378#ifdef CONFIG_FB_RADEON_I2C
2379 radeon_delete_i2c_busses(rinfo);
2380#endif
2381 if (rinfo->bios_seg)
2382 radeon_unmap_ROM(rinfo, pdev);
2383 iounmap(rinfo->mmio_base);
2384err_release_pci2:
2385 pci_release_region(pdev, 2);
2386err_release_pci0:
2387 pci_release_region(pdev, 0);
2388err_release_fb:
2389 framebuffer_release(info);
2390err_disable:
2391err_out:
2392 return ret;
2393}
2394
2395
2396
2397static void radeonfb_pci_unregister(struct pci_dev *pdev)
2398{
2399 struct fb_info *info = pci_get_drvdata(pdev);
2400 struct radeonfb_info *rinfo = info->par;
2401
2402 if (!rinfo)
2403 return;
2404
2405 radeonfb_pm_exit(rinfo);
2406
2407 if (rinfo->mon1_EDID)
2408 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2409 if (rinfo->mon2_EDID)
2410 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2411
2412#if 0
2413
2414
2415
2416
2417
2418
2419 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2420 #endif
2421
2422 del_timer_sync(&rinfo->lvds_timer);
2423 arch_phys_wc_del(rinfo->wc_cookie);
2424 unregister_framebuffer(info);
2425
2426 radeonfb_bl_exit(rinfo);
2427
2428 iounmap(rinfo->mmio_base);
2429 iounmap(rinfo->fb_base);
2430
2431 pci_release_region(pdev, 2);
2432 pci_release_region(pdev, 0);
2433
2434 kfree(rinfo->mon1_EDID);
2435 kfree(rinfo->mon2_EDID);
2436 if (rinfo->mon1_modedb)
2437 fb_destroy_modedb(rinfo->mon1_modedb);
2438#ifdef CONFIG_FB_RADEON_I2C
2439 radeon_delete_i2c_busses(rinfo);
2440#endif
2441 fb_dealloc_cmap(&info->cmap);
2442 framebuffer_release(info);
2443}
2444
2445
2446static struct pci_driver radeonfb_driver = {
2447 .name = "radeonfb",
2448 .id_table = radeonfb_pci_table,
2449 .probe = radeonfb_pci_register,
2450 .remove = radeonfb_pci_unregister,
2451#ifdef CONFIG_PM
2452 .suspend = radeonfb_pci_suspend,
2453 .resume = radeonfb_pci_resume,
2454#endif
2455};
2456
2457#ifndef MODULE
2458static int __init radeonfb_setup (char *options)
2459{
2460 char *this_opt;
2461
2462 if (!options || !*options)
2463 return 0;
2464
2465 while ((this_opt = strsep (&options, ",")) != NULL) {
2466 if (!*this_opt)
2467 continue;
2468
2469 if (!strncmp(this_opt, "noaccel", 7)) {
2470 noaccel = 1;
2471 } else if (!strncmp(this_opt, "mirror", 6)) {
2472 mirror = 1;
2473 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2474 force_dfp = 1;
2475 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2476 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2477 } else if (!strncmp(this_opt, "backlight:", 10)) {
2478 backlight = simple_strtoul(this_opt+10, NULL, 0);
2479 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2480 nomtrr = 1;
2481 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2482 nomodeset = 1;
2483 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2484 force_measure_pll = 1;
2485 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2486 ignore_edid = 1;
2487#if defined(CONFIG_PM) && defined(CONFIG_X86)
2488 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2489 force_sleep = 1;
2490 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2491 ignore_devlist = 1;
2492#endif
2493 } else
2494 mode_option = this_opt;
2495 }
2496 return 0;
2497}
2498#endif
2499
2500static int __init radeonfb_init (void)
2501{
2502#ifndef MODULE
2503 char *option = NULL;
2504
2505 if (fb_get_options("radeonfb", &option))
2506 return -ENODEV;
2507 radeonfb_setup(option);
2508#endif
2509 return pci_register_driver (&radeonfb_driver);
2510}
2511
2512
2513static void __exit radeonfb_exit (void)
2514{
2515 pci_unregister_driver (&radeonfb_driver);
2516}
2517
2518module_init(radeonfb_init);
2519module_exit(radeonfb_exit);
2520
2521MODULE_AUTHOR("Ani Joshi");
2522MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2523MODULE_LICENSE("GPL");
2524module_param(noaccel, bool, 0);
2525module_param(default_dynclk, int, 0);
2526MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2527MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2528module_param(nomodeset, bool, 0);
2529MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2530module_param(mirror, bool, 0);
2531MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2532module_param(force_dfp, bool, 0);
2533MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2534module_param(ignore_edid, bool, 0);
2535MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2536module_param(monitor_layout, charp, 0);
2537MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2538module_param(force_measure_pll, bool, 0);
2539MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2540module_param(nomtrr, bool, 0);
2541MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2542module_param(panel_yres, int, 0);
2543MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2544module_param(mode_option, charp, 0);
2545MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2546#if defined(CONFIG_PM) && defined(CONFIG_X86)
2547module_param(force_sleep, bool, 0);
2548MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2549module_param(ignore_devlist, bool, 0);
2550MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2551#endif
2552
