1/* 2 * i2c-bfin-twi.h - interface to ADI TWI controller 3 * 4 * Copyright 2005-2014 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9#ifndef __I2C_BFIN_TWI_H__ 10#define __I2C_BFIN_TWI_H__ 11 12#include <linux/types.h> 13#include <linux/i2c.h> 14 15/* 16 * ADI twi registers layout 17 */ 18struct bfin_twi_regs { 19 u16 clkdiv; 20 u16 dummy1; 21 u16 control; 22 u16 dummy2; 23 u16 slave_ctl; 24 u16 dummy3; 25 u16 slave_stat; 26 u16 dummy4; 27 u16 slave_addr; 28 u16 dummy5; 29 u16 master_ctl; 30 u16 dummy6; 31 u16 master_stat; 32 u16 dummy7; 33 u16 master_addr; 34 u16 dummy8; 35 u16 int_stat; 36 u16 dummy9; 37 u16 int_mask; 38 u16 dummy10; 39 u16 fifo_ctl; 40 u16 dummy11; 41 u16 fifo_stat; 42 u16 dummy12; 43 u32 __pad[20]; 44 u16 xmt_data8; 45 u16 dummy13; 46 u16 xmt_data16; 47 u16 dummy14; 48 u16 rcv_data8; 49 u16 dummy15; 50 u16 rcv_data16; 51 u16 dummy16; 52}; 53 54struct bfin_twi_iface { 55 int irq; 56 spinlock_t lock; 57 char read_write; 58 u8 command; 59 u8 *transPtr; 60 int readNum; 61 int writeNum; 62 int cur_mode; 63 int manual_stop; 64 int result; 65 struct i2c_adapter adap; 66 struct completion complete; 67 struct i2c_msg *pmsg; 68 int msg_num; 69 int cur_msg; 70 u16 saved_clkdiv; 71 u16 saved_control; 72 struct bfin_twi_regs __iomem *regs_base; 73}; 74 75/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/ 76/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ 77#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ 78#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ 79 80/* TWI_PRESCALE Masks */ 81#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ 82#define TWI_ENA 0x0080 /* TWI Enable */ 83#define SCCB 0x0200 /* SCCB Compatibility Enable */ 84 85/* TWI_SLAVE_CTL Masks */ 86#define SEN 0x0001 /* Slave Enable */ 87#define SADD_LEN 0x0002 /* Slave Address Length */ 88#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 89#define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */ 90#define GEN 0x0010 /* General Call Address Matching Enabled */ 91 92/* TWI_SLAVE_STAT Masks */ 93#define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */ 94#define GCALL 0x0002 /* General Call Indicator */ 95 96/* TWI_MASTER_CTL Masks */ 97#define MEN 0x0001 /* Master Mode Enable */ 98#define MADD_LEN 0x0002 /* Master Address Length */ 99#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 100#define FAST 0x0008 /* Use Fast Mode Timing Specs */ 101#define STOP 0x0010 /* Issue Stop Condition */ 102#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ 103#define DCNT 0x3FC0 /* Data Bytes To Transfer */ 104#define SDAOVR 0x4000 /* Serial Data Override */ 105#define SCLOVR 0x8000 /* Serial Clock Override */ 106 107/* TWI_MASTER_STAT Masks */ 108#define MPROG 0x0001 /* Master Transfer In Progress */ 109#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ 110#define ANAK 0x0004 /* Address Not Acknowledged */ 111#define DNAK 0x0008 /* Data Not Acknowledged */ 112#define BUFRDERR 0x0010 /* Buffer Read Error */ 113#define BUFWRERR 0x0020 /* Buffer Write Error */ 114#define SDASEN 0x0040 /* Serial Data Sense */ 115#define SCLSEN 0x0080 /* Serial Clock Sense */ 116#define BUSBUSY 0x0100 /* Bus Busy Indicator */ 117 118/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ 119#define SINIT 0x0001 /* Slave Transfer Initiated */ 120#define SCOMP 0x0002 /* Slave Transfer Complete */ 121#define SERR 0x0004 /* Slave Transfer Error */ 122#define SOVF 0x0008 /* Slave Overflow */ 123#define MCOMP 0x0010 /* Master Transfer Complete */ 124#define MERR 0x0020 /* Master Transfer Error */ 125#define XMTSERV 0x0040 /* Transmit FIFO Service */ 126#define RCVSERV 0x0080 /* Receive FIFO Service */ 127 128/* TWI_FIFO_CTRL Masks */ 129#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ 130#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ 131#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ 132#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ 133 134/* TWI_FIFO_STAT Masks */ 135#define XMTSTAT 0x0003 /* Transmit FIFO Status */ 136#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ 137#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ 138#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ 139 140#define RCVSTAT 0x000C /* Receive FIFO Status */ 141#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ 142#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 143#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 144 145#endif 146