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8#ifndef __MACH_PRCMU_H
9#define __MACH_PRCMU_H
10
11#include <linux/interrupt.h>
12#include <linux/notifier.h>
13#include <linux/err.h>
14
15#include <dt-bindings/mfd/dbx500-prcmu.h>
16
17
18#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
19#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
20
21
22enum prcmu_wakeup_index {
23 PRCMU_WAKEUP_INDEX_RTC,
24 PRCMU_WAKEUP_INDEX_RTT0,
25 PRCMU_WAKEUP_INDEX_RTT1,
26 PRCMU_WAKEUP_INDEX_HSI0,
27 PRCMU_WAKEUP_INDEX_HSI1,
28 PRCMU_WAKEUP_INDEX_USB,
29 PRCMU_WAKEUP_INDEX_ABB,
30 PRCMU_WAKEUP_INDEX_ABB_FIFO,
31 PRCMU_WAKEUP_INDEX_ARM,
32 PRCMU_WAKEUP_INDEX_CD_IRQ,
33 NUM_PRCMU_WAKEUP_INDICES
34};
35#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
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52
53#define EPOD_ID_SVAMMDSP 0
54#define EPOD_ID_SVAPIPE 1
55#define EPOD_ID_SIAMMDSP 2
56#define EPOD_ID_SIAPIPE 3
57#define EPOD_ID_SGA 4
58#define EPOD_ID_B2R2_MCDE 5
59#define EPOD_ID_ESRAM12 6
60#define EPOD_ID_ESRAM34 7
61#define NUM_EPOD_ID 8
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71
72#define EPOD_STATE_NO_CHANGE 0x00
73#define EPOD_STATE_OFF 0x01
74#define EPOD_STATE_RAMRET 0x02
75#define EPOD_STATE_ON_CLK_OFF 0x03
76#define EPOD_STATE_ON 0x04
77
78
79
80
81#define PRCMU_CLKSRC_CLK38M 0x00
82#define PRCMU_CLKSRC_ACLK 0x01
83#define PRCMU_CLKSRC_SYSCLK 0x02
84#define PRCMU_CLKSRC_LCDCLK 0x03
85#define PRCMU_CLKSRC_SDMMCCLK 0x04
86#define PRCMU_CLKSRC_TVCLK 0x05
87#define PRCMU_CLKSRC_TIMCLK 0x06
88#define PRCMU_CLKSRC_CLK009 0x07
89
90#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
91#define PRCMU_CLKSRC_I2CCLK 0x41
92#define PRCMU_CLKSRC_MSP02CLK 0x42
93#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
94#define PRCMU_CLKSRC_HSIRXCLK 0x44
95#define PRCMU_CLKSRC_HSITXCLK 0x45
96#define PRCMU_CLKSRC_ARMCLKFIX 0x46
97#define PRCMU_CLKSRC_HDMICLK 0x47
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104
105enum prcmu_wdog_id {
106 PRCMU_WDOG_ALL = 0x00,
107 PRCMU_WDOG_CPU1 = 0x01,
108 PRCMU_WDOG_CPU2 = 0x02,
109};
110
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118
119enum ape_opp {
120 APE_OPP_INIT = 0x00,
121 APE_NO_CHANGE = 0x01,
122 APE_100_OPP = 0x02,
123 APE_50_OPP = 0x03,
124 APE_50_PARTLY_25_OPP = 0xFF,
125};
126
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136
137enum arm_opp {
138 ARM_OPP_INIT = 0x00,
139 ARM_NO_CHANGE = 0x01,
140 ARM_100_OPP = 0x02,
141 ARM_50_OPP = 0x03,
142 ARM_MAX_OPP = 0x04,
143 ARM_MAX_FREQ100OPP = 0x05,
144 ARM_EXTCLK = 0x07
145};
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152
153enum ddr_opp {
154 DDR_100_OPP = 0x00,
155 DDR_50_OPP = 0x01,
156 DDR_25_OPP = 0x02,
157};
158
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161
162#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
163#define ESRAM0_DEEP_SLEEP_STATE_RET 2
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170
171
172enum ddr_pwrst {
173 DDR_PWR_STATE_UNCHANGED = 0x00,
174 DDR_PWR_STATE_ON = 0x01,
175 DDR_PWR_STATE_OFFLOWLAT = 0x02,
176 DDR_PWR_STATE_OFFHIGHLAT = 0x03
177};
178
179#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
180
181struct prcmu_pdata
182{
183 bool enable_set_ddr_opp;
184 bool enable_ape_opp_100_voltage;
185 struct ab8500_platform_data *ab_platdata;
186 u32 version_offset;
187 u32 legacy_offset;
188 u32 adt_offset;
189};
190
191#define PRCMU_FW_PROJECT_U8500 2
192#define PRCMU_FW_PROJECT_U8400 3
193#define PRCMU_FW_PROJECT_U9500 4
194#define PRCMU_FW_PROJECT_U8500_MBB 5
195#define PRCMU_FW_PROJECT_U8500_C1 6
196#define PRCMU_FW_PROJECT_U8500_C2 7
197#define PRCMU_FW_PROJECT_U8500_C3 8
198#define PRCMU_FW_PROJECT_U8500_C4 9
199#define PRCMU_FW_PROJECT_U9500_MBL 10
200#define PRCMU_FW_PROJECT_U8500_MBL 11
201#define PRCMU_FW_PROJECT_U8500_MBL2 12
202#define PRCMU_FW_PROJECT_U8520 13
203#define PRCMU_FW_PROJECT_U8420 14
204#define PRCMU_FW_PROJECT_A9420 20
205
206#define PRCMU_FW_PROJECT_U9540 32
207
208#define PRCMU_FW_PROJECT_L8540 64
209
210#define PRCMU_FW_PROJECT_L8580 96
211
212#define PRCMU_FW_PROJECT_NAME_LEN 20
213struct prcmu_fw_version {
214 u32 project;
215 u8 api_version;
216 u8 func_version;
217 u8 errata;
218 char project_name[PRCMU_FW_PROJECT_NAME_LEN];
219};
220
221#include <linux/mfd/db8500-prcmu.h>
222
223#if defined(CONFIG_UX500_SOC_DB8500)
224
225static inline void prcmu_early_init(u32 phy_base, u32 size)
226{
227 return db8500_prcmu_early_init(phy_base, size);
228}
229
230static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
231 bool keep_ap_pll)
232{
233 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
234 keep_ap_pll);
235}
236
237static inline u8 prcmu_get_power_state_result(void)
238{
239 return db8500_prcmu_get_power_state_result();
240}
241
242static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
243{
244 return db8500_prcmu_set_epod(epod_id, epod_state);
245}
246
247static inline void prcmu_enable_wakeups(u32 wakeups)
248{
249 db8500_prcmu_enable_wakeups(wakeups);
250}
251
252static inline void prcmu_disable_wakeups(void)
253{
254 prcmu_enable_wakeups(0);
255}
256
257static inline void prcmu_config_abb_event_readout(u32 abb_events)
258{
259 db8500_prcmu_config_abb_event_readout(abb_events);
260}
261
262static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
263{
264 db8500_prcmu_get_abb_event_buffer(buf);
265}
266
267int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
268int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
269int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
270
271int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
272
273static inline int prcmu_request_clock(u8 clock, bool enable)
274{
275 return db8500_prcmu_request_clock(clock, enable);
276}
277
278unsigned long prcmu_clock_rate(u8 clock);
279long prcmu_round_clock_rate(u8 clock, unsigned long rate);
280int prcmu_set_clock_rate(u8 clock, unsigned long rate);
281
282static inline int prcmu_set_ddr_opp(u8 opp)
283{
284 return db8500_prcmu_set_ddr_opp(opp);
285}
286static inline int prcmu_get_ddr_opp(void)
287{
288 return db8500_prcmu_get_ddr_opp();
289}
290
291static inline int prcmu_set_arm_opp(u8 opp)
292{
293 return db8500_prcmu_set_arm_opp(opp);
294}
295
296static inline int prcmu_get_arm_opp(void)
297{
298 return db8500_prcmu_get_arm_opp();
299}
300
301static inline int prcmu_set_ape_opp(u8 opp)
302{
303 return db8500_prcmu_set_ape_opp(opp);
304}
305
306static inline int prcmu_get_ape_opp(void)
307{
308 return db8500_prcmu_get_ape_opp();
309}
310
311static inline int prcmu_request_ape_opp_100_voltage(bool enable)
312{
313 return db8500_prcmu_request_ape_opp_100_voltage(enable);
314}
315
316static inline void prcmu_system_reset(u16 reset_code)
317{
318 return db8500_prcmu_system_reset(reset_code);
319}
320
321static inline u16 prcmu_get_reset_code(void)
322{
323 return db8500_prcmu_get_reset_code();
324}
325
326int prcmu_ac_wake_req(void);
327void prcmu_ac_sleep_req(void);
328static inline void prcmu_modem_reset(void)
329{
330 return db8500_prcmu_modem_reset();
331}
332
333static inline bool prcmu_is_ac_wake_requested(void)
334{
335 return db8500_prcmu_is_ac_wake_requested();
336}
337
338static inline int prcmu_set_display_clocks(void)
339{
340 return db8500_prcmu_set_display_clocks();
341}
342
343static inline int prcmu_disable_dsipll(void)
344{
345 return db8500_prcmu_disable_dsipll();
346}
347
348static inline int prcmu_enable_dsipll(void)
349{
350 return db8500_prcmu_enable_dsipll();
351}
352
353static inline int prcmu_config_esram0_deep_sleep(u8 state)
354{
355 return db8500_prcmu_config_esram0_deep_sleep(state);
356}
357
358static inline int prcmu_config_hotdog(u8 threshold)
359{
360 return db8500_prcmu_config_hotdog(threshold);
361}
362
363static inline int prcmu_config_hotmon(u8 low, u8 high)
364{
365 return db8500_prcmu_config_hotmon(low, high);
366}
367
368static inline int prcmu_start_temp_sense(u16 cycles32k)
369{
370 return db8500_prcmu_start_temp_sense(cycles32k);
371}
372
373static inline int prcmu_stop_temp_sense(void)
374{
375 return db8500_prcmu_stop_temp_sense();
376}
377
378static inline u32 prcmu_read(unsigned int reg)
379{
380 return db8500_prcmu_read(reg);
381}
382
383static inline void prcmu_write(unsigned int reg, u32 value)
384{
385 db8500_prcmu_write(reg, value);
386}
387
388static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
389{
390 db8500_prcmu_write_masked(reg, mask, value);
391}
392
393static inline int prcmu_enable_a9wdog(u8 id)
394{
395 return db8500_prcmu_enable_a9wdog(id);
396}
397
398static inline int prcmu_disable_a9wdog(u8 id)
399{
400 return db8500_prcmu_disable_a9wdog(id);
401}
402
403static inline int prcmu_kick_a9wdog(u8 id)
404{
405 return db8500_prcmu_kick_a9wdog(id);
406}
407
408static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
409{
410 return db8500_prcmu_load_a9wdog(id, timeout);
411}
412
413static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
414{
415 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
416}
417#else
418
419static inline void prcmu_early_init(u32 phy_base, u32 size) {}
420
421static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
422 bool keep_ap_pll)
423{
424 return 0;
425}
426
427static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
428{
429 return 0;
430}
431
432static inline void prcmu_enable_wakeups(u32 wakeups) {}
433
434static inline void prcmu_disable_wakeups(void) {}
435
436static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
437{
438 return -ENOSYS;
439}
440
441static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
442{
443 return -ENOSYS;
444}
445
446static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
447 u8 size)
448{
449 return -ENOSYS;
450}
451
452static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
453{
454 return 0;
455}
456
457static inline int prcmu_request_clock(u8 clock, bool enable)
458{
459 return 0;
460}
461
462static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
463{
464 return 0;
465}
466
467static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
468{
469 return 0;
470}
471
472static inline unsigned long prcmu_clock_rate(u8 clock)
473{
474 return 0;
475}
476
477static inline int prcmu_set_ape_opp(u8 opp)
478{
479 return 0;
480}
481
482static inline int prcmu_get_ape_opp(void)
483{
484 return APE_100_OPP;
485}
486
487static inline int prcmu_request_ape_opp_100_voltage(bool enable)
488{
489 return 0;
490}
491
492static inline int prcmu_set_arm_opp(u8 opp)
493{
494 return 0;
495}
496
497static inline int prcmu_get_arm_opp(void)
498{
499 return ARM_100_OPP;
500}
501
502static inline int prcmu_set_ddr_opp(u8 opp)
503{
504 return 0;
505}
506
507static inline int prcmu_get_ddr_opp(void)
508{
509 return DDR_100_OPP;
510}
511
512static inline void prcmu_system_reset(u16 reset_code) {}
513
514static inline u16 prcmu_get_reset_code(void)
515{
516 return 0;
517}
518
519static inline int prcmu_ac_wake_req(void)
520{
521 return 0;
522}
523
524static inline void prcmu_ac_sleep_req(void) {}
525
526static inline void prcmu_modem_reset(void) {}
527
528static inline bool prcmu_is_ac_wake_requested(void)
529{
530 return false;
531}
532
533static inline int prcmu_set_display_clocks(void)
534{
535 return 0;
536}
537
538static inline int prcmu_disable_dsipll(void)
539{
540 return 0;
541}
542
543static inline int prcmu_enable_dsipll(void)
544{
545 return 0;
546}
547
548static inline int prcmu_config_esram0_deep_sleep(u8 state)
549{
550 return 0;
551}
552
553static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
554
555static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
556{
557 *buf = NULL;
558}
559
560static inline int prcmu_config_hotdog(u8 threshold)
561{
562 return 0;
563}
564
565static inline int prcmu_config_hotmon(u8 low, u8 high)
566{
567 return 0;
568}
569
570static inline int prcmu_start_temp_sense(u16 cycles32k)
571{
572 return 0;
573}
574
575static inline int prcmu_stop_temp_sense(void)
576{
577 return 0;
578}
579
580static inline u32 prcmu_read(unsigned int reg)
581{
582 return 0;
583}
584
585static inline void prcmu_write(unsigned int reg, u32 value) {}
586
587static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
588
589#endif
590
591static inline void prcmu_set(unsigned int reg, u32 bits)
592{
593 prcmu_write_masked(reg, bits, bits);
594}
595
596static inline void prcmu_clear(unsigned int reg, u32 bits)
597{
598 prcmu_write_masked(reg, bits, 0);
599}
600
601
602#define PRCMU_QOS_APE_OPP 1
603#define PRCMU_QOS_DDR_OPP 2
604#define PRCMU_QOS_ARM_OPP 3
605#define PRCMU_QOS_DEFAULT_VALUE -1
606
607#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
608
609unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
610void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
611void prcmu_qos_force_opp(int, s32);
612int prcmu_qos_requirement(int pm_qos_class);
613int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
614int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
615void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
616int prcmu_qos_add_notifier(int prcmu_qos_class,
617 struct notifier_block *notifier);
618int prcmu_qos_remove_notifier(int prcmu_qos_class,
619 struct notifier_block *notifier);
620
621#else
622
623static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
624{
625 return 0;
626}
627
628static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
629
630static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
631
632static inline int prcmu_qos_requirement(int prcmu_qos_class)
633{
634 return 0;
635}
636
637static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
638 char *name, s32 value)
639{
640 return 0;
641}
642
643static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
644 char *name, s32 new_value)
645{
646 return 0;
647}
648
649static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
650{
651}
652
653static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
654 struct notifier_block *notifier)
655{
656 return 0;
657}
658static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
659 struct notifier_block *notifier)
660{
661 return 0;
662}
663
664#endif
665
666#endif
667