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15#ifndef __MFD_WM831X_CORE_H__
16#define __MFD_WM831X_CORE_H__
17
18#include <linux/completion.h>
19#include <linux/interrupt.h>
20#include <linux/irqdomain.h>
21#include <linux/list.h>
22#include <linux/regmap.h>
23#include <linux/mfd/wm831x/auxadc.h>
24
25
26
27
28#define WM831X_RESET_ID 0x00
29#define WM831X_REVISION 0x01
30#define WM831X_PARENT_ID 0x4000
31#define WM831X_SYSVDD_CONTROL 0x4001
32#define WM831X_THERMAL_MONITORING 0x4002
33#define WM831X_POWER_STATE 0x4003
34#define WM831X_WATCHDOG 0x4004
35#define WM831X_ON_PIN_CONTROL 0x4005
36#define WM831X_RESET_CONTROL 0x4006
37#define WM831X_CONTROL_INTERFACE 0x4007
38#define WM831X_SECURITY_KEY 0x4008
39#define WM831X_SOFTWARE_SCRATCH 0x4009
40#define WM831X_OTP_CONTROL 0x400A
41#define WM831X_GPIO_LEVEL 0x400C
42#define WM831X_SYSTEM_STATUS 0x400D
43#define WM831X_ON_SOURCE 0x400E
44#define WM831X_OFF_SOURCE 0x400F
45#define WM831X_SYSTEM_INTERRUPTS 0x4010
46#define WM831X_INTERRUPT_STATUS_1 0x4011
47#define WM831X_INTERRUPT_STATUS_2 0x4012
48#define WM831X_INTERRUPT_STATUS_3 0x4013
49#define WM831X_INTERRUPT_STATUS_4 0x4014
50#define WM831X_INTERRUPT_STATUS_5 0x4015
51#define WM831X_IRQ_CONFIG 0x4017
52#define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
53#define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
54#define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
55#define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
56#define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
57#define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
58#define WM831X_RTC_WRITE_COUNTER 0x4020
59#define WM831X_RTC_TIME_1 0x4021
60#define WM831X_RTC_TIME_2 0x4022
61#define WM831X_RTC_ALARM_1 0x4023
62#define WM831X_RTC_ALARM_2 0x4024
63#define WM831X_RTC_CONTROL 0x4025
64#define WM831X_RTC_TRIM 0x4026
65#define WM831X_TOUCH_CONTROL_1 0x4028
66#define WM831X_TOUCH_CONTROL_2 0x4029
67#define WM831X_TOUCH_DATA_X 0x402A
68#define WM831X_TOUCH_DATA_Y 0x402B
69#define WM831X_TOUCH_DATA_Z 0x402C
70#define WM831X_AUXADC_DATA 0x402D
71#define WM831X_AUXADC_CONTROL 0x402E
72#define WM831X_AUXADC_SOURCE 0x402F
73#define WM831X_COMPARATOR_CONTROL 0x4030
74#define WM831X_COMPARATOR_1 0x4031
75#define WM831X_COMPARATOR_2 0x4032
76#define WM831X_COMPARATOR_3 0x4033
77#define WM831X_COMPARATOR_4 0x4034
78#define WM831X_GPIO1_CONTROL 0x4038
79#define WM831X_GPIO2_CONTROL 0x4039
80#define WM831X_GPIO3_CONTROL 0x403A
81#define WM831X_GPIO4_CONTROL 0x403B
82#define WM831X_GPIO5_CONTROL 0x403C
83#define WM831X_GPIO6_CONTROL 0x403D
84#define WM831X_GPIO7_CONTROL 0x403E
85#define WM831X_GPIO8_CONTROL 0x403F
86#define WM831X_GPIO9_CONTROL 0x4040
87#define WM831X_GPIO10_CONTROL 0x4041
88#define WM831X_GPIO11_CONTROL 0x4042
89#define WM831X_GPIO12_CONTROL 0x4043
90#define WM831X_GPIO13_CONTROL 0x4044
91#define WM831X_GPIO14_CONTROL 0x4045
92#define WM831X_GPIO15_CONTROL 0x4046
93#define WM831X_GPIO16_CONTROL 0x4047
94#define WM831X_CHARGER_CONTROL_1 0x4048
95#define WM831X_CHARGER_CONTROL_2 0x4049
96#define WM831X_CHARGER_STATUS 0x404A
97#define WM831X_BACKUP_CHARGER_CONTROL 0x404B
98#define WM831X_STATUS_LED_1 0x404C
99#define WM831X_STATUS_LED_2 0x404D
100#define WM831X_CURRENT_SINK_1 0x404E
101#define WM831X_CURRENT_SINK_2 0x404F
102#define WM831X_DCDC_ENABLE 0x4050
103#define WM831X_LDO_ENABLE 0x4051
104#define WM831X_DCDC_STATUS 0x4052
105#define WM831X_LDO_STATUS 0x4053
106#define WM831X_DCDC_UV_STATUS 0x4054
107#define WM831X_LDO_UV_STATUS 0x4055
108#define WM831X_DC1_CONTROL_1 0x4056
109#define WM831X_DC1_CONTROL_2 0x4057
110#define WM831X_DC1_ON_CONFIG 0x4058
111#define WM831X_DC1_SLEEP_CONTROL 0x4059
112#define WM831X_DC1_DVS_CONTROL 0x405A
113#define WM831X_DC2_CONTROL_1 0x405B
114#define WM831X_DC2_CONTROL_2 0x405C
115#define WM831X_DC2_ON_CONFIG 0x405D
116#define WM831X_DC2_SLEEP_CONTROL 0x405E
117#define WM831X_DC2_DVS_CONTROL 0x405F
118#define WM831X_DC3_CONTROL_1 0x4060
119#define WM831X_DC3_CONTROL_2 0x4061
120#define WM831X_DC3_ON_CONFIG 0x4062
121#define WM831X_DC3_SLEEP_CONTROL 0x4063
122#define WM831X_DC4_CONTROL 0x4064
123#define WM831X_DC4_SLEEP_CONTROL 0x4065
124#define WM832X_DC4_SLEEP_CONTROL 0x4067
125#define WM831X_EPE1_CONTROL 0x4066
126#define WM831X_EPE2_CONTROL 0x4067
127#define WM831X_LDO1_CONTROL 0x4068
128#define WM831X_LDO1_ON_CONTROL 0x4069
129#define WM831X_LDO1_SLEEP_CONTROL 0x406A
130#define WM831X_LDO2_CONTROL 0x406B
131#define WM831X_LDO2_ON_CONTROL 0x406C
132#define WM831X_LDO2_SLEEP_CONTROL 0x406D
133#define WM831X_LDO3_CONTROL 0x406E
134#define WM831X_LDO3_ON_CONTROL 0x406F
135#define WM831X_LDO3_SLEEP_CONTROL 0x4070
136#define WM831X_LDO4_CONTROL 0x4071
137#define WM831X_LDO4_ON_CONTROL 0x4072
138#define WM831X_LDO4_SLEEP_CONTROL 0x4073
139#define WM831X_LDO5_CONTROL 0x4074
140#define WM831X_LDO5_ON_CONTROL 0x4075
141#define WM831X_LDO5_SLEEP_CONTROL 0x4076
142#define WM831X_LDO6_CONTROL 0x4077
143#define WM831X_LDO6_ON_CONTROL 0x4078
144#define WM831X_LDO6_SLEEP_CONTROL 0x4079
145#define WM831X_LDO7_CONTROL 0x407A
146#define WM831X_LDO7_ON_CONTROL 0x407B
147#define WM831X_LDO7_SLEEP_CONTROL 0x407C
148#define WM831X_LDO8_CONTROL 0x407D
149#define WM831X_LDO8_ON_CONTROL 0x407E
150#define WM831X_LDO8_SLEEP_CONTROL 0x407F
151#define WM831X_LDO9_CONTROL 0x4080
152#define WM831X_LDO9_ON_CONTROL 0x4081
153#define WM831X_LDO9_SLEEP_CONTROL 0x4082
154#define WM831X_LDO10_CONTROL 0x4083
155#define WM831X_LDO10_ON_CONTROL 0x4084
156#define WM831X_LDO10_SLEEP_CONTROL 0x4085
157#define WM831X_LDO11_ON_CONTROL 0x4087
158#define WM831X_LDO11_SLEEP_CONTROL 0x4088
159#define WM831X_POWER_GOOD_SOURCE_1 0x408E
160#define WM831X_POWER_GOOD_SOURCE_2 0x408F
161#define WM831X_CLOCK_CONTROL_1 0x4090
162#define WM831X_CLOCK_CONTROL_2 0x4091
163#define WM831X_FLL_CONTROL_1 0x4092
164#define WM831X_FLL_CONTROL_2 0x4093
165#define WM831X_FLL_CONTROL_3 0x4094
166#define WM831X_FLL_CONTROL_4 0x4095
167#define WM831X_FLL_CONTROL_5 0x4096
168#define WM831X_UNIQUE_ID_1 0x7800
169#define WM831X_UNIQUE_ID_2 0x7801
170#define WM831X_UNIQUE_ID_3 0x7802
171#define WM831X_UNIQUE_ID_4 0x7803
172#define WM831X_UNIQUE_ID_5 0x7804
173#define WM831X_UNIQUE_ID_6 0x7805
174#define WM831X_UNIQUE_ID_7 0x7806
175#define WM831X_UNIQUE_ID_8 0x7807
176#define WM831X_FACTORY_OTP_ID 0x7808
177#define WM831X_FACTORY_OTP_1 0x7809
178#define WM831X_FACTORY_OTP_2 0x780A
179#define WM831X_FACTORY_OTP_3 0x780B
180#define WM831X_FACTORY_OTP_4 0x780C
181#define WM831X_FACTORY_OTP_5 0x780D
182#define WM831X_CUSTOMER_OTP_ID 0x7810
183#define WM831X_DC1_OTP_CONTROL 0x7811
184#define WM831X_DC2_OTP_CONTROL 0x7812
185#define WM831X_DC3_OTP_CONTROL 0x7813
186#define WM831X_LDO1_2_OTP_CONTROL 0x7814
187#define WM831X_LDO3_4_OTP_CONTROL 0x7815
188#define WM831X_LDO5_6_OTP_CONTROL 0x7816
189#define WM831X_LDO7_8_OTP_CONTROL 0x7817
190#define WM831X_LDO9_10_OTP_CONTROL 0x7818
191#define WM831X_LDO11_EPE_CONTROL 0x7819
192#define WM831X_GPIO1_OTP_CONTROL 0x781A
193#define WM831X_GPIO2_OTP_CONTROL 0x781B
194#define WM831X_GPIO3_OTP_CONTROL 0x781C
195#define WM831X_GPIO4_OTP_CONTROL 0x781D
196#define WM831X_GPIO5_OTP_CONTROL 0x781E
197#define WM831X_GPIO6_OTP_CONTROL 0x781F
198#define WM831X_DBE_CHECK_DATA 0x7827
199
200
201
202
203#define WM831X_CHIP_ID_MASK 0xFFFF
204#define WM831X_CHIP_ID_SHIFT 0
205#define WM831X_CHIP_ID_WIDTH 16
206
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209
210#define WM831X_PARENT_REV_MASK 0xFF00
211#define WM831X_PARENT_REV_SHIFT 8
212#define WM831X_PARENT_REV_WIDTH 8
213#define WM831X_CHILD_REV_MASK 0x00FF
214#define WM831X_CHILD_REV_SHIFT 0
215#define WM831X_CHILD_REV_WIDTH 8
216
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219
220#define WM831X_PARENT_ID_MASK 0xFFFF
221#define WM831X_PARENT_ID_SHIFT 0
222#define WM831X_PARENT_ID_WIDTH 16
223
224
225
226
227#define WM831X_ON_PIN_SECACT_MASK 0x0300
228#define WM831X_ON_PIN_SECACT_SHIFT 8
229#define WM831X_ON_PIN_SECACT_WIDTH 2
230#define WM831X_ON_PIN_PRIMACT_MASK 0x0030
231#define WM831X_ON_PIN_PRIMACT_SHIFT 4
232#define WM831X_ON_PIN_PRIMACT_WIDTH 2
233#define WM831X_ON_PIN_STS 0x0008
234#define WM831X_ON_PIN_STS_MASK 0x0008
235#define WM831X_ON_PIN_STS_SHIFT 3
236#define WM831X_ON_PIN_STS_WIDTH 1
237#define WM831X_ON_PIN_TO_MASK 0x0003
238#define WM831X_ON_PIN_TO_SHIFT 0
239#define WM831X_ON_PIN_TO_WIDTH 2
240
241
242
243
244#define WM831X_CLKOUT_ENA 0x8000
245#define WM831X_CLKOUT_ENA_MASK 0x8000
246#define WM831X_CLKOUT_ENA_SHIFT 15
247#define WM831X_CLKOUT_ENA_WIDTH 1
248#define WM831X_CLKOUT_OD 0x2000
249#define WM831X_CLKOUT_OD_MASK 0x2000
250#define WM831X_CLKOUT_OD_SHIFT 13
251#define WM831X_CLKOUT_OD_WIDTH 1
252#define WM831X_CLKOUT_SLOT_MASK 0x0700
253#define WM831X_CLKOUT_SLOT_SHIFT 8
254#define WM831X_CLKOUT_SLOT_WIDTH 3
255#define WM831X_CLKOUT_SLPSLOT_MASK 0x0070
256#define WM831X_CLKOUT_SLPSLOT_SHIFT 4
257#define WM831X_CLKOUT_SLPSLOT_WIDTH 3
258#define WM831X_CLKOUT_SRC 0x0001
259#define WM831X_CLKOUT_SRC_MASK 0x0001
260#define WM831X_CLKOUT_SRC_SHIFT 0
261#define WM831X_CLKOUT_SRC_WIDTH 1
262
263
264
265
266#define WM831X_XTAL_INH 0x8000
267#define WM831X_XTAL_INH_MASK 0x8000
268#define WM831X_XTAL_INH_SHIFT 15
269#define WM831X_XTAL_INH_WIDTH 1
270#define WM831X_XTAL_ENA 0x2000
271#define WM831X_XTAL_ENA_MASK 0x2000
272#define WM831X_XTAL_ENA_SHIFT 13
273#define WM831X_XTAL_ENA_WIDTH 1
274#define WM831X_XTAL_BKUPENA 0x1000
275#define WM831X_XTAL_BKUPENA_MASK 0x1000
276#define WM831X_XTAL_BKUPENA_SHIFT 12
277#define WM831X_XTAL_BKUPENA_WIDTH 1
278#define WM831X_FLL_AUTO 0x0080
279#define WM831X_FLL_AUTO_MASK 0x0080
280#define WM831X_FLL_AUTO_SHIFT 7
281#define WM831X_FLL_AUTO_WIDTH 1
282#define WM831X_FLL_AUTO_FREQ_MASK 0x0007
283#define WM831X_FLL_AUTO_FREQ_SHIFT 0
284#define WM831X_FLL_AUTO_FREQ_WIDTH 3
285
286
287
288
289#define WM831X_FLL_FRAC 0x0004
290#define WM831X_FLL_FRAC_MASK 0x0004
291#define WM831X_FLL_FRAC_SHIFT 2
292#define WM831X_FLL_FRAC_WIDTH 1
293#define WM831X_FLL_OSC_ENA 0x0002
294#define WM831X_FLL_OSC_ENA_MASK 0x0002
295#define WM831X_FLL_OSC_ENA_SHIFT 1
296#define WM831X_FLL_OSC_ENA_WIDTH 1
297#define WM831X_FLL_ENA 0x0001
298#define WM831X_FLL_ENA_MASK 0x0001
299#define WM831X_FLL_ENA_SHIFT 0
300#define WM831X_FLL_ENA_WIDTH 1
301
302
303
304
305#define WM831X_FLL_OUTDIV_MASK 0x3F00
306#define WM831X_FLL_OUTDIV_SHIFT 8
307#define WM831X_FLL_OUTDIV_WIDTH 6
308#define WM831X_FLL_CTRL_RATE_MASK 0x0070
309#define WM831X_FLL_CTRL_RATE_SHIFT 4
310#define WM831X_FLL_CTRL_RATE_WIDTH 3
311#define WM831X_FLL_FRATIO_MASK 0x0007
312#define WM831X_FLL_FRATIO_SHIFT 0
313#define WM831X_FLL_FRATIO_WIDTH 3
314
315
316
317
318#define WM831X_FLL_K_MASK 0xFFFF
319#define WM831X_FLL_K_SHIFT 0
320#define WM831X_FLL_K_WIDTH 16
321
322
323
324
325#define WM831X_FLL_N_MASK 0x7FE0
326#define WM831X_FLL_N_SHIFT 5
327#define WM831X_FLL_N_WIDTH 10
328#define WM831X_FLL_GAIN_MASK 0x000F
329#define WM831X_FLL_GAIN_SHIFT 0
330#define WM831X_FLL_GAIN_WIDTH 4
331
332
333
334
335#define WM831X_FLL_CLK_REF_DIV_MASK 0x0018
336#define WM831X_FLL_CLK_REF_DIV_SHIFT 3
337#define WM831X_FLL_CLK_REF_DIV_WIDTH 2
338#define WM831X_FLL_CLK_SRC_MASK 0x0003
339#define WM831X_FLL_CLK_SRC_SHIFT 0
340#define WM831X_FLL_CLK_SRC_WIDTH 2
341
342struct regulator_dev;
343struct irq_domain;
344
345#define WM831X_NUM_IRQ_REGS 5
346#define WM831X_NUM_GPIO_REGS 16
347
348enum wm831x_parent {
349 WM8310 = 0x8310,
350 WM8311 = 0x8311,
351 WM8312 = 0x8312,
352 WM8320 = 0x8320,
353 WM8321 = 0x8321,
354 WM8325 = 0x8325,
355 WM8326 = 0x8326,
356};
357
358struct wm831x;
359
360typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x,
361 enum wm831x_auxadc input);
362
363struct wm831x {
364 struct mutex io_lock;
365
366 struct device *dev;
367
368 struct regmap *regmap;
369
370 int irq;
371 struct mutex irq_lock;
372 struct irq_domain *irq_domain;
373 int irq_masks_cur[WM831X_NUM_IRQ_REGS];
374 int irq_masks_cache[WM831X_NUM_IRQ_REGS];
375
376 bool soft_shutdown;
377
378
379 unsigned has_gpio_ena:1;
380 unsigned has_cs_sts:1;
381 unsigned charger_irq_wake:1;
382
383 int num_gpio;
384
385
386 int gpio_update[WM831X_NUM_GPIO_REGS];
387 bool gpio_level_high[WM831X_NUM_GPIO_REGS];
388 bool gpio_level_low[WM831X_NUM_GPIO_REGS];
389
390 struct mutex auxadc_lock;
391 struct list_head auxadc_pending;
392 u16 auxadc_active;
393 wm831x_auxadc_read_fn auxadc_read;
394
395
396
397
398
399
400 struct mutex key_lock;
401 unsigned int locked:1;
402};
403
404
405int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
406int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
407 unsigned short val);
408void wm831x_reg_lock(struct wm831x *wm831x);
409int wm831x_reg_unlock(struct wm831x *wm831x);
410int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
411 unsigned short mask, unsigned short val);
412int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
413 int count, u16 *buf);
414
415int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq);
416void wm831x_device_exit(struct wm831x *wm831x);
417int wm831x_device_suspend(struct wm831x *wm831x);
418void wm831x_device_shutdown(struct wm831x *wm831x);
419int wm831x_irq_init(struct wm831x *wm831x, int irq);
420void wm831x_irq_exit(struct wm831x *wm831x);
421void wm831x_auxadc_init(struct wm831x *wm831x);
422
423static inline int wm831x_irq(struct wm831x *wm831x, int irq)
424{
425 return irq_create_mapping(wm831x->irq_domain, irq);
426}
427
428extern struct regmap_config wm831x_regmap_config;
429
430#endif
431