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18#ifndef __LINUX_MTD_NAND_H
19#define __LINUX_MTD_NAND_H
20
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/flashchip.h>
25#include <linux/mtd/bbm.h>
26
27struct mtd_info;
28struct nand_flash_dev;
29struct device_node;
30
31
32extern int nand_scan(struct mtd_info *mtd, int max_chips);
33
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35
36
37extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
38 struct nand_flash_dev *table);
39extern int nand_scan_tail(struct mtd_info *mtd);
40
41
42extern void nand_release(struct mtd_info *mtd);
43
44
45extern void nand_wait_ready(struct mtd_info *mtd);
46
47
48extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
49
50
51extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
52
53
54#define NAND_MAX_CHIPS 8
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61
62
63#define NAND_NCE 0x01
64
65#define NAND_CLE 0x02
66
67#define NAND_ALE 0x04
68
69#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
70#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
71#define NAND_CTRL_CHANGE 0x80
72
73
74
75
76#define NAND_CMD_READ0 0
77#define NAND_CMD_READ1 1
78#define NAND_CMD_RNDOUT 5
79#define NAND_CMD_PAGEPROG 0x10
80#define NAND_CMD_READOOB 0x50
81#define NAND_CMD_ERASE1 0x60
82#define NAND_CMD_STATUS 0x70
83#define NAND_CMD_SEQIN 0x80
84#define NAND_CMD_RNDIN 0x85
85#define NAND_CMD_READID 0x90
86#define NAND_CMD_ERASE2 0xd0
87#define NAND_CMD_PARAM 0xec
88#define NAND_CMD_GET_FEATURES 0xee
89#define NAND_CMD_SET_FEATURES 0xef
90#define NAND_CMD_RESET 0xff
91
92#define NAND_CMD_LOCK 0x2a
93#define NAND_CMD_UNLOCK1 0x23
94#define NAND_CMD_UNLOCK2 0x24
95
96
97#define NAND_CMD_READSTART 0x30
98#define NAND_CMD_RNDOUTSTART 0xE0
99#define NAND_CMD_CACHEDPROG 0x15
100
101#define NAND_CMD_NONE -1
102
103
104#define NAND_STATUS_FAIL 0x01
105#define NAND_STATUS_FAIL_N1 0x02
106#define NAND_STATUS_TRUE_READY 0x20
107#define NAND_STATUS_READY 0x40
108#define NAND_STATUS_WP 0x80
109
110
111
112
113typedef enum {
114 NAND_ECC_NONE,
115 NAND_ECC_SOFT,
116 NAND_ECC_HW,
117 NAND_ECC_HW_SYNDROME,
118 NAND_ECC_HW_OOB_FIRST,
119 NAND_ECC_SOFT_BCH,
120} nand_ecc_modes_t;
121
122
123
124
125
126#define NAND_ECC_READ 0
127
128#define NAND_ECC_WRITE 1
129
130#define NAND_ECC_READSYN 2
131
132
133#define NAND_GET_DEVICE 0x80
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140
141#define NAND_BUSWIDTH_16 0x00000002
142
143#define NAND_CACHEPRG 0x00000008
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148
149#define NAND_NEED_READRDY 0x00000100
150
151
152#define NAND_NO_SUBPAGE_WRITE 0x00000200
153
154
155#define NAND_BROKEN_XD 0x00000400
156
157
158#define NAND_ROM 0x00000800
159
160
161#define NAND_SUBPAGE_READ 0x00001000
162
163
164#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
165
166
167#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
168#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
169
170
171
172#define NAND_SKIP_BBTSCAN 0x00010000
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176
177#define NAND_OWN_BUFFERS 0x00020000
178
179#define NAND_SCAN_SILENT_NODEV 0x00040000
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185
186#define NAND_BUSWIDTH_AUTO 0x00080000
187
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189
190
191#define NAND_USE_BOUNCE_BUFFER 0x00100000
192
193
194
195#define NAND_CONTROLLER_ALLOC 0x80000000
196
197
198#define NAND_CI_CHIPNR_MSK 0x03
199#define NAND_CI_CELLTYPE_MSK 0x0C
200#define NAND_CI_CELLTYPE_SHIFT 2
201
202
203struct nand_chip;
204
205
206#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
207#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
208
209
210#define ONFI_TIMING_MODE_0 (1 << 0)
211#define ONFI_TIMING_MODE_1 (1 << 1)
212#define ONFI_TIMING_MODE_2 (1 << 2)
213#define ONFI_TIMING_MODE_3 (1 << 3)
214#define ONFI_TIMING_MODE_4 (1 << 4)
215#define ONFI_TIMING_MODE_5 (1 << 5)
216#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
217
218
219#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
220
221
222#define ONFI_FEATURE_ADDR_READ_RETRY 0x89
223
224
225#define ONFI_SUBFEATURE_PARAM_LEN 4
226
227
228#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
229
230struct nand_onfi_params {
231
232
233 u8 sig[4];
234 __le16 revision;
235 __le16 features;
236 __le16 opt_cmd;
237 u8 reserved0[2];
238 __le16 ext_param_page_length;
239 u8 num_of_param_pages;
240 u8 reserved1[17];
241
242
243 char manufacturer[12];
244 char model[20];
245 u8 jedec_id;
246 __le16 date_code;
247 u8 reserved2[13];
248
249
250 __le32 byte_per_page;
251 __le16 spare_bytes_per_page;
252 __le32 data_bytes_per_ppage;
253 __le16 spare_bytes_per_ppage;
254 __le32 pages_per_block;
255 __le32 blocks_per_lun;
256 u8 lun_count;
257 u8 addr_cycles;
258 u8 bits_per_cell;
259 __le16 bb_per_lun;
260 __le16 block_endurance;
261 u8 guaranteed_good_blocks;
262 __le16 guaranteed_block_endurance;
263 u8 programs_per_page;
264 u8 ppage_attr;
265 u8 ecc_bits;
266 u8 interleaved_bits;
267 u8 interleaved_ops;
268 u8 reserved3[13];
269
270
271 u8 io_pin_capacitance_max;
272 __le16 async_timing_mode;
273 __le16 program_cache_timing_mode;
274 __le16 t_prog;
275 __le16 t_bers;
276 __le16 t_r;
277 __le16 t_ccs;
278 __le16 src_sync_timing_mode;
279 __le16 src_ssync_features;
280 __le16 clk_pin_capacitance_typ;
281 __le16 io_pin_capacitance_typ;
282 __le16 input_pin_capacitance_typ;
283 u8 input_pin_capacitance_max;
284 u8 driver_strength_support;
285 __le16 t_int_r;
286 __le16 t_ald;
287 u8 reserved4[7];
288
289
290 __le16 vendor_revision;
291 u8 vendor[88];
292
293 __le16 crc;
294} __packed;
295
296#define ONFI_CRC_BASE 0x4F4E
297
298
299struct onfi_ext_ecc_info {
300 u8 ecc_bits;
301 u8 codeword_size;
302 __le16 bb_per_lun;
303 __le16 block_endurance;
304 u8 reserved[2];
305} __packed;
306
307#define ONFI_SECTION_TYPE_0 0
308#define ONFI_SECTION_TYPE_1 1
309#define ONFI_SECTION_TYPE_2 2
310struct onfi_ext_section {
311 u8 type;
312 u8 length;
313} __packed;
314
315#define ONFI_EXT_SECTION_MAX 8
316
317
318struct onfi_ext_param_page {
319 __le16 crc;
320 u8 sig[4];
321 u8 reserved0[10];
322 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
323
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329
330} __packed;
331
332struct nand_onfi_vendor_micron {
333 u8 two_plane_read;
334 u8 read_cache;
335 u8 read_unique_id;
336 u8 dq_imped;
337 u8 dq_imped_num_settings;
338 u8 dq_imped_feat_addr;
339 u8 rb_pulldown_strength;
340 u8 rb_pulldown_strength_feat_addr;
341 u8 rb_pulldown_strength_num_settings;
342 u8 otp_mode;
343 u8 otp_page_start;
344 u8 otp_data_prot_addr;
345 u8 otp_num_pages;
346 u8 otp_feat_addr;
347 u8 read_retry_options;
348 u8 reserved[72];
349 u8 param_revision;
350} __packed;
351
352struct jedec_ecc_info {
353 u8 ecc_bits;
354 u8 codeword_size;
355 __le16 bb_per_lun;
356 __le16 block_endurance;
357 u8 reserved[2];
358} __packed;
359
360
361#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
362
363struct nand_jedec_params {
364
365
366 u8 sig[4];
367 __le16 revision;
368 __le16 features;
369 u8 opt_cmd[3];
370 __le16 sec_cmd;
371 u8 num_of_param_pages;
372 u8 reserved0[18];
373
374
375 char manufacturer[12];
376 char model[20];
377 u8 jedec_id[6];
378 u8 reserved1[10];
379
380
381 __le32 byte_per_page;
382 __le16 spare_bytes_per_page;
383 u8 reserved2[6];
384 __le32 pages_per_block;
385 __le32 blocks_per_lun;
386 u8 lun_count;
387 u8 addr_cycles;
388 u8 bits_per_cell;
389 u8 programs_per_page;
390 u8 multi_plane_addr;
391 u8 multi_plane_op_attr;
392 u8 reserved3[38];
393
394
395 __le16 async_sdr_speed_grade;
396 __le16 toggle_ddr_speed_grade;
397 __le16 sync_ddr_speed_grade;
398 u8 async_sdr_features;
399 u8 toggle_ddr_features;
400 u8 sync_ddr_features;
401 __le16 t_prog;
402 __le16 t_bers;
403 __le16 t_r;
404 __le16 t_r_multi_plane;
405 __le16 t_ccs;
406 __le16 io_pin_capacitance_typ;
407 __le16 input_pin_capacitance_typ;
408 __le16 clk_pin_capacitance_typ;
409 u8 driver_strength_support;
410 __le16 t_ald;
411 u8 reserved4[36];
412
413
414 u8 guaranteed_good_blocks;
415 __le16 guaranteed_block_endurance;
416 struct jedec_ecc_info ecc_info[4];
417 u8 reserved5[29];
418
419
420 u8 reserved6[148];
421
422
423 __le16 vendor_rev_num;
424 u8 reserved7[88];
425
426
427 __le16 crc;
428} __packed;
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437
438struct nand_hw_control {
439 spinlock_t lock;
440 struct nand_chip *active;
441 wait_queue_head_t wq;
442};
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488struct nand_ecc_ctrl {
489 nand_ecc_modes_t mode;
490 int steps;
491 int size;
492 int bytes;
493 int total;
494 int strength;
495 int prepad;
496 int postpad;
497 struct nand_ecclayout *layout;
498 void *priv;
499 void (*hwctl)(struct mtd_info *mtd, int mode);
500 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
501 uint8_t *ecc_code);
502 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
503 uint8_t *calc_ecc);
504 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
505 uint8_t *buf, int oob_required, int page);
506 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
507 const uint8_t *buf, int oob_required);
508 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
509 uint8_t *buf, int oob_required, int page);
510 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
511 uint32_t offs, uint32_t len, uint8_t *buf, int page);
512 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
513 uint32_t offset, uint32_t data_len,
514 const uint8_t *data_buf, int oob_required);
515 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
516 const uint8_t *buf, int oob_required);
517 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
518 int page);
519 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
520 int page);
521 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
522 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
523 int page);
524};
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534
535struct nand_buffers {
536 uint8_t *ecccalc;
537 uint8_t *ecccode;
538 uint8_t *databuf;
539};
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646struct nand_chip {
647 void __iomem *IO_ADDR_R;
648 void __iomem *IO_ADDR_W;
649
650 struct device_node *dn;
651
652 uint8_t (*read_byte)(struct mtd_info *mtd);
653 u16 (*read_word)(struct mtd_info *mtd);
654 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
655 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
656 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
657 void (*select_chip)(struct mtd_info *mtd, int chip);
658 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
659 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
660 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
661 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
662 u8 *id_data);
663 int (*dev_ready)(struct mtd_info *mtd);
664 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
665 int page_addr);
666 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
667 int (*erase)(struct mtd_info *mtd, int page);
668 int (*scan_bbt)(struct mtd_info *mtd);
669 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
670 int status, int page);
671 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
672 uint32_t offset, int data_len, const uint8_t *buf,
673 int oob_required, int page, int cached, int raw);
674 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
675 int feature_addr, uint8_t *subfeature_para);
676 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
677 int feature_addr, uint8_t *subfeature_para);
678 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
679
680 int chip_delay;
681 unsigned int options;
682 unsigned int bbt_options;
683
684 int page_shift;
685 int phys_erase_shift;
686 int bbt_erase_shift;
687 int chip_shift;
688 int numchips;
689 uint64_t chipsize;
690 int pagemask;
691 int pagebuf;
692 unsigned int pagebuf_bitflips;
693 int subpagesize;
694 uint8_t bits_per_cell;
695 uint16_t ecc_strength_ds;
696 uint16_t ecc_step_ds;
697 int onfi_timing_mode_default;
698 int badblockpos;
699 int badblockbits;
700
701 int onfi_version;
702 int jedec_version;
703 union {
704 struct nand_onfi_params onfi_params;
705 struct nand_jedec_params jedec_params;
706 };
707
708 int read_retries;
709
710 flstate_t state;
711
712 uint8_t *oob_poi;
713 struct nand_hw_control *controller;
714
715 struct nand_ecc_ctrl ecc;
716 struct nand_buffers *buffers;
717 struct nand_hw_control hwcontrol;
718
719 uint8_t *bbt;
720 struct nand_bbt_descr *bbt_td;
721 struct nand_bbt_descr *bbt_md;
722
723 struct nand_bbt_descr *badblock_pattern;
724
725 void *priv;
726};
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730
731#define NAND_MFR_TOSHIBA 0x98
732#define NAND_MFR_SAMSUNG 0xec
733#define NAND_MFR_FUJITSU 0x04
734#define NAND_MFR_NATIONAL 0x8f
735#define NAND_MFR_RENESAS 0x07
736#define NAND_MFR_STMICRO 0x20
737#define NAND_MFR_HYNIX 0xad
738#define NAND_MFR_MICRON 0x2c
739#define NAND_MFR_AMD 0x01
740#define NAND_MFR_MACRONIX 0xc2
741#define NAND_MFR_EON 0x92
742#define NAND_MFR_SANDISK 0x45
743#define NAND_MFR_INTEL 0x89
744#define NAND_MFR_ATO 0x9b
745
746
747#define NAND_MAX_ID_LEN 8
748
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753
754#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
755 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
756 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
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768#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
769 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
770 .options = (opts) }
771
772#define NAND_ECC_INFO(_strength, _step) \
773 { .strength_ds = (_strength), .step_ds = (_step) }
774#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
775#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
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806struct nand_flash_dev {
807 char *name;
808 union {
809 struct {
810 uint8_t mfr_id;
811 uint8_t dev_id;
812 };
813 uint8_t id[NAND_MAX_ID_LEN];
814 };
815 unsigned int pagesize;
816 unsigned int chipsize;
817 unsigned int erasesize;
818 unsigned int options;
819 uint16_t id_len;
820 uint16_t oobsize;
821 struct {
822 uint16_t strength_ds;
823 uint16_t step_ds;
824 } ecc;
825 int onfi_timing_mode_default;
826};
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833struct nand_manufacturers {
834 int id;
835 char *name;
836};
837
838extern struct nand_flash_dev nand_flash_ids[];
839extern struct nand_manufacturers nand_manuf_ids[];
840
841extern int nand_default_bbt(struct mtd_info *mtd);
842extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
843extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
844extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
845extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
846 int allowbbt);
847extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
848 size_t *retlen, uint8_t *buf);
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862struct platform_nand_chip {
863 int nr_chips;
864 int chip_offset;
865 int nr_partitions;
866 struct mtd_partition *partitions;
867 struct nand_ecclayout *ecclayout;
868 int chip_delay;
869 unsigned int options;
870 unsigned int bbt_options;
871 const char **part_probe_types;
872};
873
874
875struct platform_device;
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893struct platform_nand_ctrl {
894 int (*probe)(struct platform_device *pdev);
895 void (*remove)(struct platform_device *pdev);
896 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
897 int (*dev_ready)(struct mtd_info *mtd);
898 void (*select_chip)(struct mtd_info *mtd, int chip);
899 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
900 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
901 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
902 unsigned char (*read_byte)(struct mtd_info *mtd);
903 void *priv;
904};
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911struct platform_nand_data {
912 struct platform_nand_chip chip;
913 struct platform_nand_ctrl ctrl;
914};
915
916
917static inline
918struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
919{
920 struct nand_chip *chip = mtd->priv;
921
922 return chip->priv;
923}
924
925
926static inline int onfi_feature(struct nand_chip *chip)
927{
928 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
929}
930
931
932static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
933{
934 if (!chip->onfi_version)
935 return ONFI_TIMING_MODE_UNKNOWN;
936 return le16_to_cpu(chip->onfi_params.async_timing_mode);
937}
938
939
940static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
941{
942 if (!chip->onfi_version)
943 return ONFI_TIMING_MODE_UNKNOWN;
944 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
945}
946
947
948
949
950
951
952static inline bool nand_is_slc(struct nand_chip *chip)
953{
954 return chip->bits_per_cell == 1;
955}
956
957
958
959
960
961static inline int nand_opcode_8bits(unsigned int command)
962{
963 switch (command) {
964 case NAND_CMD_READID:
965 case NAND_CMD_PARAM:
966 case NAND_CMD_GET_FEATURES:
967 case NAND_CMD_SET_FEATURES:
968 return 1;
969 default:
970 break;
971 }
972 return 0;
973}
974
975
976static inline int jedec_feature(struct nand_chip *chip)
977{
978 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
979 : 0;
980}
981
982
983
984
985
986
987
988
989
990
991
992
993
994struct nand_sdr_timings {
995 u32 tALH_min;
996 u32 tADL_min;
997 u32 tALS_min;
998 u32 tAR_min;
999 u32 tCEA_max;
1000 u32 tCEH_min;
1001 u32 tCH_min;
1002 u32 tCHZ_max;
1003 u32 tCLH_min;
1004 u32 tCLR_min;
1005 u32 tCLS_min;
1006 u32 tCOH_min;
1007 u32 tCS_min;
1008 u32 tDH_min;
1009 u32 tDS_min;
1010 u32 tFEAT_max;
1011 u32 tIR_min;
1012 u32 tITC_max;
1013 u32 tRC_min;
1014 u32 tREA_max;
1015 u32 tREH_min;
1016 u32 tRHOH_min;
1017 u32 tRHW_min;
1018 u32 tRHZ_max;
1019 u32 tRLOH_min;
1020 u32 tRP_min;
1021 u32 tRR_min;
1022 u64 tRST_max;
1023 u32 tWB_max;
1024 u32 tWC_min;
1025 u32 tWH_min;
1026 u32 tWHR_min;
1027 u32 tWP_min;
1028 u32 tWW_min;
1029};
1030
1031
1032const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1033#endif
1034