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23#ifndef _UAPI__SOUND_ASOUND_H
24#define _UAPI__SOUND_ASOUND_H
25
26#include <linux/types.h>
27
28#ifndef __KERNEL__
29#include <stdlib.h>
30#endif
31
32
33
34
35
36#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor))
37#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff)
38#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff)
39#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff)
40#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \
41 (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \
42 (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \
43 SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion)))
44
45
46
47
48
49
50
51struct snd_aes_iec958 {
52 unsigned char status[24];
53 unsigned char subcode[147];
54 unsigned char pad;
55 unsigned char dig_subframe[4];
56};
57
58
59
60
61
62
63
64struct snd_cea_861_aud_if {
65 unsigned char db1_ct_cc;
66 unsigned char db2_sf_ss;
67 unsigned char db3;
68 unsigned char db4_ca;
69 unsigned char db5_dminh_lsv;
70};
71
72
73
74
75
76
77
78#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
79
80enum {
81 SNDRV_HWDEP_IFACE_OPL2 = 0,
82 SNDRV_HWDEP_IFACE_OPL3,
83 SNDRV_HWDEP_IFACE_OPL4,
84 SNDRV_HWDEP_IFACE_SB16CSP,
85 SNDRV_HWDEP_IFACE_EMU10K1,
86 SNDRV_HWDEP_IFACE_YSS225,
87 SNDRV_HWDEP_IFACE_ICS2115,
88 SNDRV_HWDEP_IFACE_SSCAPE,
89 SNDRV_HWDEP_IFACE_VX,
90 SNDRV_HWDEP_IFACE_MIXART,
91 SNDRV_HWDEP_IFACE_USX2Y,
92 SNDRV_HWDEP_IFACE_EMUX_WAVETABLE,
93 SNDRV_HWDEP_IFACE_BLUETOOTH,
94 SNDRV_HWDEP_IFACE_USX2Y_PCM,
95 SNDRV_HWDEP_IFACE_PCXHR,
96 SNDRV_HWDEP_IFACE_SB_RC,
97 SNDRV_HWDEP_IFACE_HDA,
98 SNDRV_HWDEP_IFACE_USB_STREAM,
99 SNDRV_HWDEP_IFACE_FW_DICE,
100 SNDRV_HWDEP_IFACE_FW_FIREWORKS,
101 SNDRV_HWDEP_IFACE_FW_BEBOB,
102 SNDRV_HWDEP_IFACE_FW_OXFW,
103
104
105 SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_FW_OXFW
106};
107
108struct snd_hwdep_info {
109 unsigned int device;
110 int card;
111 unsigned char id[64];
112 unsigned char name[80];
113 int iface;
114 unsigned char reserved[64];
115};
116
117
118struct snd_hwdep_dsp_status {
119 unsigned int version;
120 unsigned char id[32];
121 unsigned int num_dsps;
122 unsigned int dsp_loaded;
123 unsigned int chip_ready;
124 unsigned char reserved[16];
125};
126
127struct snd_hwdep_dsp_image {
128 unsigned int index;
129 unsigned char name[64];
130 unsigned char __user *image;
131 size_t length;
132 unsigned long driver_data;
133};
134
135#define SNDRV_HWDEP_IOCTL_PVERSION _IOR ('H', 0x00, int)
136#define SNDRV_HWDEP_IOCTL_INFO _IOR ('H', 0x01, struct snd_hwdep_info)
137#define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status)
138#define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image)
139
140
141
142
143
144
145
146#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 13)
147
148typedef unsigned long snd_pcm_uframes_t;
149typedef signed long snd_pcm_sframes_t;
150
151enum {
152 SNDRV_PCM_CLASS_GENERIC = 0,
153 SNDRV_PCM_CLASS_MULTI,
154 SNDRV_PCM_CLASS_MODEM,
155 SNDRV_PCM_CLASS_DIGITIZER,
156
157 SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER,
158};
159
160enum {
161 SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0,
162 SNDRV_PCM_SUBCLASS_MULTI_MIX,
163
164 SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX,
165};
166
167enum {
168 SNDRV_PCM_STREAM_PLAYBACK = 0,
169 SNDRV_PCM_STREAM_CAPTURE,
170 SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE,
171};
172
173typedef int __bitwise snd_pcm_access_t;
174#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((__force snd_pcm_access_t) 0)
175#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((__force snd_pcm_access_t) 1)
176#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((__force snd_pcm_access_t) 2)
177#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((__force snd_pcm_access_t) 3)
178#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((__force snd_pcm_access_t) 4)
179#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED
180
181typedef int __bitwise snd_pcm_format_t;
182#define SNDRV_PCM_FORMAT_S8 ((__force snd_pcm_format_t) 0)
183#define SNDRV_PCM_FORMAT_U8 ((__force snd_pcm_format_t) 1)
184#define SNDRV_PCM_FORMAT_S16_LE ((__force snd_pcm_format_t) 2)
185#define SNDRV_PCM_FORMAT_S16_BE ((__force snd_pcm_format_t) 3)
186#define SNDRV_PCM_FORMAT_U16_LE ((__force snd_pcm_format_t) 4)
187#define SNDRV_PCM_FORMAT_U16_BE ((__force snd_pcm_format_t) 5)
188#define SNDRV_PCM_FORMAT_S24_LE ((__force snd_pcm_format_t) 6)
189#define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7)
190#define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8)
191#define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9)
192#define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10)
193#define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11)
194#define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12)
195#define SNDRV_PCM_FORMAT_U32_BE ((__force snd_pcm_format_t) 13)
196#define SNDRV_PCM_FORMAT_FLOAT_LE ((__force snd_pcm_format_t) 14)
197#define SNDRV_PCM_FORMAT_FLOAT_BE ((__force snd_pcm_format_t) 15)
198#define SNDRV_PCM_FORMAT_FLOAT64_LE ((__force snd_pcm_format_t) 16)
199#define SNDRV_PCM_FORMAT_FLOAT64_BE ((__force snd_pcm_format_t) 17)
200#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((__force snd_pcm_format_t) 18)
201#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((__force snd_pcm_format_t) 19)
202#define SNDRV_PCM_FORMAT_MU_LAW ((__force snd_pcm_format_t) 20)
203#define SNDRV_PCM_FORMAT_A_LAW ((__force snd_pcm_format_t) 21)
204#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22)
205#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23)
206#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24)
207#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31)
208#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32)
209#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33)
210#define SNDRV_PCM_FORMAT_U24_3LE ((__force snd_pcm_format_t) 34)
211#define SNDRV_PCM_FORMAT_U24_3BE ((__force snd_pcm_format_t) 35)
212#define SNDRV_PCM_FORMAT_S20_3LE ((__force snd_pcm_format_t) 36)
213#define SNDRV_PCM_FORMAT_S20_3BE ((__force snd_pcm_format_t) 37)
214#define SNDRV_PCM_FORMAT_U20_3LE ((__force snd_pcm_format_t) 38)
215#define SNDRV_PCM_FORMAT_U20_3BE ((__force snd_pcm_format_t) 39)
216#define SNDRV_PCM_FORMAT_S18_3LE ((__force snd_pcm_format_t) 40)
217#define SNDRV_PCM_FORMAT_S18_3BE ((__force snd_pcm_format_t) 41)
218#define SNDRV_PCM_FORMAT_U18_3LE ((__force snd_pcm_format_t) 42)
219#define SNDRV_PCM_FORMAT_U18_3BE ((__force snd_pcm_format_t) 43)
220#define SNDRV_PCM_FORMAT_G723_24 ((__force snd_pcm_format_t) 44)
221#define SNDRV_PCM_FORMAT_G723_24_1B ((__force snd_pcm_format_t) 45)
222#define SNDRV_PCM_FORMAT_G723_40 ((__force snd_pcm_format_t) 46)
223#define SNDRV_PCM_FORMAT_G723_40_1B ((__force snd_pcm_format_t) 47)
224#define SNDRV_PCM_FORMAT_DSD_U8 ((__force snd_pcm_format_t) 48)
225#define SNDRV_PCM_FORMAT_DSD_U16_LE ((__force snd_pcm_format_t) 49)
226#define SNDRV_PCM_FORMAT_DSD_U32_LE ((__force snd_pcm_format_t) 50)
227#define SNDRV_PCM_FORMAT_DSD_U16_BE ((__force snd_pcm_format_t) 51)
228#define SNDRV_PCM_FORMAT_DSD_U32_BE ((__force snd_pcm_format_t) 52)
229#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U32_BE
230
231#ifdef SNDRV_LITTLE_ENDIAN
232#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE
233#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE
234#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE
235#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE
236#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE
237#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE
238#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
239#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
240#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
241#endif
242#ifdef SNDRV_BIG_ENDIAN
243#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
244#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE
245#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE
246#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE
247#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE
248#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE
249#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
250#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
251#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
252#endif
253
254typedef int __bitwise snd_pcm_subformat_t;
255#define SNDRV_PCM_SUBFORMAT_STD ((__force snd_pcm_subformat_t) 0)
256#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD
257
258#define SNDRV_PCM_INFO_MMAP 0x00000001
259#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002
260#define SNDRV_PCM_INFO_DOUBLE 0x00000004
261#define SNDRV_PCM_INFO_BATCH 0x00000010
262#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100
263#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200
264#define SNDRV_PCM_INFO_COMPLEX 0x00000400
265#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000
266#define SNDRV_PCM_INFO_OVERRANGE 0x00020000
267#define SNDRV_PCM_INFO_RESUME 0x00040000
268#define SNDRV_PCM_INFO_PAUSE 0x00080000
269#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000
270#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000
271#define SNDRV_PCM_INFO_SYNC_START 0x00400000
272#define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000
273#define SNDRV_PCM_INFO_HAS_WALL_CLOCK 0x01000000
274#define SNDRV_PCM_INFO_HAS_LINK_ATIME 0x01000000
275#define SNDRV_PCM_INFO_HAS_LINK_ABSOLUTE_ATIME 0x02000000
276#define SNDRV_PCM_INFO_HAS_LINK_ESTIMATED_ATIME 0x04000000
277#define SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 0x08000000
278
279#define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000
280#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000
281
282
283
284typedef int __bitwise snd_pcm_state_t;
285#define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0)
286#define SNDRV_PCM_STATE_SETUP ((__force snd_pcm_state_t) 1)
287#define SNDRV_PCM_STATE_PREPARED ((__force snd_pcm_state_t) 2)
288#define SNDRV_PCM_STATE_RUNNING ((__force snd_pcm_state_t) 3)
289#define SNDRV_PCM_STATE_XRUN ((__force snd_pcm_state_t) 4)
290#define SNDRV_PCM_STATE_DRAINING ((__force snd_pcm_state_t) 5)
291#define SNDRV_PCM_STATE_PAUSED ((__force snd_pcm_state_t) 6)
292#define SNDRV_PCM_STATE_SUSPENDED ((__force snd_pcm_state_t) 7)
293#define SNDRV_PCM_STATE_DISCONNECTED ((__force snd_pcm_state_t) 8)
294#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED
295
296enum {
297 SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000,
298 SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000,
299 SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000,
300};
301
302union snd_pcm_sync_id {
303 unsigned char id[16];
304 unsigned short id16[8];
305 unsigned int id32[4];
306};
307
308struct snd_pcm_info {
309 unsigned int device;
310 unsigned int subdevice;
311 int stream;
312 int card;
313 unsigned char id[64];
314 unsigned char name[80];
315 unsigned char subname[32];
316 int dev_class;
317 int dev_subclass;
318 unsigned int subdevices_count;
319 unsigned int subdevices_avail;
320 union snd_pcm_sync_id sync;
321 unsigned char reserved[64];
322};
323
324typedef int snd_pcm_hw_param_t;
325#define SNDRV_PCM_HW_PARAM_ACCESS 0
326#define SNDRV_PCM_HW_PARAM_FORMAT 1
327#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2
328#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS
329#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT
330
331#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8
332#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9
333#define SNDRV_PCM_HW_PARAM_CHANNELS 10
334#define SNDRV_PCM_HW_PARAM_RATE 11
335#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12
336
337
338#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13
339
340
341#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14
342
343
344#define SNDRV_PCM_HW_PARAM_PERIODS 15
345
346
347#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16
348
349
350#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17
351#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18
352#define SNDRV_PCM_HW_PARAM_TICK_TIME 19
353#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS
354#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME
355
356#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0)
357#define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1<<1)
358#define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1<<2)
359
360struct snd_interval {
361 unsigned int min, max;
362 unsigned int openmin:1,
363 openmax:1,
364 integer:1,
365 empty:1;
366};
367
368#define SNDRV_MASK_MAX 256
369
370struct snd_mask {
371 __u32 bits[(SNDRV_MASK_MAX+31)/32];
372};
373
374struct snd_pcm_hw_params {
375 unsigned int flags;
376 struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK -
377 SNDRV_PCM_HW_PARAM_FIRST_MASK + 1];
378 struct snd_mask mres[5];
379 struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL -
380 SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1];
381 struct snd_interval ires[9];
382 unsigned int rmask;
383 unsigned int cmask;
384 unsigned int info;
385 unsigned int msbits;
386 unsigned int rate_num;
387 unsigned int rate_den;
388 snd_pcm_uframes_t fifo_size;
389 unsigned char reserved[64];
390};
391
392enum {
393 SNDRV_PCM_TSTAMP_NONE = 0,
394 SNDRV_PCM_TSTAMP_ENABLE,
395 SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE,
396};
397
398struct snd_pcm_sw_params {
399 int tstamp_mode;
400 unsigned int period_step;
401 unsigned int sleep_min;
402 snd_pcm_uframes_t avail_min;
403 snd_pcm_uframes_t xfer_align;
404 snd_pcm_uframes_t start_threshold;
405 snd_pcm_uframes_t stop_threshold;
406 snd_pcm_uframes_t silence_threshold;
407 snd_pcm_uframes_t silence_size;
408 snd_pcm_uframes_t boundary;
409 unsigned int proto;
410 unsigned int tstamp_type;
411 unsigned char reserved[56];
412};
413
414struct snd_pcm_channel_info {
415 unsigned int channel;
416 __kernel_off_t offset;
417 unsigned int first;
418 unsigned int step;
419};
420
421enum {
422
423
424
425
426 SNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0,
427
428
429 SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1,
430 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2,
431 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3,
432 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4,
433 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5,
434 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED
435};
436
437struct snd_pcm_status {
438 snd_pcm_state_t state;
439 struct timespec trigger_tstamp;
440 struct timespec tstamp;
441 snd_pcm_uframes_t appl_ptr;
442 snd_pcm_uframes_t hw_ptr;
443 snd_pcm_sframes_t delay;
444 snd_pcm_uframes_t avail;
445 snd_pcm_uframes_t avail_max;
446 snd_pcm_uframes_t overrange;
447 snd_pcm_state_t suspended_state;
448 __u32 audio_tstamp_data;
449 struct timespec audio_tstamp;
450 struct timespec driver_tstamp;
451 __u32 audio_tstamp_accuracy;
452 unsigned char reserved[52-2*sizeof(struct timespec)];
453};
454
455struct snd_pcm_mmap_status {
456 snd_pcm_state_t state;
457 int pad1;
458 snd_pcm_uframes_t hw_ptr;
459 struct timespec tstamp;
460 snd_pcm_state_t suspended_state;
461 struct timespec audio_tstamp;
462};
463
464struct snd_pcm_mmap_control {
465 snd_pcm_uframes_t appl_ptr;
466 snd_pcm_uframes_t avail_min;
467};
468
469#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0)
470#define SNDRV_PCM_SYNC_PTR_APPL (1<<1)
471#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2)
472
473struct snd_pcm_sync_ptr {
474 unsigned int flags;
475 union {
476 struct snd_pcm_mmap_status status;
477 unsigned char reserved[64];
478 } s;
479 union {
480 struct snd_pcm_mmap_control control;
481 unsigned char reserved[64];
482 } c;
483};
484
485struct snd_xferi {
486 snd_pcm_sframes_t result;
487 void __user *buf;
488 snd_pcm_uframes_t frames;
489};
490
491struct snd_xfern {
492 snd_pcm_sframes_t result;
493 void __user * __user *bufs;
494 snd_pcm_uframes_t frames;
495};
496
497enum {
498 SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0,
499 SNDRV_PCM_TSTAMP_TYPE_MONOTONIC,
500 SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW,
501 SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW,
502};
503
504
505enum {
506 SNDRV_CHMAP_UNKNOWN = 0,
507 SNDRV_CHMAP_NA,
508 SNDRV_CHMAP_MONO,
509
510 SNDRV_CHMAP_FL,
511 SNDRV_CHMAP_FR,
512 SNDRV_CHMAP_RL,
513 SNDRV_CHMAP_RR,
514 SNDRV_CHMAP_FC,
515 SNDRV_CHMAP_LFE,
516 SNDRV_CHMAP_SL,
517 SNDRV_CHMAP_SR,
518 SNDRV_CHMAP_RC,
519
520 SNDRV_CHMAP_FLC,
521 SNDRV_CHMAP_FRC,
522 SNDRV_CHMAP_RLC,
523 SNDRV_CHMAP_RRC,
524 SNDRV_CHMAP_FLW,
525 SNDRV_CHMAP_FRW,
526 SNDRV_CHMAP_FLH,
527 SNDRV_CHMAP_FCH,
528 SNDRV_CHMAP_FRH,
529 SNDRV_CHMAP_TC,
530 SNDRV_CHMAP_TFL,
531 SNDRV_CHMAP_TFR,
532 SNDRV_CHMAP_TFC,
533 SNDRV_CHMAP_TRL,
534 SNDRV_CHMAP_TRR,
535 SNDRV_CHMAP_TRC,
536
537 SNDRV_CHMAP_TFLC,
538 SNDRV_CHMAP_TFRC,
539 SNDRV_CHMAP_TSL,
540 SNDRV_CHMAP_TSR,
541 SNDRV_CHMAP_LLFE,
542 SNDRV_CHMAP_RLFE,
543 SNDRV_CHMAP_BC,
544 SNDRV_CHMAP_BLC,
545 SNDRV_CHMAP_BRC,
546 SNDRV_CHMAP_LAST = SNDRV_CHMAP_BRC,
547};
548
549#define SNDRV_CHMAP_POSITION_MASK 0xffff
550#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16)
551#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16)
552
553#define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int)
554#define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info)
555#define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int)
556#define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int)
557#define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params)
558#define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params)
559#define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12)
560#define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params)
561#define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status)
562#define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t)
563#define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22)
564#define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr)
565#define SNDRV_PCM_IOCTL_STATUS_EXT _IOWR('A', 0x24, struct snd_pcm_status)
566#define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info)
567#define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40)
568#define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41)
569#define SNDRV_PCM_IOCTL_START _IO('A', 0x42)
570#define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43)
571#define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44)
572#define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int)
573#define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t)
574#define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47)
575#define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48)
576#define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t)
577#define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi)
578#define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi)
579#define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern)
580#define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern)
581#define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int)
582#define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61)
583
584
585
586
587
588
589
590
591
592
593
594#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0)
595
596enum {
597 SNDRV_RAWMIDI_STREAM_OUTPUT = 0,
598 SNDRV_RAWMIDI_STREAM_INPUT,
599 SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT,
600};
601
602#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001
603#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002
604#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004
605
606struct snd_rawmidi_info {
607 unsigned int device;
608 unsigned int subdevice;
609 int stream;
610 int card;
611 unsigned int flags;
612 unsigned char id[64];
613 unsigned char name[80];
614 unsigned char subname[32];
615 unsigned int subdevices_count;
616 unsigned int subdevices_avail;
617 unsigned char reserved[64];
618};
619
620struct snd_rawmidi_params {
621 int stream;
622 size_t buffer_size;
623 size_t avail_min;
624 unsigned int no_active_sensing: 1;
625 unsigned char reserved[16];
626};
627
628struct snd_rawmidi_status {
629 int stream;
630 struct timespec tstamp;
631 size_t avail;
632 size_t xruns;
633 unsigned char reserved[16];
634};
635
636#define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int)
637#define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info)
638#define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params)
639#define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status)
640#define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int)
641#define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int)
642
643
644
645
646
647#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6)
648
649enum {
650 SNDRV_TIMER_CLASS_NONE = -1,
651 SNDRV_TIMER_CLASS_SLAVE = 0,
652 SNDRV_TIMER_CLASS_GLOBAL,
653 SNDRV_TIMER_CLASS_CARD,
654 SNDRV_TIMER_CLASS_PCM,
655 SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM,
656};
657
658
659enum {
660 SNDRV_TIMER_SCLASS_NONE = 0,
661 SNDRV_TIMER_SCLASS_APPLICATION,
662 SNDRV_TIMER_SCLASS_SEQUENCER,
663 SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
664 SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
665};
666
667
668#define SNDRV_TIMER_GLOBAL_SYSTEM 0
669#define SNDRV_TIMER_GLOBAL_RTC 1
670#define SNDRV_TIMER_GLOBAL_HPET 2
671#define SNDRV_TIMER_GLOBAL_HRTIMER 3
672
673
674#define SNDRV_TIMER_FLG_SLAVE (1<<0)
675
676struct snd_timer_id {
677 int dev_class;
678 int dev_sclass;
679 int card;
680 int device;
681 int subdevice;
682};
683
684struct snd_timer_ginfo {
685 struct snd_timer_id tid;
686 unsigned int flags;
687 int card;
688 unsigned char id[64];
689 unsigned char name[80];
690 unsigned long reserved0;
691 unsigned long resolution;
692 unsigned long resolution_min;
693 unsigned long resolution_max;
694 unsigned int clients;
695 unsigned char reserved[32];
696};
697
698struct snd_timer_gparams {
699 struct snd_timer_id tid;
700 unsigned long period_num;
701 unsigned long period_den;
702 unsigned char reserved[32];
703};
704
705struct snd_timer_gstatus {
706 struct snd_timer_id tid;
707 unsigned long resolution;
708 unsigned long resolution_num;
709 unsigned long resolution_den;
710 unsigned char reserved[32];
711};
712
713struct snd_timer_select {
714 struct snd_timer_id id;
715 unsigned char reserved[32];
716};
717
718struct snd_timer_info {
719 unsigned int flags;
720 int card;
721 unsigned char id[64];
722 unsigned char name[80];
723 unsigned long reserved0;
724 unsigned long resolution;
725 unsigned char reserved[64];
726};
727
728#define SNDRV_TIMER_PSFLG_AUTO (1<<0)
729#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1)
730#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2)
731
732struct snd_timer_params {
733 unsigned int flags;
734 unsigned int ticks;
735 unsigned int queue_size;
736 unsigned int reserved0;
737 unsigned int filter;
738 unsigned char reserved[60];
739};
740
741struct snd_timer_status {
742 struct timespec tstamp;
743 unsigned int resolution;
744 unsigned int lost;
745 unsigned int overrun;
746 unsigned int queue;
747 unsigned char reserved[64];
748};
749
750#define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int)
751#define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id)
752#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int)
753#define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo)
754#define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams)
755#define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus)
756#define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select)
757#define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info)
758#define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params)
759#define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status)
760
761#define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0)
762#define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1)
763#define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2)
764#define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3)
765
766struct snd_timer_read {
767 unsigned int resolution;
768 unsigned int ticks;
769};
770
771enum {
772 SNDRV_TIMER_EVENT_RESOLUTION = 0,
773 SNDRV_TIMER_EVENT_TICK,
774 SNDRV_TIMER_EVENT_START,
775 SNDRV_TIMER_EVENT_STOP,
776 SNDRV_TIMER_EVENT_CONTINUE,
777 SNDRV_TIMER_EVENT_PAUSE,
778 SNDRV_TIMER_EVENT_EARLY,
779 SNDRV_TIMER_EVENT_SUSPEND,
780 SNDRV_TIMER_EVENT_RESUME,
781
782 SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10,
783 SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10,
784 SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10,
785 SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10,
786 SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10,
787 SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10,
788};
789
790struct snd_timer_tread {
791 int event;
792 struct timespec tstamp;
793 unsigned int val;
794};
795
796
797
798
799
800
801
802#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7)
803
804struct snd_ctl_card_info {
805 int card;
806 int pad;
807 unsigned char id[16];
808 unsigned char driver[16];
809 unsigned char name[32];
810 unsigned char longname[80];
811 unsigned char reserved_[16];
812 unsigned char mixername[80];
813 unsigned char components[128];
814};
815
816typedef int __bitwise snd_ctl_elem_type_t;
817#define SNDRV_CTL_ELEM_TYPE_NONE ((__force snd_ctl_elem_type_t) 0)
818#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((__force snd_ctl_elem_type_t) 1)
819#define SNDRV_CTL_ELEM_TYPE_INTEGER ((__force snd_ctl_elem_type_t) 2)
820#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((__force snd_ctl_elem_type_t) 3)
821#define SNDRV_CTL_ELEM_TYPE_BYTES ((__force snd_ctl_elem_type_t) 4)
822#define SNDRV_CTL_ELEM_TYPE_IEC958 ((__force snd_ctl_elem_type_t) 5)
823#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((__force snd_ctl_elem_type_t) 6)
824#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64
825
826typedef int __bitwise snd_ctl_elem_iface_t;
827#define SNDRV_CTL_ELEM_IFACE_CARD ((__force snd_ctl_elem_iface_t) 0)
828#define SNDRV_CTL_ELEM_IFACE_HWDEP ((__force snd_ctl_elem_iface_t) 1)
829#define SNDRV_CTL_ELEM_IFACE_MIXER ((__force snd_ctl_elem_iface_t) 2)
830#define SNDRV_CTL_ELEM_IFACE_PCM ((__force snd_ctl_elem_iface_t) 3)
831#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((__force snd_ctl_elem_iface_t) 4)
832#define SNDRV_CTL_ELEM_IFACE_TIMER ((__force snd_ctl_elem_iface_t) 5)
833#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((__force snd_ctl_elem_iface_t) 6)
834#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER
835
836#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0)
837#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1)
838#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE)
839#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2)
840#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<3)
841#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4)
842#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5)
843#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
844#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6)
845#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8)
846#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9)
847#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10)
848#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28)
849#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29)
850
851
852
853#define SNDRV_CTL_POWER_D0 0x0000
854#define SNDRV_CTL_POWER_D1 0x0100
855#define SNDRV_CTL_POWER_D2 0x0200
856#define SNDRV_CTL_POWER_D3 0x0300
857#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000)
858#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001)
859
860#define SNDRV_CTL_ELEM_ID_NAME_MAXLEN 44
861
862struct snd_ctl_elem_id {
863 unsigned int numid;
864 snd_ctl_elem_iface_t iface;
865 unsigned int device;
866 unsigned int subdevice;
867 unsigned char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
868 unsigned int index;
869};
870
871struct snd_ctl_elem_list {
872 unsigned int offset;
873 unsigned int space;
874 unsigned int used;
875 unsigned int count;
876 struct snd_ctl_elem_id __user *pids;
877 unsigned char reserved[50];
878};
879
880struct snd_ctl_elem_info {
881 struct snd_ctl_elem_id id;
882 snd_ctl_elem_type_t type;
883 unsigned int access;
884 unsigned int count;
885 __kernel_pid_t owner;
886 union {
887 struct {
888 long min;
889 long max;
890 long step;
891 } integer;
892 struct {
893 long long min;
894 long long max;
895 long long step;
896 } integer64;
897 struct {
898 unsigned int items;
899 unsigned int item;
900 char name[64];
901 __u64 names_ptr;
902 unsigned int names_length;
903 } enumerated;
904 unsigned char reserved[128];
905 } value;
906 union {
907 unsigned short d[4];
908 unsigned short *d_ptr;
909 } dimen;
910 unsigned char reserved[64-4*sizeof(unsigned short)];
911};
912
913struct snd_ctl_elem_value {
914 struct snd_ctl_elem_id id;
915 unsigned int indirect: 1;
916 union {
917 union {
918 long value[128];
919 long *value_ptr;
920 } integer;
921 union {
922 long long value[64];
923 long long *value_ptr;
924 } integer64;
925 union {
926 unsigned int item[128];
927 unsigned int *item_ptr;
928 } enumerated;
929 union {
930 unsigned char data[512];
931 unsigned char *data_ptr;
932 } bytes;
933 struct snd_aes_iec958 iec958;
934 } value;
935 struct timespec tstamp;
936 unsigned char reserved[128-sizeof(struct timespec)];
937};
938
939struct snd_ctl_tlv {
940 unsigned int numid;
941 unsigned int length;
942 unsigned int tlv[0];
943};
944
945#define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int)
946#define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info)
947#define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list)
948#define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info)
949#define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value)
950#define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value)
951#define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id)
952#define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id)
953#define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int)
954#define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info)
955#define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info)
956#define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id)
957#define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv)
958#define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv)
959#define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv)
960#define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int)
961#define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info)
962#define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int)
963#define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info)
964#define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int)
965#define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int)
966#define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info)
967#define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int)
968#define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int)
969#define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int)
970
971
972
973
974
975enum sndrv_ctl_event_type {
976 SNDRV_CTL_EVENT_ELEM = 0,
977 SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM,
978};
979
980#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0)
981#define SNDRV_CTL_EVENT_MASK_INFO (1<<1)
982#define SNDRV_CTL_EVENT_MASK_ADD (1<<2)
983#define SNDRV_CTL_EVENT_MASK_TLV (1<<3)
984#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U)
985
986struct snd_ctl_event {
987 int type;
988 union {
989 struct {
990 unsigned int mask;
991 struct snd_ctl_elem_id id;
992 } elem;
993 unsigned char data8[60];
994 } data;
995};
996
997
998
999
1000
1001#define SNDRV_CTL_NAME_NONE ""
1002#define SNDRV_CTL_NAME_PLAYBACK "Playback "
1003#define SNDRV_CTL_NAME_CAPTURE "Capture "
1004
1005#define SNDRV_CTL_NAME_IEC958_NONE ""
1006#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch"
1007#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume"
1008#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default"
1009#define SNDRV_CTL_NAME_IEC958_MASK "Mask"
1010#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask"
1011#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask"
1012#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream"
1013#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what
1014
1015#endif
1016