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22#ifndef _UAPI__SOUND_EMU10K1_H
23#define _UAPI__SOUND_EMU10K1_H
24
25#include <linux/types.h>
26#include <sound/asound.h>
27
28
29
30
31
32#define EMU10K1_CARD_CREATIVE 0x00000000
33#define EMU10K1_CARD_EMUAPS 0x00000001
34
35#define EMU10K1_FX8010_PCM_COUNT 8
36
37
38#define iMAC0 0x00
39#define iMAC1 0x01
40#define iMAC2 0x02
41#define iMAC3 0x03
42#define iMACINT0 0x04
43#define iMACINT1 0x05
44#define iACC3 0x06
45#define iMACMV 0x07
46#define iANDXOR 0x08
47#define iTSTNEG 0x09
48#define iLIMITGE 0x0a
49#define iLIMITLT 0x0b
50#define iLOG 0x0c
51#define iEXP 0x0d
52#define iINTERP 0x0e
53#define iSKIP 0x0f
54
55
56#define FXBUS(x) (0x00 + (x))
57#define EXTIN(x) (0x10 + (x))
58#define EXTOUT(x) (0x20 + (x))
59#define FXBUS2(x) (0x30 + (x))
60
61
62#define C_00000000 0x40
63#define C_00000001 0x41
64#define C_00000002 0x42
65#define C_00000003 0x43
66#define C_00000004 0x44
67#define C_00000008 0x45
68#define C_00000010 0x46
69#define C_00000020 0x47
70#define C_00000100 0x48
71#define C_00010000 0x49
72#define C_00080000 0x4a
73#define C_10000000 0x4b
74#define C_20000000 0x4c
75#define C_40000000 0x4d
76#define C_80000000 0x4e
77#define C_7fffffff 0x4f
78#define C_ffffffff 0x50
79#define C_fffffffe 0x51
80#define C_c0000000 0x52
81#define C_4f1bbcdc 0x53
82#define C_5a7ef9db 0x54
83#define C_00100000 0x55
84#define GPR_ACCU 0x56
85#define GPR_COND 0x57
86#define GPR_NOISE0 0x58
87#define GPR_NOISE1 0x59
88#define GPR_IRQ 0x5a
89#define GPR_DBAC 0x5b
90#define GPR(x) (FXGPREGBASE + (x))
91#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
92#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x))
93#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
94#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x))
95
96#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
97#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x))
98#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
99#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x))
100#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x))
101#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x))
102
103#define A_FXBUS(x) (0x00 + (x))
104#define A_EXTIN(x) (0x40 + (x))
105#define A_P16VIN(x) (0x50 + (x))
106#define A_EXTOUT(x) (0x60 + (x))
107#define A_FXBUS2(x) (0x80 + (x))
108#define A_EMU32OUTH(x) (0xa0 + (x))
109#define A_EMU32OUTL(x) (0xb0 + (x))
110#define A3_EMU32IN(x) (0x160 + (x))
111#define A3_EMU32OUT(x) (0x1E0 + (x))
112#define A_GPR(x) (A_FXGPREGBASE + (x))
113
114
115#define CC_REG_NORMALIZED C_00000001
116#define CC_REG_BORROW C_00000002
117#define CC_REG_MINUS C_00000004
118#define CC_REG_ZERO C_00000008
119#define CC_REG_SATURATE C_00000010
120#define CC_REG_NONZERO C_00000100
121
122
123#define FXBUS_PCM_LEFT 0x00
124#define FXBUS_PCM_RIGHT 0x01
125#define FXBUS_PCM_LEFT_REAR 0x02
126#define FXBUS_PCM_RIGHT_REAR 0x03
127#define FXBUS_MIDI_LEFT 0x04
128#define FXBUS_MIDI_RIGHT 0x05
129#define FXBUS_PCM_CENTER 0x06
130#define FXBUS_PCM_LFE 0x07
131#define FXBUS_PCM_LEFT_FRONT 0x08
132#define FXBUS_PCM_RIGHT_FRONT 0x09
133#define FXBUS_MIDI_REVERB 0x0c
134#define FXBUS_MIDI_CHORUS 0x0d
135#define FXBUS_PCM_LEFT_SIDE 0x0e
136#define FXBUS_PCM_RIGHT_SIDE 0x0f
137#define FXBUS_PT_LEFT 0x14
138#define FXBUS_PT_RIGHT 0x15
139
140
141#define EXTIN_AC97_L 0x00
142#define EXTIN_AC97_R 0x01
143#define EXTIN_SPDIF_CD_L 0x02
144#define EXTIN_SPDIF_CD_R 0x03
145#define EXTIN_ZOOM_L 0x04
146#define EXTIN_ZOOM_R 0x05
147#define EXTIN_TOSLINK_L 0x06
148#define EXTIN_TOSLINK_R 0x07
149#define EXTIN_LINE1_L 0x08
150#define EXTIN_LINE1_R 0x09
151#define EXTIN_COAX_SPDIF_L 0x0a
152#define EXTIN_COAX_SPDIF_R 0x0b
153#define EXTIN_LINE2_L 0x0c
154#define EXTIN_LINE2_R 0x0d
155
156
157#define EXTOUT_AC97_L 0x00
158#define EXTOUT_AC97_R 0x01
159#define EXTOUT_TOSLINK_L 0x02
160#define EXTOUT_TOSLINK_R 0x03
161#define EXTOUT_AC97_CENTER 0x04
162#define EXTOUT_AC97_LFE 0x05
163#define EXTOUT_HEADPHONE_L 0x06
164#define EXTOUT_HEADPHONE_R 0x07
165#define EXTOUT_REAR_L 0x08
166#define EXTOUT_REAR_R 0x09
167#define EXTOUT_ADC_CAP_L 0x0a
168#define EXTOUT_ADC_CAP_R 0x0b
169#define EXTOUT_MIC_CAP 0x0c
170#define EXTOUT_AC97_REAR_L 0x0d
171#define EXTOUT_AC97_REAR_R 0x0e
172#define EXTOUT_ACENTER 0x11
173#define EXTOUT_ALFE 0x12
174
175
176#define A_EXTIN_AC97_L 0x00
177#define A_EXTIN_AC97_R 0x01
178#define A_EXTIN_SPDIF_CD_L 0x02
179#define A_EXTIN_SPDIF_CD_R 0x03
180#define A_EXTIN_OPT_SPDIF_L 0x04
181#define A_EXTIN_OPT_SPDIF_R 0x05
182#define A_EXTIN_LINE2_L 0x08
183#define A_EXTIN_LINE2_R 0x09
184#define A_EXTIN_ADC_L 0x0a
185#define A_EXTIN_ADC_R 0x0b
186#define A_EXTIN_AUX2_L 0x0c
187#define A_EXTIN_AUX2_R 0x0d
188
189
190#define A_EXTOUT_FRONT_L 0x00
191#define A_EXTOUT_FRONT_R 0x01
192#define A_EXTOUT_CENTER 0x02
193#define A_EXTOUT_LFE 0x03
194#define A_EXTOUT_HEADPHONE_L 0x04
195#define A_EXTOUT_HEADPHONE_R 0x05
196#define A_EXTOUT_REAR_L 0x06
197#define A_EXTOUT_REAR_R 0x07
198#define A_EXTOUT_AFRONT_L 0x08
199#define A_EXTOUT_AFRONT_R 0x09
200#define A_EXTOUT_ACENTER 0x0a
201#define A_EXTOUT_ALFE 0x0b
202#define A_EXTOUT_ASIDE_L 0x0c
203#define A_EXTOUT_ASIDE_R 0x0d
204#define A_EXTOUT_AREAR_L 0x0e
205#define A_EXTOUT_AREAR_R 0x0f
206#define A_EXTOUT_AC97_L 0x10
207#define A_EXTOUT_AC97_R 0x11
208#define A_EXTOUT_ADC_CAP_L 0x16
209#define A_EXTOUT_ADC_CAP_R 0x17
210#define A_EXTOUT_MIC_CAP 0x18
211
212
213#define A_C_00000000 0xc0
214#define A_C_00000001 0xc1
215#define A_C_00000002 0xc2
216#define A_C_00000003 0xc3
217#define A_C_00000004 0xc4
218#define A_C_00000008 0xc5
219#define A_C_00000010 0xc6
220#define A_C_00000020 0xc7
221#define A_C_00000100 0xc8
222#define A_C_00010000 0xc9
223#define A_C_00000800 0xca
224#define A_C_10000000 0xcb
225#define A_C_20000000 0xcc
226#define A_C_40000000 0xcd
227#define A_C_80000000 0xce
228#define A_C_7fffffff 0xcf
229#define A_C_ffffffff 0xd0
230#define A_C_fffffffe 0xd1
231#define A_C_c0000000 0xd2
232#define A_C_4f1bbcdc 0xd3
233#define A_C_5a7ef9db 0xd4
234#define A_C_00100000 0xd5
235#define A_GPR_ACCU 0xd6
236#define A_GPR_COND 0xd7
237#define A_GPR_NOISE0 0xd8
238#define A_GPR_NOISE1 0xd9
239#define A_GPR_IRQ 0xda
240#define A_GPR_DBAC 0xdb
241#define A_GPR_DBACE 0xde
242
243
244#define EMU10K1_DBG_ZC 0x80000000
245#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000
246#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000
247#define EMU10K1_DBG_SINGLE_STEP 0x00008000
248#define EMU10K1_DBG_STEP 0x00004000
249#define EMU10K1_DBG_CONDITION_CODE 0x00003e00
250#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff
251
252
253#ifndef __KERNEL__
254#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
255#define TANKMEMADDRREG_CLEAR 0x00800000
256#define TANKMEMADDRREG_ALIGN 0x00400000
257#define TANKMEMADDRREG_WRITE 0x00200000
258#define TANKMEMADDRREG_READ 0x00100000
259#endif
260
261struct snd_emu10k1_fx8010_info {
262 unsigned int internal_tram_size;
263 unsigned int external_tram_size;
264 char fxbus_names[16][32];
265 char extin_names[16][32];
266 char extout_names[32][32];
267 unsigned int gpr_controls;
268};
269
270#define EMU10K1_GPR_TRANSLATION_NONE 0
271#define EMU10K1_GPR_TRANSLATION_TABLE100 1
272#define EMU10K1_GPR_TRANSLATION_BASS 2
273#define EMU10K1_GPR_TRANSLATION_TREBLE 3
274#define EMU10K1_GPR_TRANSLATION_ONOFF 4
275
276struct snd_emu10k1_fx8010_control_gpr {
277 struct snd_ctl_elem_id id;
278 unsigned int vcount;
279 unsigned int count;
280 unsigned short gpr[32];
281 unsigned int value[32];
282 unsigned int min;
283 unsigned int max;
284 unsigned int translation;
285 const unsigned int *tlv;
286};
287
288
289struct snd_emu10k1_fx8010_control_old_gpr {
290 struct snd_ctl_elem_id id;
291 unsigned int vcount;
292 unsigned int count;
293 unsigned short gpr[32];
294 unsigned int value[32];
295 unsigned int min;
296 unsigned int max;
297 unsigned int translation;
298};
299
300struct snd_emu10k1_fx8010_code {
301 char name[128];
302
303 DECLARE_BITMAP(gpr_valid, 0x200);
304 __u32 __user *gpr_map;
305
306 unsigned int gpr_add_control_count;
307 struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls;
308
309 unsigned int gpr_del_control_count;
310 struct snd_ctl_elem_id __user *gpr_del_controls;
311
312 unsigned int gpr_list_control_count;
313 unsigned int gpr_list_control_total;
314 struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls;
315
316 DECLARE_BITMAP(tram_valid, 0x100);
317 __u32 __user *tram_data_map;
318 __u32 __user *tram_addr_map;
319
320 DECLARE_BITMAP(code_valid, 1024);
321 __u32 __user *code;
322};
323
324struct snd_emu10k1_fx8010_tram {
325 unsigned int address;
326 unsigned int size;
327 unsigned int *samples;
328
329};
330
331struct snd_emu10k1_fx8010_pcm_rec {
332 unsigned int substream;
333 unsigned int res1;
334 unsigned int channels;
335 unsigned int tram_start;
336 unsigned int buffer_size;
337 unsigned short gpr_size;
338 unsigned short gpr_ptr;
339 unsigned short gpr_count;
340 unsigned short gpr_tmpcount;
341 unsigned short gpr_trigger;
342 unsigned short gpr_running;
343 unsigned char pad;
344 unsigned char etram[32];
345 unsigned int res2;
346};
347
348#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
349
350#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
351#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
352#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
353#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
354#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
355#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
356#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
357#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
358#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
359#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
360#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
361#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
362#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
363#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
364
365
366typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
367typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
368typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
369typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
370typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
371
372#endif
373