LXR linux/sound/pci/echoaudio/mona

   1/****************************************************************************
   2
   3   Copyright Echo Digital Audio Corporation (c) 1998 - 2004
   4   All rights reserved
   5   www.echoaudio.com
   6
   7   This file is part of Echo Digital Audio's generic driver library.
   8
   9   Echo Digital Audio's generic driver library is free software;
  10   you can redistribute it and/or modify it under the terms of
  11   the GNU General Public License as published by the Free Software
  12   Foundation.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; if not, write to the Free Software
  21   Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  22   MA  02111-1307, USA.
  23
  24   *************************************************************************
  25
  26 Translation from C++ and adaptation for use in ALSA-Driver
  27 were made by Giuliano Pochini <pochini@shiny.it>
  28
  29****************************************************************************/
  30
  31
  32static int write_control_reg(struct echoaudio *chip, u32 value, char force);
  33static int set_input_clock(struct echoaudio *chip, u16 clock);
  34static int set_professional_spdif(struct echoaudio *chip, char prof);
  35static int set_digital_mode(struct echoaudio *chip, u8 mode);
  36static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
  37static int check_asic_status(struct echoaudio *chip);
  38
  39
  40static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
  41{
  42        int err;
  43
  44        if (snd_BUG_ON((subdevice_id & 0xfff0) != MONA))
  45                return -ENODEV;
  46
  47        if ((err = init_dsp_comm_page(chip))) {
  48                dev_err(chip->card->dev,
  49                        "init_hw - could not initialize DSP comm page\n");
  50                return err;
  51        }
  52
  53        chip->device_id = device_id;
  54        chip->subdevice_id = subdevice_id;
  55        chip->bad_board = TRUE;
  56        chip->input_clock_types =
  57                ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
  58                ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
  59        chip->digital_modes =
  60                ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
  61                ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
  62                ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
  63
  64        /* Mona comes in both '301 and '361 flavors */
  65        if (chip->device_id == DEVICE_ID_56361)
  66                chip->dsp_code_to_load = FW_MONA_361_DSP;
  67        else
  68                chip->dsp_code_to_load = FW_MONA_301_DSP;
  69
  70        if ((err = load_firmware(chip)) < 0)
  71                return err;
  72        chip->bad_board = FALSE;
  73
  74        return err;
  75}
  76
  77
  78
  79static int set_mixer_defaults(struct echoaudio *chip)
  80{
  81        chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
  82        chip->professional_spdif = FALSE;
  83        chip->digital_in_automute = TRUE;
  84        return init_line_levels(chip);
  85}
  86
  87
  88
  89static u32 detect_input_clocks(const struct echoaudio *chip)
  90{
  91        u32 clocks_from_dsp, clock_bits;
  92
  93        /* Map the DSP clock detect bits to the generic driver clock
  94           detect bits */
  95        clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
  96
  97        clock_bits = ECHO_CLOCK_BIT_INTERNAL;
  98
  99        if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
 100                clock_bits |= ECHO_CLOCK_BIT_SPDIF;
 101
 102        if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
 103                clock_bits |= ECHO_CLOCK_BIT_ADAT;
 104
 105        if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
 106                clock_bits |= ECHO_CLOCK_BIT_WORD;
 107
 108        return clock_bits;
 109}
 110
 111
 112
 113/* Mona has an ASIC on the PCI card and another ASIC in the external box; 
 114both need to be loaded. */
 115static int load_asic(struct echoaudio *chip)
 116{
 117        u32 control_reg;
 118        int err;
 119        short asic;
 120
 121        if (chip->asic_loaded)
 122                return 0;
 123
 124        mdelay(10);
 125
 126        if (chip->device_id == DEVICE_ID_56361)
 127                asic = FW_MONA_361_1_ASIC48;
 128        else
 129                asic = FW_MONA_301_1_ASIC48;
 130
 131        err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic);
 132        if (err < 0)
 133                return err;
 134
 135        chip->asic_code = asic;
 136        mdelay(10);
 137
 138        /* Do the external one */
 139        err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC,
 140                                FW_MONA_2_ASIC);
 141        if (err < 0)
 142                return err;
 143
 144        mdelay(10);
 145        err = check_asic_status(chip);
 146
 147        /* Set up the control register if the load succeeded -
 148           48 kHz, internal clock, S/PDIF RCA mode */
 149        if (!err) {
 150                control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
 151                err = write_control_reg(chip, control_reg, TRUE);
 152        }
 153
 154        return err;
 155}
 156
 157
 158
 159/* Depending on what digital mode you want, Mona needs different ASICs
 160loaded.  This function checks the ASIC needed for the new mode and sees
 161if it matches the one already loaded. */
 162static int switch_asic(struct echoaudio *chip, char double_speed)
 163{
 164        int err;
 165        short asic;
 166
 167        /* Check the clock detect bits to see if this is
 168        a single-speed clock or a double-speed clock; load
 169        a new ASIC if necessary. */
 170        if (chip->device_id == DEVICE_ID_56361) {
 171                if (double_speed)
 172                        asic = FW_MONA_361_1_ASIC96;
 173                else
 174                        asic = FW_MONA_361_1_ASIC48;
 175        } else {
 176                if (double_speed)
 177                        asic = FW_MONA_301_1_ASIC96;
 178                else
 179                        asic = FW_MONA_301_1_ASIC48;
 180        }
 181
 182        if (asic != chip->asic_code) {
 183                /* Load the desired ASIC */
 184                err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
 185                                        asic);
 186                if (err < 0)
 187                        return err;
 188                chip->asic_code = asic;
 189        }
 190
 191        return 0;
 192}
 193
 194
 195
 196static int set_sample_rate(struct echoaudio *chip, u32 rate)
 197{
 198        u32 control_reg, clock;
 199        short asic;
 200        char force_write;
 201
 202        /* Only set the clock for internal mode. */
 203        if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
 204                dev_dbg(chip->card->dev,
 205                        "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
 206                /* Save the rate anyhow */
 207                chip->comm_page->sample_rate = cpu_to_le32(rate);
 208                chip->sample_rate = rate;
 209                return 0;
 210        }
 211
 212        /* Now, check to see if the required ASIC is loaded */
 213        if (rate >= 88200) {
 214                if (chip->digital_mode == DIGITAL_MODE_ADAT)
 215                        return -EINVAL;
 216                if (chip->device_id == DEVICE_ID_56361)
 217                        asic = FW_MONA_361_1_ASIC96;
 218                else
 219                        asic = FW_MONA_301_1_ASIC96;
 220        } else {
 221                if (chip->device_id == DEVICE_ID_56361)
 222                        asic = FW_MONA_361_1_ASIC48;
 223                else
 224                        asic = FW_MONA_301_1_ASIC48;
 225        }
 226
 227        force_write = 0;
 228        if (asic != chip->asic_code) {
 229                int err;
 230                /* Load the desired ASIC (load_asic_generic() can sleep) */
 231                spin_unlock_irq(&chip->lock);
 232                err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
 233                                        asic);
 234                spin_lock_irq(&chip->lock);
 235
 236                if (err < 0)
 237                        return err;
 238                chip->asic_code = asic;
 239                force_write = 1;
 240        }
 241
 242        /* Compute the new control register value */
 243        clock = 0;
 244        control_reg = le32_to_cpu(chip->comm_page->control_register);
 245        control_reg &= GML_CLOCK_CLEAR_MASK;
 246        control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
 247
 248        switch (rate) {
 249        case 96000:
 250                clock = GML_96KHZ;
 251                break;
 252        case 88200:
 253                clock = GML_88KHZ;
 254                break;
 255        case 48000:
 256                clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
 257                break;
 258        case 44100:
 259                clock = GML_44KHZ;
 260                /* Professional mode */
 261                if (control_reg & GML_SPDIF_PRO_MODE)
 262                        clock |= GML_SPDIF_SAMPLE_RATE0;
 263                break;
 264        case 32000:
 265                clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
 266                        GML_SPDIF_SAMPLE_RATE1;
 267                break;
 268        case 22050:
 269                clock = GML_22KHZ;
 270                break;
 271        case 16000:
 272                clock = GML_16KHZ;
 273                break;
 274        case 11025:
 275                clock = GML_11KHZ;
 276                break;
 277        case 8000:
 278                clock = GML_8KHZ;
 279                break;
 280        default:
 281                dev_err(chip->card->dev,
 282                        "set_sample_rate: %d invalid!\n", rate);
 283                return -EINVAL;
 284        }
 285
 286        control_reg |= clock;
 287
 288        chip->comm_page->sample_rate = cpu_to_le32(rate);       /* ignored by the DSP */
 289        chip->sample_rate = rate;
 290        dev_dbg(chip->card->dev,
 291                "set_sample_rate: %d clock %d\n", rate, clock);
 292
 293        return write_control_reg(chip, control_reg, force_write);
 294}
 295
 296
 297
 298static int set_input_clock(struct echoaudio *chip, u16 clock)
 299{
 300        u32 control_reg, clocks_from_dsp;
 301        int err;
 302
 303
 304        /* Prevent two simultaneous calls to switch_asic() */
 305        if (atomic_read(&chip->opencount))
 306                return -EAGAIN;
 307
 308        /* Mask off the clock select bits */
 309        control_reg = le32_to_cpu(chip->comm_page->control_register) &
 310                GML_CLOCK_CLEAR_MASK;
 311        clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
 312
 313        switch (clock) {
 314        case ECHO_CLOCK_INTERNAL:
 315                chip->input_clock = ECHO_CLOCK_INTERNAL;
 316                return set_sample_rate(chip, chip->sample_rate);
 317        case ECHO_CLOCK_SPDIF:
 318                if (chip->digital_mode == DIGITAL_MODE_ADAT)
 319                        return -EAGAIN;
 320                spin_unlock_irq(&chip->lock);
 321                err = switch_asic(chip, clocks_from_dsp &
 322                                  GML_CLOCK_DETECT_BIT_SPDIF96);
 323                spin_lock_irq(&chip->lock);
 324                if (err < 0)
 325                        return err;
 326                control_reg |= GML_SPDIF_CLOCK;
 327                if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
 328                        control_reg |= GML_DOUBLE_SPEED_MODE;
 329                else
 330                        control_reg &= ~GML_DOUBLE_SPEED_MODE;
 331                break;
 332        case ECHO_CLOCK_WORD:
 333                spin_unlock_irq(&chip->lock);
 334                err = switch_asic(chip, clocks_from_dsp &
 335                                  GML_CLOCK_DETECT_BIT_WORD96);
 336                spin_lock_irq(&chip->lock);
 337                if (err < 0)
 338                        return err;
 339                control_reg |= GML_WORD_CLOCK;
 340                if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
 341                        control_reg |= GML_DOUBLE_SPEED_MODE;
 342                else
 343                        control_reg &= ~GML_DOUBLE_SPEED_MODE;
 344                break;
 345        case ECHO_CLOCK_ADAT:
 346                dev_dbg(chip->card->dev, "Set Mona clock to ADAT\n");
 347                if (chip->digital_mode != DIGITAL_MODE_ADAT)
 348                        return -EAGAIN;
 349                control_reg |= GML_ADAT_CLOCK;
 350                control_reg &= ~GML_DOUBLE_SPEED_MODE;
 351                break;
 352        default:
 353                dev_err(chip->card->dev,
 354                        "Input clock 0x%x not supported for Mona\n", clock);
 355                return -EINVAL;
 356        }
 357
 358        chip->input_clock = clock;
 359        return write_control_reg(chip, control_reg, TRUE);
 360}
 361
 362
 363
 364static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
 365{
 366        u32 control_reg;
 367        int err, incompatible_clock;
 368
 369        /* Set clock to "internal" if it's not compatible with the new mode */
 370        incompatible_clock = FALSE;
 371        switch (mode) {
 372        case DIGITAL_MODE_SPDIF_OPTICAL:
 373        case DIGITAL_MODE_SPDIF_RCA:
 374                if (chip->input_clock == ECHO_CLOCK_ADAT)
 375                        incompatible_clock = TRUE;
 376                break;
 377        case DIGITAL_MODE_ADAT:
 378                if (chip->input_clock == ECHO_CLOCK_SPDIF)
 379                        incompatible_clock = TRUE;
 380                break;
 381        default:
 382                dev_err(chip->card->dev,
 383                        "Digital mode not supported: %d\n", mode);
 384                return -EINVAL;
 385        }
 386
 387        spin_lock_irq(&chip->lock);
 388
 389        if (incompatible_clock) {       /* Switch to 48KHz, internal */
 390                chip->sample_rate = 48000;
 391                set_input_clock(chip, ECHO_CLOCK_INTERNAL);
 392        }
 393
 394        /* Clear the current digital mode */
 395        control_reg = le32_to_cpu(chip->comm_page->control_register);
 396        control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
 397
 398        /* Tweak the control reg */
 399        switch (mode) {
 400        case DIGITAL_MODE_SPDIF_OPTICAL:
 401                control_reg |= GML_SPDIF_OPTICAL_MODE;
 402                break;
 403        case DIGITAL_MODE_SPDIF_RCA:
 404                /* GML_SPDIF_OPTICAL_MODE bit cleared */
 405                break;
 406        case DIGITAL_MODE_ADAT:
 407                /* If the current ASIC is the 96KHz ASIC, switch the ASIC
 408                   and set to 48 KHz */
 409                if (chip->asic_code == FW_MONA_361_1_ASIC96 ||
 410                    chip->asic_code == FW_MONA_301_1_ASIC96) {
 411                        set_sample_rate(chip, 48000);
 412                }
 413                control_reg |= GML_ADAT_MODE;
 414                control_reg &= ~GML_DOUBLE_SPEED_MODE;
 415                break;
 416        }
 417
 418        err = write_control_reg(chip, control_reg, FALSE);
 419        spin_unlock_irq(&chip->lock);
 420        if (err < 0)
 421                return err;
 422        chip->digital_mode = mode;
 423
 424        dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);
 425        return incompatible_clock;
 426}
 427