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10#ifndef _ASM_IA64_SN_BTE_H
11#define _ASM_IA64_SN_BTE_H
12
13#include <linux/timer.h>
14#include <linux/spinlock.h>
15#include <linux/cache.h>
16#include <asm/sn/pda.h>
17#include <asm/sn/types.h>
18#include <asm/sn/shub_mmr.h>
19
20struct nodepda_s;
21
22#define IBCT_NOTIFY (0x1UL << 4)
23#define IBCT_ZFIL_MODE (0x1UL << 0)
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26
27
28#ifdef BTE_DEBUG
29# define BTE_PRINTK(x) printk x
30# ifdef BTE_DEBUG_VERBOSE
31# define BTE_PRINTKV(x) printk x
32# else
33# define BTE_PRINTKV(x)
34# endif
35#else
36# define BTE_PRINTK(x)
37# define BTE_PRINTKV(x)
38#endif
39
40
41
42#define BTE_LEN_BITS (16)
43#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
44#define BTE_MAX_XFER (BTE_LEN_MASK << L1_CACHE_SHIFT)
45
46
47
48#define BTES_PER_NODE (is_shub2() ? 4 : 2)
49#define MAX_BTES_PER_NODE 4
50
51#define BTE2OFF_CTRL 0
52#define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
53#define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
54#define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
55
56#define BTE_BASE_ADDR(interface) \
57 (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \
58 (interface == 1) ? SH2_BT_ENG_CSR_1 : \
59 (interface == 2) ? SH2_BT_ENG_CSR_2 : \
60 SH2_BT_ENG_CSR_3 \
61 : (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
62
63#define BTE_SOURCE_ADDR(base) \
64 (is_shub2() ? base + (BTE2OFF_SRC/8) \
65 : base + (BTEOFF_SRC/8))
66
67#define BTE_DEST_ADDR(base) \
68 (is_shub2() ? base + (BTE2OFF_DEST/8) \
69 : base + (BTEOFF_DEST/8))
70
71#define BTE_CTRL_ADDR(base) \
72 (is_shub2() ? base + (BTE2OFF_CTRL/8) \
73 : base + (BTEOFF_CTRL/8))
74
75#define BTE_NOTIF_ADDR(base) \
76 (is_shub2() ? base + (BTE2OFF_NOTIFY/8) \
77 : base + (BTEOFF_NOTIFY/8))
78
79
80#define BTE_NOTIFY IBCT_NOTIFY
81#define BTE_NORMAL BTE_NOTIFY
82#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
83
84#define BTE_WACQUIRE 0x4000
85
86#define BTE_USE_DEST (BTE_WACQUIRE << 1)
87
88#define BTE_USE_ANY (BTE_USE_DEST << 1)
89
90#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
91
92#define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR)
93#define BTE_WORD_AVAILABLE (IBLS_BUSY << 1)
94#define BTE_WORD_BUSY (~BTE_WORD_AVAILABLE)
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99
100#define BTE_LNSTAT_LOAD(_bte) \
101 HUB_L(_bte->bte_base_addr)
102#define BTE_LNSTAT_STORE(_bte, _x) \
103 HUB_S(_bte->bte_base_addr, (_x))
104#define BTE_SRC_STORE(_bte, _x) \
105({ \
106 u64 __addr = ((_x) & ~AS_MASK); \
107 if (is_shub2()) \
108 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
109 HUB_S(_bte->bte_source_addr, __addr); \
110})
111#define BTE_DEST_STORE(_bte, _x) \
112({ \
113 u64 __addr = ((_x) & ~AS_MASK); \
114 if (is_shub2()) \
115 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
116 HUB_S(_bte->bte_destination_addr, __addr); \
117})
118#define BTE_CTRL_STORE(_bte, _x) \
119 HUB_S(_bte->bte_control_addr, (_x))
120#define BTE_NOTIF_STORE(_bte, _x) \
121({ \
122 u64 __addr = ia64_tpa((_x) & ~AS_MASK); \
123 if (is_shub2()) \
124 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
125 HUB_S(_bte->bte_notify_addr, __addr); \
126})
127
128#define BTE_START_TRANSFER(_bte, _len, _mode) \
129 is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
130 : BTE_LNSTAT_STORE(_bte, _len); \
131 BTE_CTRL_STORE(_bte, _mode)
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139
140#define BTEFAIL_OFFSET 1
141
142typedef enum {
143 BTE_SUCCESS,
144 BTEFAIL_DIR,
145 BTEFAIL_POISON,
146 BTEFAIL_WERR,
147 BTEFAIL_ACCESS,
148 BTEFAIL_PWERR,
149 BTEFAIL_PRERR,
150 BTEFAIL_TOUT,
151 BTEFAIL_XTERR,
152 BTEFAIL_NOTAVAIL,
153} bte_result_t;
154
155#define BTEFAIL_SH2_RESP_SHORT 0x1
156#define BTEFAIL_SH2_RESP_LONG 0x2
157#define BTEFAIL_SH2_RESP_DSP 0x4
158#define BTEFAIL_SH2_RESP_ACCESS 0x8
159#define BTEFAIL_SH2_CRB_TO 0x10
160#define BTEFAIL_SH2_NACK_LIMIT 0x20
161#define BTEFAIL_SH2_ALL 0x3F
162
163#define BTE_ERR_BITS 0x3FUL
164#define BTE_ERR_SHIFT 36
165#define BTE_ERR_MASK (BTE_ERR_BITS << BTE_ERR_SHIFT)
166
167#define BTE_ERROR_RETRY(value) \
168 (is_shub2() ? (value != BTEFAIL_SH2_CRB_TO) \
169 : (value != BTEFAIL_TOUT))
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173
174#define BTE_SHUB2_ERROR(_status) \
175 ((_status & BTE_ERR_MASK) \
176 ? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \
177 : _status)
178
179#define BTE_GET_ERROR_STATUS(_status) \
180 (BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR)
181
182#define BTE_VALID_SH2_ERROR(value) \
183 ((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL))
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191
192struct bteinfo_s {
193 volatile u64 notify ____cacheline_aligned;
194 u64 *bte_base_addr ____cacheline_aligned;
195 u64 *bte_source_addr;
196 u64 *bte_destination_addr;
197 u64 *bte_control_addr;
198 u64 *bte_notify_addr;
199 spinlock_t spinlock;
200 cnodeid_t bte_cnode;
201 int bte_error_count;
202 int bte_num;
203 int cleanup_active;
204 volatile bte_result_t bh_error;
205 volatile u64 *most_rcnt_na;
206 struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
207};
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213extern bte_result_t bte_copy(u64, u64, u64, u64, void *);
214extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64);
215extern void bte_error_handler(struct nodepda_s *);
216
217#define bte_zero(dest, len, mode, notification) \
218 bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
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228#define BTE_UNALIGNED_COPY(src, dest, len, mode) \
229 (((len & (L1_CACHE_BYTES - 1)) || \
230 (src & (L1_CACHE_BYTES - 1)) || \
231 (dest & (L1_CACHE_BYTES - 1))) ? \
232 bte_unaligned_copy(src, dest, len, mode) : \
233 bte_copy(src, dest, len, mode, NULL))
234
235
236#endif
237