linux/drivers/clk/sunxi/clk-sunxi.c
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   1/*
   2 * Copyright 2013 Emilio López
   3 *
   4 * Emilio López <emilio@elopez.com.ar>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 */
  16
  17#include <linux/clk.h>
  18#include <linux/clk-provider.h>
  19#include <linux/clkdev.h>
  20#include <linux/of.h>
  21#include <linux/of_address.h>
  22#include <linux/reset-controller.h>
  23#include <linux/slab.h>
  24#include <linux/spinlock.h>
  25#include <linux/log2.h>
  26
  27#include "clk-factors.h"
  28
  29static DEFINE_SPINLOCK(clk_lock);
  30
  31/* Maximum number of parents our clocks have */
  32#define SUNXI_MAX_PARENTS       5
  33
  34/**
  35 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
  36 * PLL1 rate is calculated as follows
  37 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
  38 * parent_rate is always 24Mhz
  39 */
  40
  41static void sun4i_get_pll1_factors(struct factors_request *req)
  42{
  43        u8 div;
  44
  45        /* Normalize value to a 6M multiple */
  46        div = req->rate / 6000000;
  47        req->rate = 6000000 * div;
  48
  49        /* m is always zero for pll1 */
  50        req->m = 0;
  51
  52        /* k is 1 only on these cases */
  53        if (req->rate >= 768000000 || req->rate == 42000000 ||
  54                        req->rate == 54000000)
  55                req->k = 1;
  56        else
  57                req->k = 0;
  58
  59        /* p will be 3 for divs under 10 */
  60        if (div < 10)
  61                req->p = 3;
  62
  63        /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
  64        else if (div < 20 || (div < 32 && (div & 1)))
  65                req->p = 2;
  66
  67        /* p will be 1 for even divs under 32, divs under 40 and odd pairs
  68         * of divs between 40-62 */
  69        else if (div < 40 || (div < 64 && (div & 2)))
  70                req->p = 1;
  71
  72        /* any other entries have p = 0 */
  73        else
  74                req->p = 0;
  75
  76        /* calculate a suitable n based on k and p */
  77        div <<= req->p;
  78        div /= (req->k + 1);
  79        req->n = div / 4;
  80}
  81
  82/**
  83 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
  84 * PLL1 rate is calculated as follows
  85 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
  86 * parent_rate should always be 24MHz
  87 */
  88static void sun6i_a31_get_pll1_factors(struct factors_request *req)
  89{
  90        /*
  91         * We can operate only on MHz, this will make our life easier
  92         * later.
  93         */
  94        u32 freq_mhz = req->rate / 1000000;
  95        u32 parent_freq_mhz = req->parent_rate / 1000000;
  96
  97        /*
  98         * Round down the frequency to the closest multiple of either
  99         * 6 or 16
 100         */
 101        u32 round_freq_6 = round_down(freq_mhz, 6);
 102        u32 round_freq_16 = round_down(freq_mhz, 16);
 103
 104        if (round_freq_6 > round_freq_16)
 105                freq_mhz = round_freq_6;
 106        else
 107                freq_mhz = round_freq_16;
 108
 109        req->rate = freq_mhz * 1000000;
 110
 111        /* If the frequency is a multiple of 32 MHz, k is always 3 */
 112        if (!(freq_mhz % 32))
 113                req->k = 3;
 114        /* If the frequency is a multiple of 9 MHz, k is always 2 */
 115        else if (!(freq_mhz % 9))
 116                req->k = 2;
 117        /* If the frequency is a multiple of 8 MHz, k is always 1 */
 118        else if (!(freq_mhz % 8))
 119                req->k = 1;
 120        /* Otherwise, we don't use the k factor */
 121        else
 122                req->k = 0;
 123
 124        /*
 125         * If the frequency is a multiple of 2 but not a multiple of
 126         * 3, m is 3. This is the first time we use 6 here, yet we
 127         * will use it on several other places.
 128         * We use this number because it's the lowest frequency we can
 129         * generate (with n = 0, k = 0, m = 3), so every other frequency
 130         * somehow relates to this frequency.
 131         */
 132        if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
 133                req->m = 2;
 134        /*
 135         * If the frequency is a multiple of 6MHz, but the factor is
 136         * odd, m will be 3
 137         */
 138        else if ((freq_mhz / 6) & 1)
 139                req->m = 3;
 140        /* Otherwise, we end up with m = 1 */
 141        else
 142                req->m = 1;
 143
 144        /* Calculate n thanks to the above factors we already got */
 145        req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz)
 146                 - 1;
 147
 148        /*
 149         * If n end up being outbound, and that we can still decrease
 150         * m, do it.
 151         */
 152        if ((req->n + 1) > 31 && (req->m + 1) > 1) {
 153                req->n = (req->n + 1) / 2 - 1;
 154                req->m = (req->m + 1) / 2 - 1;
 155        }
 156}
 157
 158/**
 159 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
 160 * PLL1 rate is calculated as follows
 161 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
 162 * parent_rate is always 24Mhz
 163 */
 164
 165static void sun8i_a23_get_pll1_factors(struct factors_request *req)
 166{
 167        u8 div;
 168
 169        /* Normalize value to a 6M multiple */
 170        div = req->rate / 6000000;
 171        req->rate = 6000000 * div;
 172
 173        /* m is always zero for pll1 */
 174        req->m = 0;
 175
 176        /* k is 1 only on these cases */
 177        if (req->rate >= 768000000 || req->rate == 42000000 ||
 178                        req->rate == 54000000)
 179                req->k = 1;
 180        else
 181                req->k = 0;
 182
 183        /* p will be 2 for divs under 20 and odd divs under 32 */
 184        if (div < 20 || (div < 32 && (div & 1)))
 185                req->p = 2;
 186
 187        /* p will be 1 for even divs under 32, divs under 40 and odd pairs
 188         * of divs between 40-62 */
 189        else if (div < 40 || (div < 64 && (div & 2)))
 190                req->p = 1;
 191
 192        /* any other entries have p = 0 */
 193        else
 194                req->p = 0;
 195
 196        /* calculate a suitable n based on k and p */
 197        div <<= req->p;
 198        div /= (req->k + 1);
 199        req->n = div / 4 - 1;
 200}
 201
 202/**
 203 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
 204 * PLL5 rate is calculated as follows
 205 * rate = parent_rate * n * (k + 1)
 206 * parent_rate is always 24Mhz
 207 */
 208
 209static void sun4i_get_pll5_factors(struct factors_request *req)
 210{
 211        u8 div;
 212
 213        /* Normalize value to a parent_rate multiple (24M) */
 214        div = req->rate / req->parent_rate;
 215        req->rate = req->parent_rate * div;
 216
 217        if (div < 31)
 218                req->k = 0;
 219        else if (div / 2 < 31)
 220                req->k = 1;
 221        else if (div / 3 < 31)
 222                req->k = 2;
 223        else
 224                req->k = 3;
 225
 226        req->n = DIV_ROUND_UP(div, (req->k + 1));
 227}
 228
 229/**
 230 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
 231 * PLL6x2 rate is calculated as follows
 232 * rate = parent_rate * (n + 1) * (k + 1)
 233 * parent_rate is always 24Mhz
 234 */
 235
 236static void sun6i_a31_get_pll6_factors(struct factors_request *req)
 237{
 238        u8 div;
 239
 240        /* Normalize value to a parent_rate multiple (24M) */
 241        div = req->rate / req->parent_rate;
 242        req->rate = req->parent_rate * div;
 243
 244        req->k = div / 32;
 245        if (req->k > 3)
 246                req->k = 3;
 247
 248        req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
 249}
 250
 251/**
 252 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
 253 * AHB rate is calculated as follows
 254 * rate = parent_rate >> p
 255 */
 256
 257static void sun5i_a13_get_ahb_factors(struct factors_request *req)
 258{
 259        u32 div;
 260
 261        /* divide only */
 262        if (req->parent_rate < req->rate)
 263                req->rate = req->parent_rate;
 264
 265        /*
 266         * user manual says valid speed is 8k ~ 276M, but tests show it
 267         * can work at speeds up to 300M, just after reparenting to pll6
 268         */
 269        if (req->rate < 8000)
 270                req->rate = 8000;
 271        if (req->rate > 300000000)
 272                req->rate = 300000000;
 273
 274        div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
 275
 276        /* p = 0 ~ 3 */
 277        if (div > 3)
 278                div = 3;
 279
 280        req->rate = req->parent_rate >> div;
 281
 282        req->p = div;
 283}
 284
 285#define SUN6I_AHB1_PARENT_PLL6  3
 286
 287/**
 288 * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
 289 * AHB rate is calculated as follows
 290 * rate = parent_rate >> p
 291 *
 292 * if parent is pll6, then
 293 * parent_rate = pll6 rate / (m + 1)
 294 */
 295
 296static void sun6i_get_ahb1_factors(struct factors_request *req)
 297{
 298        u8 div, calcp, calcm = 1;
 299
 300        /*
 301         * clock can only divide, so we will never be able to achieve
 302         * frequencies higher than the parent frequency
 303         */
 304        if (req->parent_rate && req->rate > req->parent_rate)
 305                req->rate = req->parent_rate;
 306
 307        div = DIV_ROUND_UP(req->parent_rate, req->rate);
 308
 309        /* calculate pre-divider if parent is pll6 */
 310        if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
 311                if (div < 4)
 312                        calcp = 0;
 313                else if (div / 2 < 4)
 314                        calcp = 1;
 315                else if (div / 4 < 4)
 316                        calcp = 2;
 317                else
 318                        calcp = 3;
 319
 320                calcm = DIV_ROUND_UP(div, 1 << calcp);
 321        } else {
 322                calcp = __roundup_pow_of_two(div);
 323                calcp = calcp > 3 ? 3 : calcp;
 324        }
 325
 326        req->rate = (req->parent_rate / calcm) >> calcp;
 327        req->p = calcp;
 328        req->m = calcm - 1;
 329}
 330
 331/**
 332 * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
 333 *                       parent index
 334 */
 335static void sun6i_ahb1_recalc(struct factors_request *req)
 336{
 337        req->rate = req->parent_rate;
 338
 339        /* apply pre-divider first if parent is pll6 */
 340        if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
 341                req->rate /= req->m + 1;
 342
 343        /* clk divider */
 344        req->rate >>= req->p;
 345}
 346
 347/**
 348 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
 349 * APB1 rate is calculated as follows
 350 * rate = (parent_rate >> p) / (m + 1);
 351 */
 352
 353static void sun4i_get_apb1_factors(struct factors_request *req)
 354{
 355        u8 calcm, calcp;
 356        int div;
 357
 358        if (req->parent_rate < req->rate)
 359                req->rate = req->parent_rate;
 360
 361        div = DIV_ROUND_UP(req->parent_rate, req->rate);
 362
 363        /* Invalid rate! */
 364        if (div > 32)
 365                return;
 366
 367        if (div <= 4)
 368                calcp = 0;
 369        else if (div <= 8)
 370                calcp = 1;
 371        else if (div <= 16)
 372                calcp = 2;
 373        else
 374                calcp = 3;
 375
 376        calcm = (div >> calcp) - 1;
 377
 378        req->rate = (req->parent_rate >> calcp) / (calcm + 1);
 379        req->m = calcm;
 380        req->p = calcp;
 381}
 382
 383
 384
 385
 386/**
 387 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
 388 * CLK_OUT rate is calculated as follows
 389 * rate = (parent_rate >> p) / (m + 1);
 390 */
 391
 392static void sun7i_a20_get_out_factors(struct factors_request *req)
 393{
 394        u8 div, calcm, calcp;
 395
 396        /* These clocks can only divide, so we will never be able to achieve
 397         * frequencies higher than the parent frequency */
 398        if (req->rate > req->parent_rate)
 399                req->rate = req->parent_rate;
 400
 401        div = DIV_ROUND_UP(req->parent_rate, req->rate);
 402
 403        if (div < 32)
 404                calcp = 0;
 405        else if (div / 2 < 32)
 406                calcp = 1;
 407        else if (div / 4 < 32)
 408                calcp = 2;
 409        else
 410                calcp = 3;
 411
 412        calcm = DIV_ROUND_UP(div, 1 << calcp);
 413
 414        req->rate = (req->parent_rate >> calcp) / calcm;
 415        req->m = calcm - 1;
 416        req->p = calcp;
 417}
 418
 419/**
 420 * sunxi_factors_clk_setup() - Setup function for factor clocks
 421 */
 422
 423static const struct clk_factors_config sun4i_pll1_config = {
 424        .nshift = 8,
 425        .nwidth = 5,
 426        .kshift = 4,
 427        .kwidth = 2,
 428        .mshift = 0,
 429        .mwidth = 2,
 430        .pshift = 16,
 431        .pwidth = 2,
 432};
 433
 434static const struct clk_factors_config sun6i_a31_pll1_config = {
 435        .nshift = 8,
 436        .nwidth = 5,
 437        .kshift = 4,
 438        .kwidth = 2,
 439        .mshift = 0,
 440        .mwidth = 2,
 441        .n_start = 1,
 442};
 443
 444static const struct clk_factors_config sun8i_a23_pll1_config = {
 445        .nshift = 8,
 446        .nwidth = 5,
 447        .kshift = 4,
 448        .kwidth = 2,
 449        .mshift = 0,
 450        .mwidth = 2,
 451        .pshift = 16,
 452        .pwidth = 2,
 453        .n_start = 1,
 454};
 455
 456static const struct clk_factors_config sun4i_pll5_config = {
 457        .nshift = 8,
 458        .nwidth = 5,
 459        .kshift = 4,
 460        .kwidth = 2,
 461};
 462
 463static const struct clk_factors_config sun6i_a31_pll6_config = {
 464        .nshift = 8,
 465        .nwidth = 5,
 466        .kshift = 4,
 467        .kwidth = 2,
 468        .n_start = 1,
 469};
 470
 471static const struct clk_factors_config sun5i_a13_ahb_config = {
 472        .pshift = 4,
 473        .pwidth = 2,
 474};
 475
 476static const struct clk_factors_config sun6i_ahb1_config = {
 477        .mshift = 6,
 478        .mwidth = 2,
 479        .pshift = 4,
 480        .pwidth = 2,
 481};
 482
 483static const struct clk_factors_config sun4i_apb1_config = {
 484        .mshift = 0,
 485        .mwidth = 5,
 486        .pshift = 16,
 487        .pwidth = 2,
 488};
 489
 490/* user manual says "n" but it's really "p" */
 491static const struct clk_factors_config sun7i_a20_out_config = {
 492        .mshift = 8,
 493        .mwidth = 5,
 494        .pshift = 20,
 495        .pwidth = 2,
 496};
 497
 498static const struct factors_data sun4i_pll1_data __initconst = {
 499        .enable = 31,
 500        .table = &sun4i_pll1_config,
 501        .getter = sun4i_get_pll1_factors,
 502};
 503
 504static const struct factors_data sun6i_a31_pll1_data __initconst = {
 505        .enable = 31,
 506        .table = &sun6i_a31_pll1_config,
 507        .getter = sun6i_a31_get_pll1_factors,
 508};
 509
 510static const struct factors_data sun8i_a23_pll1_data __initconst = {
 511        .enable = 31,
 512        .table = &sun8i_a23_pll1_config,
 513        .getter = sun8i_a23_get_pll1_factors,
 514};
 515
 516static const struct factors_data sun7i_a20_pll4_data __initconst = {
 517        .enable = 31,
 518        .table = &sun4i_pll5_config,
 519        .getter = sun4i_get_pll5_factors,
 520};
 521
 522static const struct factors_data sun4i_pll5_data __initconst = {
 523        .enable = 31,
 524        .table = &sun4i_pll5_config,
 525        .getter = sun4i_get_pll5_factors,
 526};
 527
 528static const struct factors_data sun6i_a31_pll6_data __initconst = {
 529        .enable = 31,
 530        .table = &sun6i_a31_pll6_config,
 531        .getter = sun6i_a31_get_pll6_factors,
 532};
 533
 534static const struct factors_data sun5i_a13_ahb_data __initconst = {
 535        .mux = 6,
 536        .muxmask = BIT(1) | BIT(0),
 537        .table = &sun5i_a13_ahb_config,
 538        .getter = sun5i_a13_get_ahb_factors,
 539};
 540
 541static const struct factors_data sun6i_ahb1_data __initconst = {
 542        .mux = 12,
 543        .muxmask = BIT(1) | BIT(0),
 544        .table = &sun6i_ahb1_config,
 545        .getter = sun6i_get_ahb1_factors,
 546        .recalc = sun6i_ahb1_recalc,
 547};
 548
 549static const struct factors_data sun4i_apb1_data __initconst = {
 550        .mux = 24,
 551        .muxmask = BIT(1) | BIT(0),
 552        .table = &sun4i_apb1_config,
 553        .getter = sun4i_get_apb1_factors,
 554};
 555
 556static const struct factors_data sun7i_a20_out_data __initconst = {
 557        .enable = 31,
 558        .mux = 24,
 559        .muxmask = BIT(1) | BIT(0),
 560        .table = &sun7i_a20_out_config,
 561        .getter = sun7i_a20_get_out_factors,
 562};
 563
 564static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 565                                                   const struct factors_data *data)
 566{
 567        void __iomem *reg;
 568
 569        reg = of_iomap(node, 0);
 570        if (!reg) {
 571                pr_err("Could not get registers for factors-clk: %pOFn\n",
 572                       node);
 573                return NULL;
 574        }
 575
 576        return sunxi_factors_register(node, data, &clk_lock, reg);
 577}
 578
 579static void __init sun4i_pll1_clk_setup(struct device_node *node)
 580{
 581        sunxi_factors_clk_setup(node, &sun4i_pll1_data);
 582}
 583CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
 584               sun4i_pll1_clk_setup);
 585
 586static void __init sun6i_pll1_clk_setup(struct device_node *node)
 587{
 588        sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data);
 589}
 590CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
 591               sun6i_pll1_clk_setup);
 592
 593static void __init sun8i_pll1_clk_setup(struct device_node *node)
 594{
 595        sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data);
 596}
 597CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
 598               sun8i_pll1_clk_setup);
 599
 600static void __init sun7i_pll4_clk_setup(struct device_node *node)
 601{
 602        sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data);
 603}
 604CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
 605               sun7i_pll4_clk_setup);
 606
 607static void __init sun5i_ahb_clk_setup(struct device_node *node)
 608{
 609        sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data);
 610}
 611CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
 612               sun5i_ahb_clk_setup);
 613
 614static void __init sun6i_ahb1_clk_setup(struct device_node *node)
 615{
 616        sunxi_factors_clk_setup(node, &sun6i_ahb1_data);
 617}
 618CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
 619               sun6i_ahb1_clk_setup);
 620
 621static void __init sun4i_apb1_clk_setup(struct device_node *node)
 622{
 623        sunxi_factors_clk_setup(node, &sun4i_apb1_data);
 624}
 625CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
 626               sun4i_apb1_clk_setup);
 627
 628static void __init sun7i_out_clk_setup(struct device_node *node)
 629{
 630        sunxi_factors_clk_setup(node, &sun7i_a20_out_data);
 631}
 632CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
 633               sun7i_out_clk_setup);
 634
 635
 636/**
 637 * sunxi_mux_clk_setup() - Setup function for muxes
 638 */
 639
 640#define SUNXI_MUX_GATE_WIDTH    2
 641
 642struct mux_data {
 643        u8 shift;
 644};
 645
 646static const struct mux_data sun4i_cpu_mux_data __initconst = {
 647        .shift = 16,
 648};
 649
 650static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
 651        .shift = 12,
 652};
 653
 654static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
 655        .shift = 0,
 656};
 657
 658static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
 659                                               const struct mux_data *data,
 660                                               unsigned long flags)
 661{
 662        struct clk *clk;
 663        const char *clk_name = node->name;
 664        const char *parents[SUNXI_MAX_PARENTS];
 665        void __iomem *reg;
 666        int i;
 667
 668        reg = of_iomap(node, 0);
 669        if (!reg) {
 670                pr_err("Could not map registers for mux-clk: %pOF\n", node);
 671                return NULL;
 672        }
 673
 674        i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
 675        if (of_property_read_string(node, "clock-output-names", &clk_name)) {
 676                pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
 677                       __func__, node);
 678                goto out_unmap;
 679        }
 680
 681        clk = clk_register_mux(NULL, clk_name, parents, i,
 682                               CLK_SET_RATE_PARENT | flags, reg,
 683                               data->shift, SUNXI_MUX_GATE_WIDTH,
 684                               0, &clk_lock);
 685
 686        if (IS_ERR(clk)) {
 687                pr_err("%s: failed to register mux clock %s: %ld\n", __func__,
 688                       clk_name, PTR_ERR(clk));
 689                goto out_unmap;
 690        }
 691
 692        if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
 693                pr_err("%s: failed to add clock provider for %s\n",
 694                       __func__, clk_name);
 695                clk_unregister_divider(clk);
 696                goto out_unmap;
 697        }
 698
 699        return clk;
 700out_unmap:
 701        iounmap(reg);
 702        return NULL;
 703}
 704
 705static void __init sun4i_cpu_clk_setup(struct device_node *node)
 706{
 707        /* Protect CPU clock */
 708        sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data, CLK_IS_CRITICAL);
 709}
 710CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
 711               sun4i_cpu_clk_setup);
 712
 713static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
 714{
 715        sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data, 0);
 716}
 717CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
 718               sun6i_ahb1_mux_clk_setup);
 719
 720static void __init sun8i_ahb2_clk_setup(struct device_node *node)
 721{
 722        sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data, 0);
 723}
 724CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
 725               sun8i_ahb2_clk_setup);
 726
 727
 728/**
 729 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
 730 */
 731
 732struct div_data {
 733        u8      shift;
 734        u8      pow;
 735        u8      width;
 736        const struct clk_div_table *table;
 737};
 738
 739static const struct div_data sun4i_axi_data __initconst = {
 740        .shift  = 0,
 741        .pow    = 0,
 742        .width  = 2,
 743};
 744
 745static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
 746        { .val = 0, .div = 1 },
 747        { .val = 1, .div = 2 },
 748        { .val = 2, .div = 3 },
 749        { .val = 3, .div = 4 },
 750        { .val = 4, .div = 4 },
 751        { .val = 5, .div = 4 },
 752        { .val = 6, .div = 4 },
 753        { .val = 7, .div = 4 },
 754        { } /* sentinel */
 755};
 756
 757static const struct div_data sun8i_a23_axi_data __initconst = {
 758        .width  = 3,
 759        .table  = sun8i_a23_axi_table,
 760};
 761
 762static const struct div_data sun4i_ahb_data __initconst = {
 763        .shift  = 4,
 764        .pow    = 1,
 765        .width  = 2,
 766};
 767
 768static const struct clk_div_table sun4i_apb0_table[] __initconst = {
 769        { .val = 0, .div = 2 },
 770        { .val = 1, .div = 2 },
 771        { .val = 2, .div = 4 },
 772        { .val = 3, .div = 8 },
 773        { } /* sentinel */
 774};
 775
 776static const struct div_data sun4i_apb0_data __initconst = {
 777        .shift  = 8,
 778        .pow    = 1,
 779        .width  = 2,
 780        .table  = sun4i_apb0_table,
 781};
 782
 783static void __init sunxi_divider_clk_setup(struct device_node *node,
 784                                           const struct div_data *data)
 785{
 786        struct clk *clk;
 787        const char *clk_name = node->name;
 788        const char *clk_parent;
 789        void __iomem *reg;
 790
 791        reg = of_iomap(node, 0);
 792        if (!reg) {
 793                pr_err("Could not map registers for mux-clk: %pOF\n", node);
 794                return;
 795        }
 796
 797        clk_parent = of_clk_get_parent_name(node, 0);
 798
 799        if (of_property_read_string(node, "clock-output-names", &clk_name)) {
 800                pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
 801                       __func__, node);
 802                goto out_unmap;
 803        }
 804
 805        clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
 806                                         reg, data->shift, data->width,
 807                                         data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
 808                                         data->table, &clk_lock);
 809        if (IS_ERR(clk)) {
 810                pr_err("%s: failed to register divider clock %s: %ld\n",
 811                       __func__, clk_name, PTR_ERR(clk));
 812                goto out_unmap;
 813        }
 814
 815        if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
 816                pr_err("%s: failed to add clock provider for %s\n",
 817                       __func__, clk_name);
 818                goto out_unregister;
 819        }
 820
 821        if (clk_register_clkdev(clk, clk_name, NULL)) {
 822                of_clk_del_provider(node);
 823                goto out_unregister;
 824        }
 825
 826        return;
 827out_unregister:
 828        clk_unregister_divider(clk);
 829
 830out_unmap:
 831        iounmap(reg);
 832}
 833
 834static void __init sun4i_ahb_clk_setup(struct device_node *node)
 835{
 836        sunxi_divider_clk_setup(node, &sun4i_ahb_data);
 837}
 838CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
 839               sun4i_ahb_clk_setup);
 840
 841static void __init sun4i_apb0_clk_setup(struct device_node *node)
 842{
 843        sunxi_divider_clk_setup(node, &sun4i_apb0_data);
 844}
 845CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
 846               sun4i_apb0_clk_setup);
 847
 848static void __init sun4i_axi_clk_setup(struct device_node *node)
 849{
 850        sunxi_divider_clk_setup(node, &sun4i_axi_data);
 851}
 852CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
 853               sun4i_axi_clk_setup);
 854
 855static void __init sun8i_axi_clk_setup(struct device_node *node)
 856{
 857        sunxi_divider_clk_setup(node, &sun8i_a23_axi_data);
 858}
 859CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
 860               sun8i_axi_clk_setup);
 861
 862
 863
 864/**
 865 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
 866 */
 867
 868#define SUNXI_GATES_MAX_SIZE    64
 869
 870struct gates_data {
 871        DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
 872};
 873
 874/**
 875 * sunxi_divs_clk_setup() helper data
 876 */
 877
 878#define SUNXI_DIVS_MAX_QTY      4
 879#define SUNXI_DIVISOR_WIDTH     2
 880
 881struct divs_data {
 882        const struct factors_data *factors; /* data for the factor clock */
 883        int ndivs; /* number of outputs */
 884        /*
 885         * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
 886         * self or base factor clock refers to the output from the pll
 887         * itself. The remaining refer to fixed or configurable divider
 888         * outputs.
 889         */
 890        struct {
 891                u8 self; /* is it the base factor clock? (only one) */
 892                u8 fixed; /* is it a fixed divisor? if not... */
 893                struct clk_div_table *table; /* is it a table based divisor? */
 894                u8 shift; /* otherwise it's a normal divisor with this shift */
 895                u8 pow;   /* is it power-of-two based? */
 896                u8 gate;  /* is it independently gateable? */
 897                bool critical;
 898        } div[SUNXI_DIVS_MAX_QTY];
 899};
 900
 901static struct clk_div_table pll6_sata_tbl[] = {
 902        { .val = 0, .div = 6, },
 903        { .val = 1, .div = 12, },
 904        { .val = 2, .div = 18, },
 905        { .val = 3, .div = 24, },
 906        { } /* sentinel */
 907};
 908
 909static const struct divs_data pll5_divs_data __initconst = {
 910        .factors = &sun4i_pll5_data,
 911        .ndivs = 2,
 912        .div = {
 913                /* Protect PLL5_DDR */
 914                { .shift = 0, .pow = 0, .critical = true }, /* M, DDR */
 915                { .shift = 16, .pow = 1, }, /* P, other */
 916                /* No output for the base factor clock */
 917        }
 918};
 919
 920static const struct divs_data pll6_divs_data __initconst = {
 921        .factors = &sun4i_pll5_data,
 922        .ndivs = 4,
 923        .div = {
 924                { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
 925                { .fixed = 2 }, /* P, other */
 926                { .self = 1 }, /* base factor clock, 2x */
 927                { .fixed = 4 }, /* pll6 / 4, used as ahb input */
 928        }
 929};
 930
 931static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
 932        .factors = &sun6i_a31_pll6_data,
 933        .ndivs = 2,
 934        .div = {
 935                { .fixed = 2 }, /* normal output */
 936                { .self = 1 }, /* base factor clock, 2x */
 937        }
 938};
 939
 940/**
 941 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
 942 *
 943 * These clocks look something like this
 944 *            ________________________
 945 *           |         ___divisor 1---|----> to consumer
 946 * parent >--|  pll___/___divisor 2---|----> to consumer
 947 *           |        \_______________|____> to consumer
 948 *           |________________________|
 949 */
 950
 951static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
 952                                                 const struct divs_data *data)
 953{
 954        struct clk_onecell_data *clk_data;
 955        const char *parent;
 956        const char *clk_name;
 957        struct clk **clks, *pclk;
 958        struct clk_hw *gate_hw, *rate_hw;
 959        const struct clk_ops *rate_ops;
 960        struct clk_gate *gate = NULL;
 961        struct clk_fixed_factor *fix_factor;
 962        struct clk_divider *divider;
 963        struct factors_data factors = *data->factors;
 964        char *derived_name = NULL;
 965        void __iomem *reg;
 966        int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
 967        int flags, clkflags;
 968
 969        /* if number of children known, use it */
 970        if (data->ndivs)
 971                ndivs = data->ndivs;
 972
 973        /* Try to find a name for base factor clock */
 974        for (i = 0; i < ndivs; i++) {
 975                if (data->div[i].self) {
 976                        of_property_read_string_index(node, "clock-output-names",
 977                                                      i, &factors.name);
 978                        break;
 979                }
 980        }
 981        /* If we don't have a .self clk use the first output-name up to '_' */
 982        if (factors.name == NULL) {
 983                char *endp;
 984
 985                of_property_read_string_index(node, "clock-output-names",
 986                                                      0, &clk_name);
 987                endp = strchr(clk_name, '_');
 988                if (endp) {
 989                        derived_name = kstrndup(clk_name, endp - clk_name,
 990                                                GFP_KERNEL);
 991                        factors.name = derived_name;
 992                } else {
 993                        factors.name = clk_name;
 994                }
 995        }
 996
 997        /* Set up factor clock that we will be dividing */
 998        pclk = sunxi_factors_clk_setup(node, &factors);
 999        if (!pclk)
1000                return NULL;
1001
1002        parent = __clk_get_name(pclk);
1003        kfree(derived_name);
1004
1005        reg = of_iomap(node, 0);
1006        if (!reg) {
1007                pr_err("Could not map registers for divs-clk: %pOF\n", node);
1008                return NULL;
1009        }
1010
1011        clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1012        if (!clk_data)
1013                goto out_unmap;
1014
1015        clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
1016        if (!clks)
1017                goto free_clkdata;
1018
1019        clk_data->clks = clks;
1020
1021        /* It's not a good idea to have automatic reparenting changing
1022         * our RAM clock! */
1023        clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1024
1025        for (i = 0; i < ndivs; i++) {
1026                if (of_property_read_string_index(node, "clock-output-names",
1027                                                  i, &clk_name) != 0)
1028                        break;
1029
1030                /* If this is the base factor clock, only update clks */
1031                if (data->div[i].self) {
1032                        clk_data->clks[i] = pclk;
1033                        continue;
1034                }
1035
1036                gate_hw = NULL;
1037                rate_hw = NULL;
1038                rate_ops = NULL;
1039
1040                /* If this leaf clock can be gated, create a gate */
1041                if (data->div[i].gate) {
1042                        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1043                        if (!gate)
1044                                goto free_clks;
1045
1046                        gate->reg = reg;
1047                        gate->bit_idx = data->div[i].gate;
1048                        gate->lock = &clk_lock;
1049
1050                        gate_hw = &gate->hw;
1051                }
1052
1053                /* Leaves can be fixed or configurable divisors */
1054                if (data->div[i].fixed) {
1055                        fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1056                        if (!fix_factor)
1057                                goto free_gate;
1058
1059                        fix_factor->mult = 1;
1060                        fix_factor->div = data->div[i].fixed;
1061
1062                        rate_hw = &fix_factor->hw;
1063                        rate_ops = &clk_fixed_factor_ops;
1064                } else {
1065                        divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1066                        if (!divider)
1067                                goto free_gate;
1068
1069                        flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1070
1071                        divider->reg = reg;
1072                        divider->shift = data->div[i].shift;
1073                        divider->width = SUNXI_DIVISOR_WIDTH;
1074                        divider->flags = flags;
1075                        divider->lock = &clk_lock;
1076                        divider->table = data->div[i].table;
1077
1078                        rate_hw = &divider->hw;
1079                        rate_ops = &clk_divider_ops;
1080                }
1081
1082                /* Wrap the (potential) gate and the divisor on a composite
1083                 * clock to unify them */
1084                clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1085                                                 NULL, NULL,
1086                                                 rate_hw, rate_ops,
1087                                                 gate_hw, &clk_gate_ops,
1088                                                 clkflags |
1089                                                 data->div[i].critical ?
1090                                                        CLK_IS_CRITICAL : 0);
1091
1092                WARN_ON(IS_ERR(clk_data->clks[i]));
1093        }
1094
1095        /* Adjust to the real max */
1096        clk_data->clk_num = i;
1097
1098        if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) {
1099                pr_err("%s: failed to add clock provider for %s\n",
1100                       __func__, clk_name);
1101                goto free_gate;
1102        }
1103
1104        return clks;
1105free_gate:
1106        kfree(gate);
1107free_clks:
1108        kfree(clks);
1109free_clkdata:
1110        kfree(clk_data);
1111out_unmap:
1112        iounmap(reg);
1113        return NULL;
1114}
1115
1116static void __init sun4i_pll5_clk_setup(struct device_node *node)
1117{
1118        sunxi_divs_clk_setup(node, &pll5_divs_data);
1119}
1120CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
1121               sun4i_pll5_clk_setup);
1122
1123static void __init sun4i_pll6_clk_setup(struct device_node *node)
1124{
1125        sunxi_divs_clk_setup(node, &pll6_divs_data);
1126}
1127CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1128               sun4i_pll6_clk_setup);
1129
1130static void __init sun6i_pll6_clk_setup(struct device_node *node)
1131{
1132        sunxi_divs_clk_setup(node, &sun6i_a31_pll6_divs_data);
1133}
1134CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
1135               sun6i_pll6_clk_setup);
1136
1137/*
1138 * sun6i display
1139 *
1140 * rate = parent_rate / (m + 1);
1141 */
1142static void sun6i_display_factors(struct factors_request *req)
1143{
1144        u8 m;
1145
1146        if (req->rate > req->parent_rate)
1147                req->rate = req->parent_rate;
1148
1149        m = DIV_ROUND_UP(req->parent_rate, req->rate);
1150
1151        req->rate = req->parent_rate / m;
1152        req->m = m - 1;
1153}
1154
1155static const struct clk_factors_config sun6i_display_config = {
1156        .mshift = 0,
1157        .mwidth = 4,
1158};
1159
1160static const struct factors_data sun6i_display_data __initconst = {
1161        .enable = 31,
1162        .mux = 24,
1163        .muxmask = BIT(2) | BIT(1) | BIT(0),
1164        .table = &sun6i_display_config,
1165        .getter = sun6i_display_factors,
1166};
1167
1168static void __init sun6i_display_setup(struct device_node *node)
1169{
1170        sunxi_factors_clk_setup(node, &sun6i_display_data);
1171}
1172CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk",
1173               sun6i_display_setup);
1174