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24#ifndef __AMDGPU_GFX_H__
25#define __AMDGPU_GFX_H__
26
27
28
29
30#include "clearstate_defs.h"
31#include "amdgpu_ring.h"
32
33
34#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
35#define AMDGPU_GFX_SAFE_MODE 0x00000001L
36#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
37#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
38#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
39
40
41struct amdgpu_rlc_funcs {
42 void (*enter_safe_mode)(struct amdgpu_device *adev);
43 void (*exit_safe_mode)(struct amdgpu_device *adev);
44};
45
46struct amdgpu_rlc {
47
48 struct amdgpu_bo *save_restore_obj;
49 uint64_t save_restore_gpu_addr;
50 volatile uint32_t *sr_ptr;
51 const u32 *reg_list;
52 u32 reg_list_size;
53
54 struct amdgpu_bo *clear_state_obj;
55 uint64_t clear_state_gpu_addr;
56 volatile uint32_t *cs_ptr;
57 const struct cs_section_def *cs_data;
58 u32 clear_state_size;
59
60 struct amdgpu_bo *cp_table_obj;
61 uint64_t cp_table_gpu_addr;
62 volatile uint32_t *cp_table_ptr;
63 u32 cp_table_size;
64
65
66 bool in_safe_mode;
67 const struct amdgpu_rlc_funcs *funcs;
68
69
70 u32 save_and_restore_offset;
71 u32 clear_state_descriptor_offset;
72 u32 avail_scratch_ram_locations;
73 u32 reg_restore_list_size;
74 u32 reg_list_format_start;
75 u32 reg_list_format_separate_start;
76 u32 starting_offsets_start;
77 u32 reg_list_format_size_bytes;
78 u32 reg_list_size_bytes;
79 u32 reg_list_format_direct_reg_list_length;
80 u32 save_restore_list_cntl_size_bytes;
81 u32 save_restore_list_gpm_size_bytes;
82 u32 save_restore_list_srm_size_bytes;
83
84 u32 *register_list_format;
85 u32 *register_restore;
86 u8 *save_restore_list_cntl;
87 u8 *save_restore_list_gpm;
88 u8 *save_restore_list_srm;
89
90 bool is_rlc_v2_1;
91};
92
93#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
94
95struct amdgpu_mec {
96 struct amdgpu_bo *hpd_eop_obj;
97 u64 hpd_eop_gpu_addr;
98 struct amdgpu_bo *mec_fw_obj;
99 u64 mec_fw_gpu_addr;
100 u32 num_mec;
101 u32 num_pipe_per_mec;
102 u32 num_queue_per_pipe;
103 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
104
105
106 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
107};
108
109struct amdgpu_kiq {
110 u64 eop_gpu_addr;
111 struct amdgpu_bo *eop_obj;
112 spinlock_t ring_lock;
113 struct amdgpu_ring ring;
114 struct amdgpu_irq_src irq;
115};
116
117
118
119
120struct amdgpu_scratch {
121 unsigned num_reg;
122 uint32_t reg_base;
123 uint32_t free_mask;
124};
125
126
127
128
129#define AMDGPU_GFX_MAX_SE 4
130#define AMDGPU_GFX_MAX_SH_PER_SE 2
131
132struct amdgpu_rb_config {
133 uint32_t rb_backend_disable;
134 uint32_t user_rb_backend_disable;
135 uint32_t raster_config;
136 uint32_t raster_config_1;
137};
138
139struct gb_addr_config {
140 uint16_t pipe_interleave_size;
141 uint8_t num_pipes;
142 uint8_t max_compress_frags;
143 uint8_t num_banks;
144 uint8_t num_se;
145 uint8_t num_rb_per_se;
146};
147
148struct amdgpu_gfx_config {
149 unsigned max_shader_engines;
150 unsigned max_tile_pipes;
151 unsigned max_cu_per_sh;
152 unsigned max_sh_per_se;
153 unsigned max_backends_per_se;
154 unsigned max_texture_channel_caches;
155 unsigned max_gprs;
156 unsigned max_gs_threads;
157 unsigned max_hw_contexts;
158 unsigned sc_prim_fifo_size_frontend;
159 unsigned sc_prim_fifo_size_backend;
160 unsigned sc_hiz_tile_fifo_size;
161 unsigned sc_earlyz_tile_fifo_size;
162
163 unsigned num_tile_pipes;
164 unsigned backend_enable_mask;
165 unsigned mem_max_burst_length_bytes;
166 unsigned mem_row_size_in_kb;
167 unsigned shader_engine_tile_size;
168 unsigned num_gpus;
169 unsigned multi_gpu_tile_size;
170 unsigned mc_arb_ramcfg;
171 unsigned gb_addr_config;
172 unsigned num_rbs;
173 unsigned gs_vgt_table_depth;
174 unsigned gs_prim_buffer_depth;
175
176 uint32_t tile_mode_array[32];
177 uint32_t macrotile_mode_array[16];
178
179 struct gb_addr_config gb_addr_config_fields;
180 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
181
182
183 uint32_t double_offchip_lds_buf;
184
185 uint32_t db_debug2;
186};
187
188struct amdgpu_cu_info {
189 uint32_t simd_per_cu;
190 uint32_t max_waves_per_simd;
191 uint32_t wave_front_size;
192 uint32_t max_scratch_slots_per_cu;
193 uint32_t lds_size;
194
195
196 uint32_t number;
197 uint32_t ao_cu_mask;
198 uint32_t ao_cu_bitmap[4][4];
199 uint32_t bitmap[4][4];
200};
201
202struct amdgpu_gfx_funcs {
203
204 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
205 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
206 u32 sh_num, u32 instance);
207 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
208 uint32_t wave, uint32_t *dst, int *no_fields);
209 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
210 uint32_t wave, uint32_t thread, uint32_t start,
211 uint32_t size, uint32_t *dst);
212 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
213 uint32_t wave, uint32_t start, uint32_t size,
214 uint32_t *dst);
215 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
216 u32 queue);
217};
218
219struct amdgpu_ngg_buf {
220 struct amdgpu_bo *bo;
221 uint64_t gpu_addr;
222 uint32_t size;
223 uint32_t bo_size;
224};
225
226enum {
227 NGG_PRIM = 0,
228 NGG_POS,
229 NGG_CNTL,
230 NGG_PARAM,
231 NGG_BUF_MAX
232};
233
234struct amdgpu_ngg {
235 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
236 uint32_t gds_reserve_addr;
237 uint32_t gds_reserve_size;
238 bool init;
239};
240
241struct sq_work {
242 struct work_struct work;
243 unsigned ih_data;
244};
245
246struct amdgpu_gfx {
247 struct mutex gpu_clock_mutex;
248 struct amdgpu_gfx_config config;
249 struct amdgpu_rlc rlc;
250 struct amdgpu_mec mec;
251 struct amdgpu_kiq kiq;
252 struct amdgpu_scratch scratch;
253 const struct firmware *me_fw;
254 uint32_t me_fw_version;
255 const struct firmware *pfp_fw;
256 uint32_t pfp_fw_version;
257 const struct firmware *ce_fw;
258 uint32_t ce_fw_version;
259 const struct firmware *rlc_fw;
260 uint32_t rlc_fw_version;
261 const struct firmware *mec_fw;
262 uint32_t mec_fw_version;
263 const struct firmware *mec2_fw;
264 uint32_t mec2_fw_version;
265 uint32_t me_feature_version;
266 uint32_t ce_feature_version;
267 uint32_t pfp_feature_version;
268 uint32_t rlc_feature_version;
269 uint32_t rlc_srlc_fw_version;
270 uint32_t rlc_srlc_feature_version;
271 uint32_t rlc_srlg_fw_version;
272 uint32_t rlc_srlg_feature_version;
273 uint32_t rlc_srls_fw_version;
274 uint32_t rlc_srls_feature_version;
275 uint32_t mec_feature_version;
276 uint32_t mec2_feature_version;
277 bool mec_fw_write_wait;
278 bool me_fw_write_wait;
279 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
280 unsigned num_gfx_rings;
281 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
282 unsigned num_compute_rings;
283 struct amdgpu_irq_src eop_irq;
284 struct amdgpu_irq_src priv_reg_irq;
285 struct amdgpu_irq_src priv_inst_irq;
286 struct amdgpu_irq_src cp_ecc_error_irq;
287 struct amdgpu_irq_src sq_irq;
288 struct sq_work sq_work;
289
290
291 uint32_t gfx_current_status;
292
293 unsigned ce_ram_size;
294 struct amdgpu_cu_info cu_info;
295 const struct amdgpu_gfx_funcs *funcs;
296
297
298 uint32_t grbm_soft_reset;
299 uint32_t srbm_soft_reset;
300
301
302 struct amdgpu_ngg ngg;
303
304
305 bool gfx_off_state;
306 struct mutex gfx_off_mutex;
307 uint32_t gfx_off_req_count;
308 struct delayed_work gfx_off_delay_work;
309
310
311 struct mutex pipe_reserve_mutex;
312 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
313};
314
315#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
316#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
317#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
318
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324
325
326
327static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
328{
329 return (u32)((1ULL << bit_width) - 1);
330}
331
332int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
333void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
334
335void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
336 unsigned max_sh);
337
338int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
339 struct amdgpu_ring *ring,
340 struct amdgpu_irq_src *irq);
341
342void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
343 struct amdgpu_irq_src *irq);
344
345void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
346int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
347 unsigned hpd_size);
348
349int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
350 unsigned mqd_size);
351void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
352
353void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
354int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, int mec,
355 int pipe, int queue);
356void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
357 int *mec, int *pipe, int *queue);
358bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
359 int pipe, int queue);
360void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
361
362#endif
363
