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11#ifndef __CIRRUS_DRV_H__
12#define __CIRRUS_DRV_H__
13
14#include <video/vga.h>
15
16#include <drm/drm_encoder.h>
17#include <drm/drm_fb_helper.h>
18
19#include <drm/ttm/ttm_bo_api.h>
20#include <drm/ttm/ttm_bo_driver.h>
21#include <drm/ttm/ttm_placement.h>
22#include <drm/ttm/ttm_memory.h>
23#include <drm/ttm/ttm_module.h>
24
25#include <drm/drm_gem.h>
26
27#define DRIVER_AUTHOR "Matthew Garrett"
28
29#define DRIVER_NAME "cirrus"
30#define DRIVER_DESC "qemu Cirrus emulation"
31#define DRIVER_DATE "20110418"
32
33#define DRIVER_MAJOR 1
34#define DRIVER_MINOR 0
35#define DRIVER_PATCHLEVEL 0
36
37#define CIRRUSFB_CONN_LIMIT 1
38
39#define RREG8(reg) ioread8(((void __iomem *)cdev->rmmio) + (reg))
40#define WREG8(reg, v) iowrite8(v, ((void __iomem *)cdev->rmmio) + (reg))
41#define RREG32(reg) ioread32(((void __iomem *)cdev->rmmio) + (reg))
42#define WREG32(reg, v) iowrite32(v, ((void __iomem *)cdev->rmmio) + (reg))
43
44#define SEQ_INDEX 4
45#define SEQ_DATA 5
46
47#define WREG_SEQ(reg, v) \
48 do { \
49 WREG8(SEQ_INDEX, reg); \
50 WREG8(SEQ_DATA, v); \
51 } while (0) \
52
53#define CRT_INDEX 0x14
54#define CRT_DATA 0x15
55
56#define WREG_CRT(reg, v) \
57 do { \
58 WREG8(CRT_INDEX, reg); \
59 WREG8(CRT_DATA, v); \
60 } while (0) \
61
62#define GFX_INDEX 0xe
63#define GFX_DATA 0xf
64
65#define WREG_GFX(reg, v) \
66 do { \
67 WREG8(GFX_INDEX, reg); \
68 WREG8(GFX_DATA, v); \
69 } while (0) \
70
71
72
73
74
75
76#define VGA_DAC_MASK 0x6
77
78#define WREG_HDR(v) \
79 do { \
80 RREG8(VGA_DAC_MASK); \
81 RREG8(VGA_DAC_MASK); \
82 RREG8(VGA_DAC_MASK); \
83 RREG8(VGA_DAC_MASK); \
84 WREG8(VGA_DAC_MASK, v); \
85 } while (0) \
86
87
88#define CIRRUS_MAX_FB_HEIGHT 4096
89#define CIRRUS_MAX_FB_WIDTH 4096
90
91#define CIRRUS_DPMS_CLEARED (-1)
92
93#define to_cirrus_crtc(x) container_of(x, struct cirrus_crtc, base)
94#define to_cirrus_encoder(x) container_of(x, struct cirrus_encoder, base)
95
96struct cirrus_crtc {
97 struct drm_crtc base;
98 int last_dpms;
99 bool enabled;
100};
101
102struct cirrus_fbdev;
103struct cirrus_mode_info {
104 bool mode_config_initialized;
105 struct cirrus_crtc *crtc;
106
107 struct cirrus_fbdev *gfbdev;
108};
109
110struct cirrus_encoder {
111 struct drm_encoder base;
112 int last_dpms;
113};
114
115struct cirrus_connector {
116 struct drm_connector base;
117};
118
119struct cirrus_mc {
120 resource_size_t vram_size;
121 resource_size_t vram_base;
122};
123
124struct cirrus_device {
125 struct drm_device *dev;
126 unsigned long flags;
127
128 resource_size_t rmmio_base;
129 resource_size_t rmmio_size;
130 void __iomem *rmmio;
131
132 struct cirrus_mc mc;
133 struct cirrus_mode_info mode_info;
134
135 int num_crtc;
136 int fb_mtrr;
137
138 struct {
139 struct drm_global_reference mem_global_ref;
140 struct ttm_bo_global_ref bo_global_ref;
141 struct ttm_bo_device bdev;
142 } ttm;
143 bool mm_inited;
144};
145
146
147struct cirrus_fbdev {
148 struct drm_fb_helper helper;
149 struct drm_framebuffer *gfb;
150 void *sysram;
151 int size;
152 int x1, y1, x2, y2;
153 spinlock_t dirty_lock;
154};
155
156struct cirrus_bo {
157 struct ttm_buffer_object bo;
158 struct ttm_placement placement;
159 struct ttm_bo_kmap_obj kmap;
160 struct drm_gem_object gem;
161 struct ttm_place placements[3];
162 int pin_count;
163};
164#define gem_to_cirrus_bo(gobj) container_of((gobj), struct cirrus_bo, gem)
165
166static inline struct cirrus_bo *
167cirrus_bo(struct ttm_buffer_object *bo)
168{
169 return container_of(bo, struct cirrus_bo, bo);
170}
171
172
173#define to_cirrus_obj(x) container_of(x, struct cirrus_gem_object, base)
174#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
175
176
177int cirrus_device_init(struct cirrus_device *cdev,
178 struct drm_device *ddev,
179 struct pci_dev *pdev,
180 uint32_t flags);
181void cirrus_device_fini(struct cirrus_device *cdev);
182void cirrus_gem_free_object(struct drm_gem_object *obj);
183int cirrus_dumb_mmap_offset(struct drm_file *file,
184 struct drm_device *dev,
185 uint32_t handle,
186 uint64_t *offset);
187int cirrus_gem_create(struct drm_device *dev,
188 u32 size, bool iskernel,
189 struct drm_gem_object **obj);
190int cirrus_dumb_create(struct drm_file *file,
191 struct drm_device *dev,
192 struct drm_mode_create_dumb *args);
193
194int cirrus_framebuffer_init(struct drm_device *dev,
195 struct drm_framebuffer *gfb,
196 const struct drm_mode_fb_cmd2 *mode_cmd,
197 struct drm_gem_object *obj);
198
199bool cirrus_check_framebuffer(struct cirrus_device *cdev, int width, int height,
200 int bpp, int pitch);
201
202
203int cirrus_modeset_init(struct cirrus_device *cdev);
204void cirrus_modeset_fini(struct cirrus_device *cdev);
205
206
207int cirrus_fbdev_init(struct cirrus_device *cdev);
208void cirrus_fbdev_fini(struct cirrus_device *cdev);
209
210
211
212
213void cirrus_driver_irq_preinstall(struct drm_device *dev);
214int cirrus_driver_irq_postinstall(struct drm_device *dev);
215void cirrus_driver_irq_uninstall(struct drm_device *dev);
216irqreturn_t cirrus_driver_irq_handler(int irq, void *arg);
217
218
219int cirrus_driver_load(struct drm_device *dev, unsigned long flags);
220void cirrus_driver_unload(struct drm_device *dev);
221extern struct drm_ioctl_desc cirrus_ioctls[];
222extern int cirrus_max_ioctl;
223
224int cirrus_mm_init(struct cirrus_device *cirrus);
225void cirrus_mm_fini(struct cirrus_device *cirrus);
226void cirrus_ttm_placement(struct cirrus_bo *bo, int domain);
227int cirrus_bo_create(struct drm_device *dev, int size, int align,
228 uint32_t flags, struct cirrus_bo **pcirrusbo);
229int cirrus_mmap(struct file *filp, struct vm_area_struct *vma);
230
231static inline int cirrus_bo_reserve(struct cirrus_bo *bo, bool no_wait)
232{
233 int ret;
234
235 ret = ttm_bo_reserve(&bo->bo, true, no_wait, NULL);
236 if (ret) {
237 if (ret != -ERESTARTSYS && ret != -EBUSY)
238 DRM_ERROR("reserve failed %p\n", bo);
239 return ret;
240 }
241 return 0;
242}
243
244static inline void cirrus_bo_unreserve(struct cirrus_bo *bo)
245{
246 ttm_bo_unreserve(&bo->bo);
247}
248
249int cirrus_bo_push_sysram(struct cirrus_bo *bo);
250int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr);
251
252extern int cirrus_bpp;
253
254#endif
255
