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25#ifndef _I915_REG_H_
26#define _I915_REG_H_
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119typedef struct {
120 uint32_t reg;
121} i915_reg_t;
122
123#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
124
125#define INVALID_MMIO_REG _MMIO(0)
126
127static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
128{
129 return reg.reg;
130}
131
132static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
133{
134 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
135}
136
137static inline bool i915_mmio_reg_valid(i915_reg_t reg)
138{
139 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
140}
141
142
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145
146
147
148#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
149
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153
154
155#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
156
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159
160#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
161#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
162#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
163#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
164#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
165#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
166#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
167#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
168#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
169#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
170#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
171#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
172#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
173#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
174
175#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
176#define _MASKED_FIELD(mask, value) ({ \
177 if (__builtin_constant_p(mask)) \
178 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
179 if (__builtin_constant_p(value)) \
180 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
181 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
182 BUILD_BUG_ON_MSG((value) & ~(mask), \
183 "Incorrect value for mask"); \
184 __MASKED_FIELD(mask, value); })
185#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
186#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
187
188
189
190#define RCS_HW 0
191#define VCS_HW 1
192#define BCS_HW 2
193#define VECS_HW 3
194#define VCS2_HW 4
195#define VCS3_HW 6
196#define VCS4_HW 7
197#define VECS2_HW 12
198
199
200
201#define RENDER_CLASS 0
202#define VIDEO_DECODE_CLASS 1
203#define VIDEO_ENHANCEMENT_CLASS 2
204#define COPY_ENGINE_CLASS 3
205#define OTHER_CLASS 4
206#define MAX_ENGINE_CLASS 4
207
208#define OTHER_GTPM_INSTANCE 1
209#define MAX_ENGINE_INSTANCE 3
210
211
212
213#define MCHBAR_I915 0x44
214#define MCHBAR_I965 0x48
215#define MCHBAR_SIZE (4 * 4096)
216
217#define DEVEN 0x54
218#define DEVEN_MCHBAR_EN (1 << 28)
219
220
221
222#define HPLLCC 0xc0
223#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
224#define GC_CLOCK_133_200 (0 << 0)
225#define GC_CLOCK_100_200 (1 << 0)
226#define GC_CLOCK_100_133 (2 << 0)
227#define GC_CLOCK_133_266 (3 << 0)
228#define GC_CLOCK_133_200_2 (4 << 0)
229#define GC_CLOCK_133_266_2 (5 << 0)
230#define GC_CLOCK_166_266 (6 << 0)
231#define GC_CLOCK_166_250 (7 << 0)
232
233#define I915_GDRST 0xc0
234#define GRDOM_FULL (0 << 2)
235#define GRDOM_RENDER (1 << 2)
236#define GRDOM_MEDIA (3 << 2)
237#define GRDOM_MASK (3 << 2)
238#define GRDOM_RESET_STATUS (1 << 1)
239#define GRDOM_RESET_ENABLE (1 << 0)
240
241
242#define I830_CLOCK_GATE 0xc8
243#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
244
245#define GCDGMBUS 0xcc
246
247#define GCFGC2 0xda
248#define GCFGC 0xf0
249#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
250#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
251#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
252#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
253#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
254#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
255#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
256#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
257#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
258#define GC_DISPLAY_CLOCK_MASK (7 << 4)
259#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
260#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
261#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
262#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
263#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
264#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
265#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
266#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
267#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
268#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
269#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
270#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
271#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
272#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
273#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
274#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
275#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
276#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
277#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
278
279#define ASLE 0xe4
280#define ASLS 0xfc
281
282#define SWSCI 0xe8
283#define SWSCI_SCISEL (1 << 15)
284#define SWSCI_GSSCIE (1 << 0)
285
286#define LBPC 0xf4
287
288
289#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
290#define ILK_GRDOM_FULL (0 << 1)
291#define ILK_GRDOM_RENDER (1 << 1)
292#define ILK_GRDOM_MEDIA (3 << 1)
293#define ILK_GRDOM_MASK (3 << 1)
294#define ILK_GRDOM_RESET_ENABLE (1 << 0)
295
296#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c)
297#define GEN6_MBC_SNPCR_SHIFT 21
298#define GEN6_MBC_SNPCR_MASK (3 << 21)
299#define GEN6_MBC_SNPCR_MAX (0 << 21)
300#define GEN6_MBC_SNPCR_MED (1 << 21)
301#define GEN6_MBC_SNPCR_LOW (2 << 21)
302#define GEN6_MBC_SNPCR_MIN (3 << 21)
303
304#define VLV_G3DCTL _MMIO(0x9024)
305#define VLV_GSCKGCTL _MMIO(0x9028)
306
307#define GEN6_MBCTL _MMIO(0x0907c)
308#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
309#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
310#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
311#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
312#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
313
314#define GEN6_GDRST _MMIO(0x941c)
315#define GEN6_GRDOM_FULL (1 << 0)
316#define GEN6_GRDOM_RENDER (1 << 1)
317#define GEN6_GRDOM_MEDIA (1 << 2)
318#define GEN6_GRDOM_BLT (1 << 3)
319#define GEN6_GRDOM_VECS (1 << 4)
320#define GEN9_GRDOM_GUC (1 << 5)
321#define GEN8_GRDOM_MEDIA2 (1 << 7)
322
323#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
324#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
325#define GEN11_GRDOM_BLT (1 << 2)
326#define GEN11_GRDOM_GUC (1 << 3)
327#define GEN11_GRDOM_MEDIA (1 << 5)
328#define GEN11_GRDOM_MEDIA2 (1 << 6)
329#define GEN11_GRDOM_MEDIA3 (1 << 7)
330#define GEN11_GRDOM_MEDIA4 (1 << 8)
331#define GEN11_GRDOM_VECS (1 << 13)
332#define GEN11_GRDOM_VECS2 (1 << 14)
333
334#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228)
335#define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518)
336#define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base + 0x220)
337#define PP_DIR_DCLV_2G 0xffffffff
338
339#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
340#define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8)
341
342#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
343#define GEN8_RPCS_ENABLE (1 << 31)
344#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
345#define GEN8_RPCS_S_CNT_SHIFT 15
346#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
347#define GEN11_RPCS_S_CNT_SHIFT 12
348#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
349#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
350#define GEN8_RPCS_SS_CNT_SHIFT 8
351#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
352#define GEN8_RPCS_EU_MAX_SHIFT 4
353#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
354#define GEN8_RPCS_EU_MIN_SHIFT 0
355#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
356
357#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
358
359#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
360#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
361#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
362#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
363
364#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
365#define HSW_RCS_CONTEXT_ENABLE (1 << 7)
366#define HSW_RCS_INHIBIT (1 << 8)
367
368#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
369#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
370#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
371#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
372#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
373#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
374#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
375#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
376#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
377#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
378
379#define GAM_ECOCHK _MMIO(0x4090)
380#define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
381#define ECOCHK_SNB_BIT (1 << 10)
382#define ECOCHK_DIS_TLB (1 << 8)
383#define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
384#define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
385#define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
386#define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
387#define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
388#define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
389#define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
390#define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
391
392#define GAC_ECO_BITS _MMIO(0x14090)
393#define ECOBITS_SNB_BIT (1 << 13)
394#define ECOBITS_PPGTT_CACHE64B (3 << 8)
395#define ECOBITS_PPGTT_CACHE4B (0 << 8)
396
397#define GAB_CTL _MMIO(0x24000)
398#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
399
400#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
401#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
402#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
403#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
404#define GEN6_STOLEN_RESERVED_1M (0 << 4)
405#define GEN6_STOLEN_RESERVED_512K (1 << 4)
406#define GEN6_STOLEN_RESERVED_256K (2 << 4)
407#define GEN6_STOLEN_RESERVED_128K (3 << 4)
408#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
409#define GEN7_STOLEN_RESERVED_1M (0 << 5)
410#define GEN7_STOLEN_RESERVED_256K (1 << 5)
411#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
412#define GEN8_STOLEN_RESERVED_1M (0 << 7)
413#define GEN8_STOLEN_RESERVED_2M (1 << 7)
414#define GEN8_STOLEN_RESERVED_4M (2 << 7)
415#define GEN8_STOLEN_RESERVED_8M (3 << 7)
416#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
417#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
418
419
420
421#define VGA_ST01_MDA 0x3ba
422#define VGA_ST01_CGA 0x3da
423
424#define _VGA_MSR_WRITE _MMIO(0x3c2)
425#define VGA_MSR_WRITE 0x3c2
426#define VGA_MSR_READ 0x3cc
427#define VGA_MSR_MEM_EN (1 << 1)
428#define VGA_MSR_CGA_MODE (1 << 0)
429
430#define VGA_SR_INDEX 0x3c4
431#define SR01 1
432#define VGA_SR_DATA 0x3c5
433
434#define VGA_AR_INDEX 0x3c0
435#define VGA_AR_VID_EN (1 << 5)
436#define VGA_AR_DATA_WRITE 0x3c0
437#define VGA_AR_DATA_READ 0x3c1
438
439#define VGA_GR_INDEX 0x3ce
440#define VGA_GR_DATA 0x3cf
441
442#define VGA_GR_MEM_READ_MODE_SHIFT 3
443#define VGA_GR_MEM_READ_MODE_PLANE 1
444
445#define VGA_GR_MEM_MODE_MASK 0xc
446#define VGA_GR_MEM_MODE_SHIFT 2
447#define VGA_GR_MEM_A0000_AFFFF 0
448#define VGA_GR_MEM_A0000_BFFFF 1
449#define VGA_GR_MEM_B0000_B7FFF 2
450#define VGA_GR_MEM_B0000_BFFFF 3
451
452#define VGA_DACMASK 0x3c6
453#define VGA_DACRX 0x3c7
454#define VGA_DACWX 0x3c8
455#define VGA_DACDATA 0x3c9
456
457#define VGA_CR_INDEX_MDA 0x3b4
458#define VGA_CR_DATA_MDA 0x3b5
459#define VGA_CR_INDEX_CGA 0x3d4
460#define VGA_CR_DATA_CGA 0x3d5
461
462#define MI_PREDICATE_SRC0 _MMIO(0x2400)
463#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
464#define MI_PREDICATE_SRC1 _MMIO(0x2408)
465#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
466
467#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
468#define LOWER_SLICE_ENABLED (1 << 0)
469#define LOWER_SLICE_DISABLED (0 << 0)
470
471
472
473
474#define BCS_SWCTRL _MMIO(0x22200)
475
476#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
477#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
478#define HS_INVOCATION_COUNT _MMIO(0x2300)
479#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
480#define DS_INVOCATION_COUNT _MMIO(0x2308)
481#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
482#define IA_VERTICES_COUNT _MMIO(0x2310)
483#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
484#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
485#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
486#define VS_INVOCATION_COUNT _MMIO(0x2320)
487#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
488#define GS_INVOCATION_COUNT _MMIO(0x2328)
489#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
490#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
491#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
492#define CL_INVOCATION_COUNT _MMIO(0x2338)
493#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
494#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
495#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
496#define PS_INVOCATION_COUNT _MMIO(0x2348)
497#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
498#define PS_DEPTH_COUNT _MMIO(0x2350)
499#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
500
501
502#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
503#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
504
505#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
506#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
507
508#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
509#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
510#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
511#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
512#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
513#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
514
515#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
516#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
517#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
518
519
520#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
521#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
522
523#define GEN7_OACONTROL _MMIO(0x2360)
524#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
525#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
526#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
527#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
528#define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
529#define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
530#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
531#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
532#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
533#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
534#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
535#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
536#define GEN7_OACONTROL_FORMAT_SHIFT 2
537#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
538#define GEN7_OACONTROL_ENABLE (1 << 0)
539
540#define GEN8_OACTXID _MMIO(0x2364)
541
542#define GEN8_OA_DEBUG _MMIO(0x2B04)
543#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
544#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
545#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
546#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
547
548#define GEN8_OACONTROL _MMIO(0x2B00)
549#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
550#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
551#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
552#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
553#define GEN8_OA_REPORT_FORMAT_SHIFT 2
554#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
555#define GEN8_OA_COUNTER_ENABLE (1 << 0)
556
557#define GEN8_OACTXCONTROL _MMIO(0x2360)
558#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
559#define GEN8_OA_TIMER_PERIOD_SHIFT 2
560#define GEN8_OA_TIMER_ENABLE (1 << 1)
561#define GEN8_OA_COUNTER_RESUME (1 << 0)
562
563#define GEN7_OABUFFER _MMIO(0x23B0)
564#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
565#define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
566#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
567#define GEN7_OABUFFER_RESUME (1 << 0)
568
569#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
570#define GEN8_OABUFFER _MMIO(0x2b14)
571#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0)
572
573#define GEN7_OASTATUS1 _MMIO(0x2364)
574#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
575#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
576#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
577#define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
578
579#define GEN7_OASTATUS2 _MMIO(0x2368)
580#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
581#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0)
582
583#define GEN8_OASTATUS _MMIO(0x2b08)
584#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
585#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
586#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
587#define GEN8_OASTATUS_REPORT_LOST (1 << 0)
588
589#define GEN8_OAHEADPTR _MMIO(0x2B0C)
590#define GEN8_OAHEADPTR_MASK 0xffffffc0
591#define GEN8_OATAILPTR _MMIO(0x2B10)
592#define GEN8_OATAILPTR_MASK 0xffffffc0
593
594#define OABUFFER_SIZE_128K (0 << 3)
595#define OABUFFER_SIZE_256K (1 << 3)
596#define OABUFFER_SIZE_512K (2 << 3)
597#define OABUFFER_SIZE_1M (3 << 3)
598#define OABUFFER_SIZE_2M (4 << 3)
599#define OABUFFER_SIZE_4M (5 << 3)
600#define OABUFFER_SIZE_8M (6 << 3)
601#define OABUFFER_SIZE_16M (7 << 3)
602
603
604
605
606
607#define EU_PERF_CNTL0 _MMIO(0xe458)
608#define EU_PERF_CNTL1 _MMIO(0xe558)
609#define EU_PERF_CNTL2 _MMIO(0xe658)
610#define EU_PERF_CNTL3 _MMIO(0xe758)
611#define EU_PERF_CNTL4 _MMIO(0xe45c)
612#define EU_PERF_CNTL5 _MMIO(0xe55c)
613#define EU_PERF_CNTL6 _MMIO(0xe65c)
614
615
616
617
618
619#define OASTARTTRIG1 _MMIO(0x2710)
620#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
621#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
622
623#define OASTARTTRIG2 _MMIO(0x2714)
624#define OASTARTTRIG2_INVERT_A_0 (1 << 0)
625#define OASTARTTRIG2_INVERT_A_1 (1 << 1)
626#define OASTARTTRIG2_INVERT_A_2 (1 << 2)
627#define OASTARTTRIG2_INVERT_A_3 (1 << 3)
628#define OASTARTTRIG2_INVERT_A_4 (1 << 4)
629#define OASTARTTRIG2_INVERT_A_5 (1 << 5)
630#define OASTARTTRIG2_INVERT_A_6 (1 << 6)
631#define OASTARTTRIG2_INVERT_A_7 (1 << 7)
632#define OASTARTTRIG2_INVERT_A_8 (1 << 8)
633#define OASTARTTRIG2_INVERT_A_9 (1 << 9)
634#define OASTARTTRIG2_INVERT_A_10 (1 << 10)
635#define OASTARTTRIG2_INVERT_A_11 (1 << 11)
636#define OASTARTTRIG2_INVERT_A_12 (1 << 12)
637#define OASTARTTRIG2_INVERT_A_13 (1 << 13)
638#define OASTARTTRIG2_INVERT_A_14 (1 << 14)
639#define OASTARTTRIG2_INVERT_A_15 (1 << 15)
640#define OASTARTTRIG2_INVERT_B_0 (1 << 16)
641#define OASTARTTRIG2_INVERT_B_1 (1 << 17)
642#define OASTARTTRIG2_INVERT_B_2 (1 << 18)
643#define OASTARTTRIG2_INVERT_B_3 (1 << 19)
644#define OASTARTTRIG2_INVERT_C_0 (1 << 20)
645#define OASTARTTRIG2_INVERT_C_1 (1 << 21)
646#define OASTARTTRIG2_INVERT_D_0 (1 << 22)
647#define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
648#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
649#define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
650#define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
651#define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
652#define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
653
654#define OASTARTTRIG3 _MMIO(0x2718)
655#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
656#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
657#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
658#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
659#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
660#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
661#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
662#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
663#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
664
665#define OASTARTTRIG4 _MMIO(0x271c)
666#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
667#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
668#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
669#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
670#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
671#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
672#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
673#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
674#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
675
676#define OASTARTTRIG5 _MMIO(0x2720)
677#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
678#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
679
680#define OASTARTTRIG6 _MMIO(0x2724)
681#define OASTARTTRIG6_INVERT_A_0 (1 << 0)
682#define OASTARTTRIG6_INVERT_A_1 (1 << 1)
683#define OASTARTTRIG6_INVERT_A_2 (1 << 2)
684#define OASTARTTRIG6_INVERT_A_3 (1 << 3)
685#define OASTARTTRIG6_INVERT_A_4 (1 << 4)
686#define OASTARTTRIG6_INVERT_A_5 (1 << 5)
687#define OASTARTTRIG6_INVERT_A_6 (1 << 6)
688#define OASTARTTRIG6_INVERT_A_7 (1 << 7)
689#define OASTARTTRIG6_INVERT_A_8 (1 << 8)
690#define OASTARTTRIG6_INVERT_A_9 (1 << 9)
691#define OASTARTTRIG6_INVERT_A_10 (1 << 10)
692#define OASTARTTRIG6_INVERT_A_11 (1 << 11)
693#define OASTARTTRIG6_INVERT_A_12 (1 << 12)
694#define OASTARTTRIG6_INVERT_A_13 (1 << 13)
695#define OASTARTTRIG6_INVERT_A_14 (1 << 14)
696#define OASTARTTRIG6_INVERT_A_15 (1 << 15)
697#define OASTARTTRIG6_INVERT_B_0 (1 << 16)
698#define OASTARTTRIG6_INVERT_B_1 (1 << 17)
699#define OASTARTTRIG6_INVERT_B_2 (1 << 18)
700#define OASTARTTRIG6_INVERT_B_3 (1 << 19)
701#define OASTARTTRIG6_INVERT_C_0 (1 << 20)
702#define OASTARTTRIG6_INVERT_C_1 (1 << 21)
703#define OASTARTTRIG6_INVERT_D_0 (1 << 22)
704#define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
705#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
706#define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
707#define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
708#define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
709#define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
710
711#define OASTARTTRIG7 _MMIO(0x2728)
712#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
713#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
714#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
715#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
716#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
717#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
718#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
719#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
720#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
721
722#define OASTARTTRIG8 _MMIO(0x272c)
723#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
724#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
725#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
726#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
727#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
728#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
729#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
730#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
731#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
732
733#define OAREPORTTRIG1 _MMIO(0x2740)
734#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
735#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000
736
737#define OAREPORTTRIG2 _MMIO(0x2744)
738#define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
739#define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
740#define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
741#define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
742#define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
743#define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
744#define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
745#define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
746#define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
747#define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
748#define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
749#define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
750#define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
751#define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
752#define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
753#define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
754#define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
755#define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
756#define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
757#define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
758#define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
759#define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
760#define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
761#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
762#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
763
764#define OAREPORTTRIG3 _MMIO(0x2748)
765#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
766#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
767#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
768#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
769#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
770#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
771#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
772#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
773#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
774
775#define OAREPORTTRIG4 _MMIO(0x274c)
776#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
777#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
778#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
779#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
780#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
781#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
782#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
783#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
784#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
785
786#define OAREPORTTRIG5 _MMIO(0x2750)
787#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
788#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000
789
790#define OAREPORTTRIG6 _MMIO(0x2754)
791#define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
792#define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
793#define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
794#define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
795#define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
796#define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
797#define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
798#define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
799#define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
800#define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
801#define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
802#define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
803#define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
804#define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
805#define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
806#define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
807#define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
808#define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
809#define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
810#define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
811#define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
812#define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
813#define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
814#define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
815#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
816
817#define OAREPORTTRIG7 _MMIO(0x2758)
818#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
819#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
820#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
821#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
822#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
823#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
824#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
825#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
826#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
827
828#define OAREPORTTRIG8 _MMIO(0x275c)
829#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
830#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
831#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
832#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
833#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
834#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
835#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
836#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
837#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
838
839
840#define OACEC_COMPARE_LESS_OR_EQUAL 6
841#define OACEC_COMPARE_NOT_EQUAL 5
842#define OACEC_COMPARE_LESS_THAN 4
843#define OACEC_COMPARE_GREATER_OR_EQUAL 3
844#define OACEC_COMPARE_EQUAL 2
845#define OACEC_COMPARE_GREATER_THAN 1
846#define OACEC_COMPARE_ANY_EQUAL 0
847
848#define OACEC_COMPARE_VALUE_MASK 0xffff
849#define OACEC_COMPARE_VALUE_SHIFT 3
850
851#define OACEC_SELECT_NOA (0 << 19)
852#define OACEC_SELECT_PREV (1 << 19)
853#define OACEC_SELECT_BOOLEAN (2 << 19)
854
855
856#define OACEC_MASK_MASK 0xffff
857#define OACEC_CONSIDERATIONS_MASK 0xffff
858#define OACEC_CONSIDERATIONS_SHIFT 16
859
860#define OACEC0_0 _MMIO(0x2770)
861#define OACEC0_1 _MMIO(0x2774)
862#define OACEC1_0 _MMIO(0x2778)
863#define OACEC1_1 _MMIO(0x277c)
864#define OACEC2_0 _MMIO(0x2780)
865#define OACEC2_1 _MMIO(0x2784)
866#define OACEC3_0 _MMIO(0x2788)
867#define OACEC3_1 _MMIO(0x278c)
868#define OACEC4_0 _MMIO(0x2790)
869#define OACEC4_1 _MMIO(0x2794)
870#define OACEC5_0 _MMIO(0x2798)
871#define OACEC5_1 _MMIO(0x279c)
872#define OACEC6_0 _MMIO(0x27a0)
873#define OACEC6_1 _MMIO(0x27a4)
874#define OACEC7_0 _MMIO(0x27a8)
875#define OACEC7_1 _MMIO(0x27ac)
876
877
878#define OA_PERFCNT1_LO _MMIO(0x91B8)
879#define OA_PERFCNT1_HI _MMIO(0x91BC)
880#define OA_PERFCNT2_LO _MMIO(0x91C0)
881#define OA_PERFCNT2_HI _MMIO(0x91C4)
882#define OA_PERFCNT3_LO _MMIO(0x91C8)
883#define OA_PERFCNT3_HI _MMIO(0x91CC)
884#define OA_PERFCNT4_LO _MMIO(0x91D8)
885#define OA_PERFCNT4_HI _MMIO(0x91DC)
886
887#define OA_PERFMATRIX_LO _MMIO(0x91C8)
888#define OA_PERFMATRIX_HI _MMIO(0x91CC)
889
890
891#define RPM_CONFIG0 _MMIO(0x0D00)
892#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
893#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
894#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
895#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
896#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
897#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
898#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
899#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
900#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
901#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
902#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
903#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
904
905#define RPM_CONFIG1 _MMIO(0x0D04)
906#define GEN10_GT_NOA_ENABLE (1 << 9)
907
908
909#define CTC_MODE _MMIO(0xA26C)
910#define CTC_SOURCE_PARAMETER_MASK 1
911#define CTC_SOURCE_CRYSTAL_CLOCK 0
912#define CTC_SOURCE_DIVIDE_LOGIC 1
913#define CTC_SHIFT_PARAMETER_SHIFT 1
914#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
915
916
917#define RCP_CONFIG _MMIO(0x0D08)
918
919
920#define HSW_MBVID2_NOA0 _MMIO(0x9E80)
921#define HSW_MBVID2_NOA1 _MMIO(0x9E84)
922#define HSW_MBVID2_NOA2 _MMIO(0x9E88)
923#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
924#define HSW_MBVID2_NOA4 _MMIO(0x9E90)
925#define HSW_MBVID2_NOA5 _MMIO(0x9E94)
926#define HSW_MBVID2_NOA6 _MMIO(0x9E98)
927#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
928#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
929#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
930
931#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
932
933
934#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
935
936#define MICRO_BP0_0 _MMIO(0x9800)
937#define MICRO_BP0_2 _MMIO(0x9804)
938#define MICRO_BP0_1 _MMIO(0x9808)
939
940#define MICRO_BP1_0 _MMIO(0x980C)
941#define MICRO_BP1_2 _MMIO(0x9810)
942#define MICRO_BP1_1 _MMIO(0x9814)
943
944#define MICRO_BP2_0 _MMIO(0x9818)
945#define MICRO_BP2_2 _MMIO(0x981C)
946#define MICRO_BP2_1 _MMIO(0x9820)
947
948#define MICRO_BP3_0 _MMIO(0x9824)
949#define MICRO_BP3_2 _MMIO(0x9828)
950#define MICRO_BP3_1 _MMIO(0x982C)
951
952#define MICRO_BP_TRIGGER _MMIO(0x9830)
953#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
954#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
955#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
956
957#define GDT_CHICKEN_BITS _MMIO(0x9840)
958#define GT_NOA_ENABLE 0x00000080
959
960#define NOA_DATA _MMIO(0x986C)
961#define NOA_WRITE _MMIO(0x9888)
962
963#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
964#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
965#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
966
967
968
969
970#define DEBUG_RESET_I830 _MMIO(0x6070)
971#define DEBUG_RESET_FULL (1 << 7)
972#define DEBUG_RESET_RENDER (1 << 8)
973#define DEBUG_RESET_DISPLAY (1 << 9)
974
975
976
977
978#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
979#define IOSF_DEVFN_SHIFT 24
980#define IOSF_OPCODE_SHIFT 16
981#define IOSF_PORT_SHIFT 8
982#define IOSF_BYTE_ENABLES_SHIFT 4
983#define IOSF_BAR_SHIFT 1
984#define IOSF_SB_BUSY (1 << 0)
985#define IOSF_PORT_BUNIT 0x03
986#define IOSF_PORT_PUNIT 0x04
987#define IOSF_PORT_NC 0x11
988#define IOSF_PORT_DPIO 0x12
989#define IOSF_PORT_GPIO_NC 0x13
990#define IOSF_PORT_CCK 0x14
991#define IOSF_PORT_DPIO_2 0x1a
992#define IOSF_PORT_FLISDSI 0x1b
993#define IOSF_PORT_GPIO_SC 0x48
994#define IOSF_PORT_GPIO_SUS 0xa8
995#define IOSF_PORT_CCU 0xa9
996#define CHV_IOSF_PORT_GPIO_N 0x13
997#define CHV_IOSF_PORT_GPIO_SE 0x48
998#define CHV_IOSF_PORT_GPIO_E 0xa8
999#define CHV_IOSF_PORT_GPIO_SW 0xb2
1000#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1001#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1002
1003
1004#define BUNIT_REG_BISOC 0x11
1005
1006#define PUNIT_REG_DSPFREQ 0x36
1007#define DSPFREQSTAT_SHIFT_CHV 24
1008#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1009#define DSPFREQGUAR_SHIFT_CHV 8
1010#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1011#define DSPFREQSTAT_SHIFT 30
1012#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1013#define DSPFREQGUAR_SHIFT 14
1014#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1015#define DSP_MAXFIFO_PM5_STATUS (1 << 22)
1016#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7)
1017#define DSP_MAXFIFO_PM5_ENABLE (1 << 6)
1018#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1019#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1020#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1021#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1022#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1023#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1024#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1025#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1026#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1027#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1028#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1029#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1030
1031
1032
1033
1034
1035
1036
1037
1038enum i915_power_well_id {
1039 DISP_PW_ID_NONE,
1040
1041 VLV_DISP_PW_DISP2D,
1042 BXT_DISP_PW_DPIO_CMN_A,
1043 VLV_DISP_PW_DPIO_CMN_BC,
1044 GLK_DISP_PW_DPIO_CMN_C,
1045 CHV_DISP_PW_DPIO_CMN_D,
1046 HSW_DISP_PW_GLOBAL,
1047 SKL_DISP_PW_MISC_IO,
1048 SKL_DISP_PW_1,
1049 SKL_DISP_PW_2,
1050};
1051
1052#define PUNIT_REG_PWRGT_CTRL 0x60
1053#define PUNIT_REG_PWRGT_STATUS 0x61
1054#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1055#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1056#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1057#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1058#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1059
1060#define PUNIT_PWGT_IDX_RENDER 0
1061#define PUNIT_PWGT_IDX_MEDIA 1
1062#define PUNIT_PWGT_IDX_DISP2D 3
1063#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1064#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1065#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1066#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1067#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1068#define PUNIT_PWGT_IDX_DPIO_RX0 10
1069#define PUNIT_PWGT_IDX_DPIO_RX1 11
1070#define PUNIT_PWGT_IDX_DPIO_CMN_D 12
1071
1072#define PUNIT_REG_GPU_LFM 0xd3
1073#define PUNIT_REG_GPU_FREQ_REQ 0xd4
1074#define PUNIT_REG_GPU_FREQ_STS 0xd8
1075#define GPLLENABLE (1 << 4)
1076#define GENFREQSTATUS (1 << 0)
1077#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1078#define PUNIT_REG_CZ_TIMESTAMP 0xce
1079
1080#define PUNIT_FUSE_BUS2 0xf6
1081#define PUNIT_FUSE_BUS1 0xf5
1082
1083#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1084#define FB_GFX_FREQ_FUSE_MASK 0xff
1085#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1086#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1087#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1088
1089#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1090#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1091
1092#define PUNIT_REG_DDR_SETUP2 0x139
1093#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1094#define FORCE_DDR_LOW_FREQ (1 << 1)
1095#define FORCE_DDR_HIGH_FREQ (1 << 0)
1096
1097#define PUNIT_GPU_STATUS_REG 0xdb
1098#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1099#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1100#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1101#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1102
1103#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1104#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1105#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1106
1107#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1108#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1109#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1110#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1111#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1112#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1113#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1114#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1115#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1116#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1117
1118#define VLV_TURBO_SOC_OVERRIDE 0x04
1119#define VLV_OVERRIDE_EN 1
1120#define VLV_SOC_TDP_EN (1 << 1)
1121#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1122#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1123
1124
1125#define CCK_FUSE_REG 0x8
1126#define CCK_FUSE_HPLL_FREQ_MASK 0x3
1127#define CCK_REG_DSI_PLL_FUSE 0x44
1128#define CCK_REG_DSI_PLL_CONTROL 0x48
1129#define DSI_PLL_VCO_EN (1 << 31)
1130#define DSI_PLL_LDO_GATE (1 << 30)
1131#define DSI_PLL_P1_POST_DIV_SHIFT 17
1132#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1133#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1134#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1135#define DSI_PLL_MUX_MASK (3 << 9)
1136#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1137#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1138#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1139#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1140#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1141#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1142#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1143#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1144#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1145#define DSI_PLL_LOCK (1 << 0)
1146#define CCK_REG_DSI_PLL_DIVIDER 0x4c
1147#define DSI_PLL_LFSR (1 << 31)
1148#define DSI_PLL_FRACTION_EN (1 << 30)
1149#define DSI_PLL_FRAC_COUNTER_SHIFT 27
1150#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1151#define DSI_PLL_USYNC_CNT_SHIFT 18
1152#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1153#define DSI_PLL_N1_DIV_SHIFT 16
1154#define DSI_PLL_N1_DIV_MASK (3 << 16)
1155#define DSI_PLL_M1_DIV_SHIFT 0
1156#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1157#define CCK_CZ_CLOCK_CONTROL 0x62
1158#define CCK_GPLL_CLOCK_CONTROL 0x67
1159#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1160#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1161#define CCK_TRUNK_FORCE_ON (1 << 17)
1162#define CCK_TRUNK_FORCE_OFF (1 << 16)
1163#define CCK_FREQUENCY_STATUS (0x1f << 8)
1164#define CCK_FREQUENCY_STATUS_SHIFT 8
1165#define CCK_FREQUENCY_VALUES (0x1f << 0)
1166
1167
1168#define DPIO_DEVFN 0
1169
1170#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1171#define DPIO_MODSEL1 (1 << 3)
1172#define DPIO_MODSEL0 (1 << 2)
1173#define DPIO_SFR_BYPASS (1 << 1)
1174#define DPIO_CMNRST (1 << 0)
1175
1176#define DPIO_PHY(pipe) ((pipe) >> 1)
1177#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1178
1179
1180
1181
1182#define _VLV_PLL_DW3_CH0 0x800c
1183#define DPIO_POST_DIV_SHIFT (28)
1184#define DPIO_POST_DIV_DAC 0
1185#define DPIO_POST_DIV_HDMIDP 1
1186#define DPIO_POST_DIV_LVDS1 2
1187#define DPIO_POST_DIV_LVDS2 3
1188#define DPIO_K_SHIFT (24)
1189#define DPIO_P1_SHIFT (21)
1190#define DPIO_P2_SHIFT (16)
1191#define DPIO_N_SHIFT (12)
1192#define DPIO_ENABLE_CALIBRATION (1 << 11)
1193#define DPIO_M1DIV_SHIFT (8)
1194#define DPIO_M2DIV_MASK 0xff
1195#define _VLV_PLL_DW3_CH1 0x802c
1196#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1197
1198#define _VLV_PLL_DW5_CH0 0x8014
1199#define DPIO_REFSEL_OVERRIDE 27
1200#define DPIO_PLL_MODESEL_SHIFT 24
1201#define DPIO_BIAS_CURRENT_CTL_SHIFT 21
1202#define DPIO_PLL_REFCLK_SEL_SHIFT 16
1203#define DPIO_PLL_REFCLK_SEL_MASK 3
1204#define DPIO_DRIVER_CTL_SHIFT 12
1205#define DPIO_CLK_BIAS_CTL_SHIFT 8
1206#define _VLV_PLL_DW5_CH1 0x8034
1207#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1208
1209#define _VLV_PLL_DW7_CH0 0x801c
1210#define _VLV_PLL_DW7_CH1 0x803c
1211#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1212
1213#define _VLV_PLL_DW8_CH0 0x8040
1214#define _VLV_PLL_DW8_CH1 0x8060
1215#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1216
1217#define VLV_PLL_DW9_BCAST 0xc044
1218#define _VLV_PLL_DW9_CH0 0x8044
1219#define _VLV_PLL_DW9_CH1 0x8064
1220#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1221
1222#define _VLV_PLL_DW10_CH0 0x8048
1223#define _VLV_PLL_DW10_CH1 0x8068
1224#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1225
1226#define _VLV_PLL_DW11_CH0 0x804c
1227#define _VLV_PLL_DW11_CH1 0x806c
1228#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1229
1230
1231#define VLV_REF_DW13 0x80ac
1232
1233#define VLV_CMN_DW0 0x8100
1234
1235
1236
1237
1238
1239#define _VLV_PCS_DW0_CH0 0x8200
1240#define _VLV_PCS_DW0_CH1 0x8400
1241#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
1242#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
1243#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
1244#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
1245#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1246
1247#define _VLV_PCS01_DW0_CH0 0x200
1248#define _VLV_PCS23_DW0_CH0 0x400
1249#define _VLV_PCS01_DW0_CH1 0x2600
1250#define _VLV_PCS23_DW0_CH1 0x2800
1251#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1252#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1253
1254#define _VLV_PCS_DW1_CH0 0x8204
1255#define _VLV_PCS_DW1_CH1 0x8404
1256#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
1257#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1258#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1259#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1260#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
1261#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1262
1263#define _VLV_PCS01_DW1_CH0 0x204
1264#define _VLV_PCS23_DW1_CH0 0x404
1265#define _VLV_PCS01_DW1_CH1 0x2604
1266#define _VLV_PCS23_DW1_CH1 0x2804
1267#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1268#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1269
1270#define _VLV_PCS_DW8_CH0 0x8220
1271#define _VLV_PCS_DW8_CH1 0x8420
1272#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1273#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1274#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1275
1276#define _VLV_PCS01_DW8_CH0 0x0220
1277#define _VLV_PCS23_DW8_CH0 0x0420
1278#define _VLV_PCS01_DW8_CH1 0x2620
1279#define _VLV_PCS23_DW8_CH1 0x2820
1280#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1281#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1282
1283#define _VLV_PCS_DW9_CH0 0x8224
1284#define _VLV_PCS_DW9_CH1 0x8424
1285#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
1286#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
1287#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
1288#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
1289#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
1290#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
1291#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1292
1293#define _VLV_PCS01_DW9_CH0 0x224
1294#define _VLV_PCS23_DW9_CH0 0x424
1295#define _VLV_PCS01_DW9_CH1 0x2624
1296#define _VLV_PCS23_DW9_CH1 0x2824
1297#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1298#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1299
1300#define _CHV_PCS_DW10_CH0 0x8228
1301#define _CHV_PCS_DW10_CH1 0x8428
1302#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
1303#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
1304#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
1305#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
1306#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
1307#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
1308#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
1309#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
1310#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1311
1312#define _VLV_PCS01_DW10_CH0 0x0228
1313#define _VLV_PCS23_DW10_CH0 0x0428
1314#define _VLV_PCS01_DW10_CH1 0x2628
1315#define _VLV_PCS23_DW10_CH1 0x2828
1316#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1317#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1318
1319#define _VLV_PCS_DW11_CH0 0x822c
1320#define _VLV_PCS_DW11_CH1 0x842c
1321#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
1322#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
1323#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
1324#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
1325#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1326
1327#define _VLV_PCS01_DW11_CH0 0x022c
1328#define _VLV_PCS23_DW11_CH0 0x042c
1329#define _VLV_PCS01_DW11_CH1 0x262c
1330#define _VLV_PCS23_DW11_CH1 0x282c
1331#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1332#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1333
1334#define _VLV_PCS01_DW12_CH0 0x0230
1335#define _VLV_PCS23_DW12_CH0 0x0430
1336#define _VLV_PCS01_DW12_CH1 0x2630
1337#define _VLV_PCS23_DW12_CH1 0x2830
1338#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1339#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1340
1341#define _VLV_PCS_DW12_CH0 0x8230
1342#define _VLV_PCS_DW12_CH1 0x8430
1343#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
1344#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
1345#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
1346#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
1347#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
1348#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1349
1350#define _VLV_PCS_DW14_CH0 0x8238
1351#define _VLV_PCS_DW14_CH1 0x8438
1352#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1353
1354#define _VLV_PCS_DW23_CH0 0x825c
1355#define _VLV_PCS_DW23_CH1 0x845c
1356#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1357
1358#define _VLV_TX_DW2_CH0 0x8288
1359#define _VLV_TX_DW2_CH1 0x8488
1360#define DPIO_SWING_MARGIN000_SHIFT 16
1361#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1362#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1363#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1364
1365#define _VLV_TX_DW3_CH0 0x828c
1366#define _VLV_TX_DW3_CH1 0x848c
1367
1368#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
1369#define DPIO_SWING_MARGIN101_SHIFT 16
1370#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1371#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1372
1373#define _VLV_TX_DW4_CH0 0x8290
1374#define _VLV_TX_DW4_CH1 0x8490
1375#define DPIO_SWING_DEEMPH9P5_SHIFT 24
1376#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1377#define DPIO_SWING_DEEMPH6P0_SHIFT 16
1378#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1379#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1380
1381#define _VLV_TX3_DW4_CH0 0x690
1382#define _VLV_TX3_DW4_CH1 0x2a90
1383#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1384
1385#define _VLV_TX_DW5_CH0 0x8294
1386#define _VLV_TX_DW5_CH1 0x8494
1387#define DPIO_TX_OCALINIT_EN (1 << 31)
1388#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1389
1390#define _VLV_TX_DW11_CH0 0x82ac
1391#define _VLV_TX_DW11_CH1 0x84ac
1392#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1393
1394#define _VLV_TX_DW14_CH0 0x82b8
1395#define _VLV_TX_DW14_CH1 0x84b8
1396#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1397
1398
1399#define _CHV_PLL_DW0_CH0 0x8000
1400#define _CHV_PLL_DW0_CH1 0x8180
1401#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1402
1403#define _CHV_PLL_DW1_CH0 0x8004
1404#define _CHV_PLL_DW1_CH1 0x8184
1405#define DPIO_CHV_N_DIV_SHIFT 8
1406#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1407#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1408
1409#define _CHV_PLL_DW2_CH0 0x8008
1410#define _CHV_PLL_DW2_CH1 0x8188
1411#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1412
1413#define _CHV_PLL_DW3_CH0 0x800c
1414#define _CHV_PLL_DW3_CH1 0x818c
1415#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1416#define DPIO_CHV_FIRST_MOD (0 << 8)
1417#define DPIO_CHV_SECOND_MOD (1 << 8)
1418#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1419#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1420#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1421
1422#define _CHV_PLL_DW6_CH0 0x8018
1423#define _CHV_PLL_DW6_CH1 0x8198
1424#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1425#define DPIO_CHV_INT_COEFF_SHIFT 8
1426#define DPIO_CHV_PROP_COEFF_SHIFT 0
1427#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1428
1429#define _CHV_PLL_DW8_CH0 0x8020
1430#define _CHV_PLL_DW8_CH1 0x81A0
1431#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1432#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1433#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1434
1435#define _CHV_PLL_DW9_CH0 0x8024
1436#define _CHV_PLL_DW9_CH1 0x81A4
1437#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1
1438#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1439#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1
1440#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1441
1442#define _CHV_CMN_DW0_CH0 0x8100
1443#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1444#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1445#define DPIO_ALLDL_POWERDOWN (1 << 1)
1446#define DPIO_ANYDL_POWERDOWN (1 << 0)
1447
1448#define _CHV_CMN_DW5_CH0 0x8114
1449#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1450#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1451#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1452#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1453#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1454#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1455#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1456#define CHV_BUFLEFTENA1_MASK (3 << 22)
1457
1458#define _CHV_CMN_DW13_CH0 0x8134
1459#define _CHV_CMN_DW0_CH1 0x8080
1460#define DPIO_CHV_S1_DIV_SHIFT 21
1461#define DPIO_CHV_P1_DIV_SHIFT 13
1462#define DPIO_CHV_P2_DIV_SHIFT 8
1463#define DPIO_CHV_K_DIV_SHIFT 4
1464#define DPIO_PLL_FREQLOCK (1 << 1)
1465#define DPIO_PLL_LOCK (1 << 0)
1466#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1467
1468#define _CHV_CMN_DW14_CH0 0x8138
1469#define _CHV_CMN_DW1_CH1 0x8084
1470#define DPIO_AFC_RECAL (1 << 14)
1471#define DPIO_DCLKP_EN (1 << 13)
1472#define CHV_BUFLEFTENA2_DISABLE (0 << 17)
1473#define CHV_BUFLEFTENA2_NORMAL (1 << 17)
1474#define CHV_BUFLEFTENA2_FORCE (3 << 17)
1475#define CHV_BUFLEFTENA2_MASK (3 << 17)
1476#define CHV_BUFRIGHTENA2_DISABLE (0 << 19)
1477#define CHV_BUFRIGHTENA2_NORMAL (1 << 19)
1478#define CHV_BUFRIGHTENA2_FORCE (3 << 19)
1479#define CHV_BUFRIGHTENA2_MASK (3 << 19)
1480#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1481
1482#define _CHV_CMN_DW19_CH0 0x814c
1483#define _CHV_CMN_DW6_CH1 0x8098
1484#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30
1485#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29
1486#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28)
1487#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1488
1489#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1490
1491#define CHV_CMN_DW28 0x8170
1492#define DPIO_CL1POWERDOWNEN (1 << 23)
1493#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1494#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1495#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1496#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1497#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1498
1499#define CHV_CMN_DW30 0x8178
1500#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1501#define DPIO_LRC_BYPASS (1 << 3)
1502
1503#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1504 (lane) * 0x200 + (offset))
1505
1506#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1507#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1508#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1509#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1510#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1511#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1512#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1513#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1514#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1515#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1516#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1517#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1518#define DPIO_FRC_LATENCY_SHFIT 8
1519#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1520#define DPIO_UPAR_SHIFT 30
1521
1522
1523#define _BXT_PHY0_BASE 0x6C000
1524#define _BXT_PHY1_BASE 0x162000
1525#define _BXT_PHY2_BASE 0x163000
1526#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1527 _BXT_PHY1_BASE, \
1528 _BXT_PHY2_BASE)
1529
1530#define _BXT_PHY(phy, reg) \
1531 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1532
1533#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1534 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1535 (reg_ch1) - _BXT_PHY0_BASE))
1536#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1537 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1538
1539#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1540#define MIPIO_RST_CTRL (1 << 2)
1541
1542#define _BXT_PHY_CTL_DDI_A 0x64C00
1543#define _BXT_PHY_CTL_DDI_B 0x64C10
1544#define _BXT_PHY_CTL_DDI_C 0x64C20
1545#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1546#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1547#define BXT_PHY_LANE_ENABLED (1 << 8)
1548#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1549 _BXT_PHY_CTL_DDI_B)
1550
1551#define _PHY_CTL_FAMILY_EDP 0x64C80
1552#define _PHY_CTL_FAMILY_DDI 0x64C90
1553#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1554#define COMMON_RESET_DIS (1 << 31)
1555#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1556 _PHY_CTL_FAMILY_EDP, \
1557 _PHY_CTL_FAMILY_DDI_C)
1558
1559
1560#define _PORT_PLL_A 0x46074
1561#define _PORT_PLL_B 0x46078
1562#define _PORT_PLL_C 0x4607c
1563#define PORT_PLL_ENABLE (1 << 31)
1564#define PORT_PLL_LOCK (1 << 30)
1565#define PORT_PLL_REF_SEL (1 << 27)
1566#define PORT_PLL_POWER_ENABLE (1 << 26)
1567#define PORT_PLL_POWER_STATE (1 << 25)
1568#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1569
1570#define _PORT_PLL_EBB_0_A 0x162034
1571#define _PORT_PLL_EBB_0_B 0x6C034
1572#define _PORT_PLL_EBB_0_C 0x6C340
1573#define PORT_PLL_P1_SHIFT 13
1574#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1575#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1576#define PORT_PLL_P2_SHIFT 8
1577#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1578#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1579#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1580 _PORT_PLL_EBB_0_B, \
1581 _PORT_PLL_EBB_0_C)
1582
1583#define _PORT_PLL_EBB_4_A 0x162038
1584#define _PORT_PLL_EBB_4_B 0x6C038
1585#define _PORT_PLL_EBB_4_C 0x6C344
1586#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1587#define PORT_PLL_RECALIBRATE (1 << 14)
1588#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1589 _PORT_PLL_EBB_4_B, \
1590 _PORT_PLL_EBB_4_C)
1591
1592#define _PORT_PLL_0_A 0x162100
1593#define _PORT_PLL_0_B 0x6C100
1594#define _PORT_PLL_0_C 0x6C380
1595
1596#define PORT_PLL_M2_MASK 0xFF
1597
1598#define PORT_PLL_N_SHIFT 8
1599#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1600#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1601
1602#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1603
1604#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1605
1606#define PORT_PLL_PROP_COEFF_MASK 0xF
1607#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1608#define PORT_PLL_INT_COEFF(x) ((x) << 8)
1609#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1610#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1611
1612#define PORT_PLL_TARGET_CNT_MASK 0x3FF
1613
1614#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1615#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1616
1617#define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
1618#define PORT_PLL_DCO_AMP_DEFAULT 15
1619#define PORT_PLL_DCO_AMP_MASK 0x3c00
1620#define PORT_PLL_DCO_AMP(x) ((x) << 10)
1621#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1622 _PORT_PLL_0_B, \
1623 _PORT_PLL_0_C)
1624#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1625 (idx) * 4)
1626
1627
1628#define _PORT_CL1CM_DW0_A 0x162000
1629#define _PORT_CL1CM_DW0_BC 0x6C000
1630#define PHY_POWER_GOOD (1 << 16)
1631#define PHY_RESERVED (1 << 7)
1632#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1633
1634#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1635#define CL_POWER_DOWN_ENABLE (1 << 4)
1636#define SUS_CLOCK_CONFIG (3 << 0)
1637
1638#define _ICL_PORT_CL_DW5_A 0x162014
1639#define _ICL_PORT_CL_DW5_B 0x6C014
1640#define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
1641 _ICL_PORT_CL_DW5_B)
1642
1643#define _CNL_PORT_CL_DW10_A 0x162028
1644#define _ICL_PORT_CL_DW10_B 0x6c028
1645#define ICL_PORT_CL_DW10(port) _MMIO_PORT(port, \
1646 _CNL_PORT_CL_DW10_A, \
1647 _ICL_PORT_CL_DW10_B)
1648#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1649#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1650#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1651#define PWR_UP_ALL_LANES (0x0 << 4)
1652#define PWR_DOWN_LN_3_2_1 (0xe << 4)
1653#define PWR_DOWN_LN_3_2 (0xc << 4)
1654#define PWR_DOWN_LN_3 (0x8 << 4)
1655#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1656#define PWR_DOWN_LN_1_0 (0x3 << 4)
1657#define PWR_DOWN_LN_1 (0x2 << 4)
1658#define PWR_DOWN_LN_3_1 (0xa << 4)
1659#define PWR_DOWN_LN_3_1_0 (0xb << 4)
1660#define PWR_DOWN_LN_MASK (0xf << 4)
1661#define PWR_DOWN_LN_SHIFT 4
1662
1663#define _PORT_CL1CM_DW9_A 0x162024
1664#define _PORT_CL1CM_DW9_BC 0x6C024
1665#define IREF0RC_OFFSET_SHIFT 8
1666#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1667#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1668
1669#define _PORT_CL1CM_DW10_A 0x162028
1670#define _PORT_CL1CM_DW10_BC 0x6C028
1671#define IREF1RC_OFFSET_SHIFT 8
1672#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1673#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1674
1675#define _ICL_PORT_CL_DW12_A 0x162030
1676#define _ICL_PORT_CL_DW12_B 0x6C030
1677#define ICL_LANE_ENABLE_AUX (1 << 0)
1678#define ICL_PORT_CL_DW12(port) _MMIO_PORT((port), \
1679 _ICL_PORT_CL_DW12_A, \
1680 _ICL_PORT_CL_DW12_B)
1681
1682#define _PORT_CL1CM_DW28_A 0x162070
1683#define _PORT_CL1CM_DW28_BC 0x6C070
1684#define OCL1_POWER_DOWN_EN (1 << 23)
1685#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1686#define SUS_CLK_CONFIG 0x3
1687#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1688
1689#define _PORT_CL1CM_DW30_A 0x162078
1690#define _PORT_CL1CM_DW30_BC 0x6C078
1691#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1692#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1693
1694#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1695#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1696#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1697#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1698#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1699#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1700#define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1701#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1702#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1703#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1704#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \
1705 _CNL_PORT_PCS_DW1_GRP_AE, \
1706 _CNL_PORT_PCS_DW1_GRP_B, \
1707 _CNL_PORT_PCS_DW1_GRP_C, \
1708 _CNL_PORT_PCS_DW1_GRP_D, \
1709 _CNL_PORT_PCS_DW1_GRP_AE, \
1710 _CNL_PORT_PCS_DW1_GRP_F))
1711
1712#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
1713 _CNL_PORT_PCS_DW1_LN0_AE, \
1714 _CNL_PORT_PCS_DW1_LN0_B, \
1715 _CNL_PORT_PCS_DW1_LN0_C, \
1716 _CNL_PORT_PCS_DW1_LN0_D, \
1717 _CNL_PORT_PCS_DW1_LN0_AE, \
1718 _CNL_PORT_PCS_DW1_LN0_F))
1719
1720#define _ICL_PORT_PCS_DW1_GRP_A 0x162604
1721#define _ICL_PORT_PCS_DW1_GRP_B 0x6C604
1722#define _ICL_PORT_PCS_DW1_LN0_A 0x162804
1723#define _ICL_PORT_PCS_DW1_LN0_B 0x6C804
1724#define _ICL_PORT_PCS_DW1_AUX_A 0x162304
1725#define _ICL_PORT_PCS_DW1_AUX_B 0x6c304
1726#define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\
1727 _ICL_PORT_PCS_DW1_GRP_A, \
1728 _ICL_PORT_PCS_DW1_GRP_B)
1729#define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \
1730 _ICL_PORT_PCS_DW1_LN0_A, \
1731 _ICL_PORT_PCS_DW1_LN0_B)
1732#define ICL_PORT_PCS_DW1_AUX(port) _MMIO_PORT(port, \
1733 _ICL_PORT_PCS_DW1_AUX_A, \
1734 _ICL_PORT_PCS_DW1_AUX_B)
1735#define COMMON_KEEPER_EN (1 << 26)
1736
1737
1738#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
1739#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
1740#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
1741#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
1742#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
1743#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
1744#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
1745#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
1746#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
1747#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
1748#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
1749 _CNL_PORT_TX_AE_GRP_OFFSET, \
1750 _CNL_PORT_TX_B_GRP_OFFSET, \
1751 _CNL_PORT_TX_B_GRP_OFFSET, \
1752 _CNL_PORT_TX_D_GRP_OFFSET, \
1753 _CNL_PORT_TX_AE_GRP_OFFSET, \
1754 _CNL_PORT_TX_F_GRP_OFFSET) + \
1755 4 * (dw))
1756#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
1757 _CNL_PORT_TX_AE_LN0_OFFSET, \
1758 _CNL_PORT_TX_B_LN0_OFFSET, \
1759 _CNL_PORT_TX_B_LN0_OFFSET, \
1760 _CNL_PORT_TX_D_LN0_OFFSET, \
1761 _CNL_PORT_TX_AE_LN0_OFFSET, \
1762 _CNL_PORT_TX_F_LN0_OFFSET) + \
1763 4 * (dw))
1764
1765#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
1766#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
1767#define _ICL_PORT_TX_DW2_GRP_A 0x162688
1768#define _ICL_PORT_TX_DW2_GRP_B 0x6C688
1769#define _ICL_PORT_TX_DW2_LN0_A 0x162888
1770#define _ICL_PORT_TX_DW2_LN0_B 0x6C888
1771#define _ICL_PORT_TX_DW2_AUX_A 0x162388
1772#define _ICL_PORT_TX_DW2_AUX_B 0x6c388
1773#define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \
1774 _ICL_PORT_TX_DW2_GRP_A, \
1775 _ICL_PORT_TX_DW2_GRP_B)
1776#define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \
1777 _ICL_PORT_TX_DW2_LN0_A, \
1778 _ICL_PORT_TX_DW2_LN0_B)
1779#define ICL_PORT_TX_DW2_AUX(port) _MMIO_PORT(port, \
1780 _ICL_PORT_TX_DW2_AUX_A, \
1781 _ICL_PORT_TX_DW2_AUX_B)
1782#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
1783#define SWING_SEL_UPPER_MASK (1 << 15)
1784#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
1785#define SWING_SEL_LOWER_MASK (0x7 << 11)
1786#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
1787#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
1788#define RCOMP_SCALAR(x) ((x) << 0)
1789#define RCOMP_SCALAR_MASK (0xFF << 0)
1790
1791#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
1792#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
1793#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
1794#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
1795#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
1796 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1797 _CNL_PORT_TX_DW4_LN0_AE)))
1798#define _ICL_PORT_TX_DW4_GRP_A 0x162690
1799#define _ICL_PORT_TX_DW4_GRP_B 0x6C690
1800#define _ICL_PORT_TX_DW4_LN0_A 0x162890
1801#define _ICL_PORT_TX_DW4_LN1_A 0x162990
1802#define _ICL_PORT_TX_DW4_LN0_B 0x6C890
1803#define _ICL_PORT_TX_DW4_AUX_A 0x162390
1804#define _ICL_PORT_TX_DW4_AUX_B 0x6c390
1805#define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \
1806 _ICL_PORT_TX_DW4_GRP_A, \
1807 _ICL_PORT_TX_DW4_GRP_B)
1808#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \
1809 _ICL_PORT_TX_DW4_LN0_A, \
1810 _ICL_PORT_TX_DW4_LN0_B) + \
1811 ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
1812 _ICL_PORT_TX_DW4_LN0_A)))
1813#define ICL_PORT_TX_DW4_AUX(port) _MMIO_PORT(port, \
1814 _ICL_PORT_TX_DW4_AUX_A, \
1815 _ICL_PORT_TX_DW4_AUX_B)
1816#define LOADGEN_SELECT (1 << 31)
1817#define POST_CURSOR_1(x) ((x) << 12)
1818#define POST_CURSOR_1_MASK (0x3F << 12)
1819#define POST_CURSOR_2(x) ((x) << 6)
1820#define POST_CURSOR_2_MASK (0x3F << 6)
1821#define CURSOR_COEFF(x) ((x) << 0)
1822#define CURSOR_COEFF_MASK (0x3F << 0)
1823
1824#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
1825#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
1826#define _ICL_PORT_TX_DW5_GRP_A 0x162694
1827#define _ICL_PORT_TX_DW5_GRP_B 0x6C694
1828#define _ICL_PORT_TX_DW5_LN0_A 0x162894
1829#define _ICL_PORT_TX_DW5_LN0_B 0x6C894
1830#define _ICL_PORT_TX_DW5_AUX_A 0x162394
1831#define _ICL_PORT_TX_DW5_AUX_B 0x6c394
1832#define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \
1833 _ICL_PORT_TX_DW5_GRP_A, \
1834 _ICL_PORT_TX_DW5_GRP_B)
1835#define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \
1836 _ICL_PORT_TX_DW5_LN0_A, \
1837 _ICL_PORT_TX_DW5_LN0_B)
1838#define ICL_PORT_TX_DW5_AUX(port) _MMIO_PORT(port, \
1839 _ICL_PORT_TX_DW5_AUX_A, \
1840 _ICL_PORT_TX_DW5_AUX_B)
1841#define TX_TRAINING_EN (1 << 31)
1842#define TAP2_DISABLE (1 << 30)
1843#define TAP3_DISABLE (1 << 29)
1844#define SCALING_MODE_SEL(x) ((x) << 18)
1845#define SCALING_MODE_SEL_MASK (0x7 << 18)
1846#define RTERM_SELECT(x) ((x) << 3)
1847#define RTERM_SELECT_MASK (0x7 << 3)
1848
1849#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
1850#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
1851#define N_SCALAR(x) ((x) << 24)
1852#define N_SCALAR_MASK (0x7F << 24)
1853
1854#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
1855 _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
1856
1857#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
1858#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
1859#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
1860#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
1861#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
1862#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
1863#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
1864#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
1865#define MG_TX1_LINK_PARAMS(port, ln) \
1866 MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1867 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1868 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1869
1870#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
1871#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
1872#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
1873#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
1874#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
1875#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
1876#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
1877#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
1878#define MG_TX2_LINK_PARAMS(port, ln) \
1879 MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1880 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1881 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1882#define CRI_USE_FS32 (1 << 5)
1883
1884#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
1885#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
1886#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
1887#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
1888#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
1889#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
1890#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
1891#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
1892#define MG_TX1_PISO_READLOAD(port, ln) \
1893 MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
1894 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
1895 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
1896
1897#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
1898#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
1899#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
1900#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
1901#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
1902#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
1903#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
1904#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
1905#define MG_TX2_PISO_READLOAD(port, ln) \
1906 MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
1907 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
1908 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
1909#define CRI_CALCINIT (1 << 1)
1910
1911#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
1912#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
1913#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
1914#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
1915#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
1916#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
1917#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
1918#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
1919#define MG_TX1_SWINGCTRL(port, ln) \
1920 MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
1921 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
1922 MG_TX_SWINGCTRL_TX1LN1_PORT1)
1923
1924#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
1925#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
1926#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
1927#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
1928#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
1929#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
1930#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
1931#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
1932#define MG_TX2_SWINGCTRL(port, ln) \
1933 MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
1934 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
1935 MG_TX_SWINGCTRL_TX2LN1_PORT1)
1936#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
1937#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
1938
1939#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
1940#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
1941#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
1942#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
1943#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
1944#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
1945#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
1946#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
1947#define MG_TX1_DRVCTRL(port, ln) \
1948 MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
1949 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
1950 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
1951
1952#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
1953#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
1954#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
1955#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
1956#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
1957#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
1958#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
1959#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
1960#define MG_TX2_DRVCTRL(port, ln) \
1961 MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
1962 MG_TX_DRVCTRL_TX2LN0_PORT2, \
1963 MG_TX_DRVCTRL_TX2LN1_PORT1)
1964#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
1965#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
1966#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
1967#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
1968#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
1969#define CRI_LOADGEN_SEL(x) ((x) << 12)
1970#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
1971
1972#define MG_CLKHUB_LN0_PORT1 0x16839C
1973#define MG_CLKHUB_LN1_PORT1 0x16879C
1974#define MG_CLKHUB_LN0_PORT2 0x16939C
1975#define MG_CLKHUB_LN1_PORT2 0x16979C
1976#define MG_CLKHUB_LN0_PORT3 0x16A39C
1977#define MG_CLKHUB_LN1_PORT3 0x16A79C
1978#define MG_CLKHUB_LN0_PORT4 0x16B39C
1979#define MG_CLKHUB_LN1_PORT4 0x16B79C
1980#define MG_CLKHUB(port, ln) \
1981 MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
1982 MG_CLKHUB_LN0_PORT2, \
1983 MG_CLKHUB_LN1_PORT1)
1984#define CFG_LOW_RATE_LKREN_EN (1 << 11)
1985
1986#define MG_TX_DCC_TX1LN0_PORT1 0x168110
1987#define MG_TX_DCC_TX1LN1_PORT1 0x168510
1988#define MG_TX_DCC_TX1LN0_PORT2 0x169110
1989#define MG_TX_DCC_TX1LN1_PORT2 0x169510
1990#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
1991#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
1992#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
1993#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
1994#define MG_TX1_DCC(port, ln) \
1995 MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
1996 MG_TX_DCC_TX1LN0_PORT2, \
1997 MG_TX_DCC_TX1LN1_PORT1)
1998#define MG_TX_DCC_TX2LN0_PORT1 0x168090
1999#define MG_TX_DCC_TX2LN1_PORT1 0x168490
2000#define MG_TX_DCC_TX2LN0_PORT2 0x169090
2001#define MG_TX_DCC_TX2LN1_PORT2 0x169490
2002#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2003#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2004#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2005#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
2006#define MG_TX2_DCC(port, ln) \
2007 MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
2008 MG_TX_DCC_TX2LN0_PORT2, \
2009 MG_TX_DCC_TX2LN1_PORT1)
2010#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2011#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2012#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
2013
2014#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2015#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2016#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2017#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2018#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2019#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2020#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2021#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
2022#define MG_DP_MODE(port, ln) \
2023 MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \
2024 MG_DP_MODE_LN0_ACU_PORT2, \
2025 MG_DP_MODE_LN1_ACU_PORT1)
2026#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2027#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2028#define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
2029#define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4)
2030#define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
2031#define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
2032#define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
2033
2034#define MG_MISC_SUS0_PORT1 0x168814
2035#define MG_MISC_SUS0_PORT2 0x169814
2036#define MG_MISC_SUS0_PORT3 0x16A814
2037#define MG_MISC_SUS0_PORT4 0x16B814
2038#define MG_MISC_SUS0(tc_port) \
2039 _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
2040#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14)
2041#define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14)
2042#define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12)
2043#define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11)
2044#define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10)
2045#define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7)
2046#define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6)
2047#define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5)
2048
2049
2050
2051
2052#define _PORT_CL2CM_DW6_A 0x162358
2053#define _PORT_CL2CM_DW6_BC 0x6C358
2054#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2055#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2056
2057#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
2058#define COMP_INIT (1 << 31)
2059#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
2060#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
2061#define PROCESS_INFO_DOT_0 (0 << 26)
2062#define PROCESS_INFO_DOT_1 (1 << 26)
2063#define PROCESS_INFO_DOT_4 (2 << 26)
2064#define PROCESS_INFO_MASK (7 << 26)
2065#define PROCESS_INFO_SHIFT 26
2066#define VOLTAGE_INFO_0_85V (0 << 24)
2067#define VOLTAGE_INFO_0_95V (1 << 24)
2068#define VOLTAGE_INFO_1_05V (2 << 24)
2069#define VOLTAGE_INFO_MASK (3 << 24)
2070#define VOLTAGE_INFO_SHIFT 24
2071#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
2072#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
2073
2074#define _ICL_PORT_COMP_DW0_A 0x162100
2075#define _ICL_PORT_COMP_DW0_B 0x6C100
2076#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
2077 _ICL_PORT_COMP_DW0_B)
2078#define _ICL_PORT_COMP_DW1_A 0x162104
2079#define _ICL_PORT_COMP_DW1_B 0x6C104
2080#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
2081 _ICL_PORT_COMP_DW1_B)
2082#define _ICL_PORT_COMP_DW3_A 0x16210C
2083#define _ICL_PORT_COMP_DW3_B 0x6C10C
2084#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
2085 _ICL_PORT_COMP_DW3_B)
2086#define _ICL_PORT_COMP_DW9_A 0x162124
2087#define _ICL_PORT_COMP_DW9_B 0x6C124
2088#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
2089 _ICL_PORT_COMP_DW9_B)
2090#define _ICL_PORT_COMP_DW10_A 0x162128
2091#define _ICL_PORT_COMP_DW10_B 0x6C128
2092#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
2093 _ICL_PORT_COMP_DW10_A, \
2094 _ICL_PORT_COMP_DW10_B)
2095
2096
2097#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
2098#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
2099#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
2100#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
2101#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
2102#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
2103#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
2104
2105
2106#define _PORT_REF_DW3_A 0x16218C
2107#define _PORT_REF_DW3_BC 0x6C18C
2108#define GRC_DONE (1 << 22)
2109#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2110
2111#define _PORT_REF_DW6_A 0x162198
2112#define _PORT_REF_DW6_BC 0x6C198
2113#define GRC_CODE_SHIFT 24
2114#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2115#define GRC_CODE_FAST_SHIFT 16
2116#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2117#define GRC_CODE_SLOW_SHIFT 8
2118#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2119#define GRC_CODE_NOM_MASK 0xFF
2120#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2121
2122#define _PORT_REF_DW8_A 0x1621A0
2123#define _PORT_REF_DW8_BC 0x6C1A0
2124#define GRC_DIS (1 << 15)
2125#define GRC_RDY_OVRD (1 << 1)
2126#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2127
2128
2129#define _PORT_PCS_DW10_LN01_A 0x162428
2130#define _PORT_PCS_DW10_LN01_B 0x6C428
2131#define _PORT_PCS_DW10_LN01_C 0x6C828
2132#define _PORT_PCS_DW10_GRP_A 0x162C28
2133#define _PORT_PCS_DW10_GRP_B 0x6CC28
2134#define _PORT_PCS_DW10_GRP_C 0x6CE28
2135#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2136 _PORT_PCS_DW10_LN01_B, \
2137 _PORT_PCS_DW10_LN01_C)
2138#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2139 _PORT_PCS_DW10_GRP_B, \
2140 _PORT_PCS_DW10_GRP_C)
2141
2142#define TX2_SWING_CALC_INIT (1 << 31)
2143#define TX1_SWING_CALC_INIT (1 << 30)
2144
2145#define _PORT_PCS_DW12_LN01_A 0x162430
2146#define _PORT_PCS_DW12_LN01_B 0x6C430
2147#define _PORT_PCS_DW12_LN01_C 0x6C830
2148#define _PORT_PCS_DW12_LN23_A 0x162630
2149#define _PORT_PCS_DW12_LN23_B 0x6C630
2150#define _PORT_PCS_DW12_LN23_C 0x6CA30
2151#define _PORT_PCS_DW12_GRP_A 0x162c30
2152#define _PORT_PCS_DW12_GRP_B 0x6CC30
2153#define _PORT_PCS_DW12_GRP_C 0x6CE30
2154#define LANESTAGGER_STRAP_OVRD (1 << 6)
2155#define LANE_STAGGER_MASK 0x1F
2156#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2157 _PORT_PCS_DW12_LN01_B, \
2158 _PORT_PCS_DW12_LN01_C)
2159#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2160 _PORT_PCS_DW12_LN23_B, \
2161 _PORT_PCS_DW12_LN23_C)
2162#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2163 _PORT_PCS_DW12_GRP_B, \
2164 _PORT_PCS_DW12_GRP_C)
2165
2166
2167#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2168 ((lane) & 1) * 0x80)
2169
2170#define _PORT_TX_DW2_LN0_A 0x162508
2171#define _PORT_TX_DW2_LN0_B 0x6C508
2172#define _PORT_TX_DW2_LN0_C 0x6C908
2173#define _PORT_TX_DW2_GRP_A 0x162D08
2174#define _PORT_TX_DW2_GRP_B 0x6CD08
2175#define _PORT_TX_DW2_GRP_C 0x6CF08
2176#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2177 _PORT_TX_DW2_LN0_B, \
2178 _PORT_TX_DW2_LN0_C)
2179#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2180 _PORT_TX_DW2_GRP_B, \
2181 _PORT_TX_DW2_GRP_C)
2182#define MARGIN_000_SHIFT 16
2183#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2184#define UNIQ_TRANS_SCALE_SHIFT 8
2185#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2186
2187#define _PORT_TX_DW3_LN0_A 0x16250C
2188#define _PORT_TX_DW3_LN0_B 0x6C50C
2189#define _PORT_TX_DW3_LN0_C 0x6C90C
2190#define _PORT_TX_DW3_GRP_A 0x162D0C
2191#define _PORT_TX_DW3_GRP_B 0x6CD0C
2192#define _PORT_TX_DW3_GRP_C 0x6CF0C
2193#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2194 _PORT_TX_DW3_LN0_B, \
2195 _PORT_TX_DW3_LN0_C)
2196#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2197 _PORT_TX_DW3_GRP_B, \
2198 _PORT_TX_DW3_GRP_C)
2199#define SCALE_DCOMP_METHOD (1 << 26)
2200#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2201
2202#define _PORT_TX_DW4_LN0_A 0x162510
2203#define _PORT_TX_DW4_LN0_B 0x6C510
2204#define _PORT_TX_DW4_LN0_C 0x6C910
2205#define _PORT_TX_DW4_GRP_A 0x162D10
2206#define _PORT_TX_DW4_GRP_B 0x6CD10
2207#define _PORT_TX_DW4_GRP_C 0x6CF10
2208#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2209 _PORT_TX_DW4_LN0_B, \
2210 _PORT_TX_DW4_LN0_C)
2211#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2212 _PORT_TX_DW4_GRP_B, \
2213 _PORT_TX_DW4_GRP_C)
2214#define DEEMPH_SHIFT 24
2215#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2216
2217#define _PORT_TX_DW5_LN0_A 0x162514
2218#define _PORT_TX_DW5_LN0_B 0x6C514
2219#define _PORT_TX_DW5_LN0_C 0x6C914
2220#define _PORT_TX_DW5_GRP_A 0x162D14
2221#define _PORT_TX_DW5_GRP_B 0x6CD14
2222#define _PORT_TX_DW5_GRP_C 0x6CF14
2223#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2224 _PORT_TX_DW5_LN0_B, \
2225 _PORT_TX_DW5_LN0_C)
2226#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2227 _PORT_TX_DW5_GRP_B, \
2228 _PORT_TX_DW5_GRP_C)
2229#define DCC_DELAY_RANGE_1 (1 << 9)
2230#define DCC_DELAY_RANGE_2 (1 << 8)
2231
2232#define _PORT_TX_DW14_LN0_A 0x162538
2233#define _PORT_TX_DW14_LN0_B 0x6C538
2234#define _PORT_TX_DW14_LN0_C 0x6C938
2235#define LATENCY_OPTIM_SHIFT 30
2236#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2237#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2238 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2239 _PORT_TX_DW14_LN0_C) + \
2240 _BXT_LANE_OFFSET(lane))
2241
2242
2243#define UAIMI_SPR1 _MMIO(0x4F074)
2244
2245#define SKL_VCCIO_MASK 0x1
2246
2247#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2248
2249#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
2250#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
2251
2252#define BALANCE_LEG_DISABLE_SHIFT 23
2253#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2266#define I830_FENCE_START_MASK 0x07f80000
2267#define I830_FENCE_TILING_Y_SHIFT 12
2268#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2269#define I830_FENCE_PITCH_SHIFT 4
2270#define I830_FENCE_REG_VALID (1 << 0)
2271#define I915_FENCE_MAX_PITCH_VAL 4
2272#define I830_FENCE_MAX_PITCH_VAL 6
2273#define I830_FENCE_MAX_SIZE_VAL (1 << 8)
2274
2275#define I915_FENCE_START_MASK 0x0ff00000
2276#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2277
2278#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2279#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2280#define I965_FENCE_PITCH_SHIFT 2
2281#define I965_FENCE_TILING_Y_SHIFT 1
2282#define I965_FENCE_REG_VALID (1 << 0)
2283#define I965_FENCE_MAX_PITCH_VAL 0x0400
2284
2285#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2286#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2287#define GEN6_FENCE_PITCH_SHIFT 32
2288#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2289
2290
2291
2292#define TILECTL _MMIO(0x101000)
2293#define TILECTL_SWZCTL (1 << 0)
2294#define TILECTL_TLBPF (1 << 1)
2295#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2296#define TILECTL_BACKSNOOP_DIS (1 << 3)
2297
2298
2299
2300
2301#define PGTBL_CTL _MMIO(0x02020)
2302#define PGTBL_ADDRESS_LO_MASK 0xfffff000
2303#define PGTBL_ADDRESS_HI_MASK 0x000000f0
2304#define PGTBL_ER _MMIO(0x02024)
2305#define PRB0_BASE (0x2030 - 0x30)
2306#define PRB1_BASE (0x2040 - 0x30)
2307#define PRB2_BASE (0x2050 - 0x30)
2308#define SRB0_BASE (0x2100 - 0x30)
2309#define SRB1_BASE (0x2110 - 0x30)
2310#define SRB2_BASE (0x2120 - 0x30)
2311#define SRB3_BASE (0x2130 - 0x30)
2312#define RENDER_RING_BASE 0x02000
2313#define BSD_RING_BASE 0x04000
2314#define GEN6_BSD_RING_BASE 0x12000
2315#define GEN8_BSD2_RING_BASE 0x1c000
2316#define GEN11_BSD_RING_BASE 0x1c0000
2317#define GEN11_BSD2_RING_BASE 0x1c4000
2318#define GEN11_BSD3_RING_BASE 0x1d0000
2319#define GEN11_BSD4_RING_BASE 0x1d4000
2320#define VEBOX_RING_BASE 0x1a000
2321#define GEN11_VEBOX_RING_BASE 0x1c8000
2322#define GEN11_VEBOX2_RING_BASE 0x1d8000
2323#define BLT_RING_BASE 0x22000
2324#define RING_TAIL(base) _MMIO((base) + 0x30)
2325#define RING_HEAD(base) _MMIO((base) + 0x34)
2326#define RING_START(base) _MMIO((base) + 0x38)
2327#define RING_CTL(base) _MMIO((base) + 0x3c)
2328#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE)
2329#define RING_SYNC_0(base) _MMIO((base) + 0x40)
2330#define RING_SYNC_1(base) _MMIO((base) + 0x44)
2331#define RING_SYNC_2(base) _MMIO((base) + 0x48)
2332#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2333#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2334#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2335#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2336#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2337#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2338#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2339#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2340#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2341#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2342#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2343#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2344#define GEN6_NOSYNC INVALID_MMIO_REG
2345#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
2346#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
2347#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
2348#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2349#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
2350#define RESET_CTL_REQUEST_RESET (1 << 0)
2351#define RESET_CTL_READY_TO_RESET (1 << 1)
2352#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2353
2354#define HSW_GTT_CACHE_EN _MMIO(0x4024)
2355#define GTT_CACHE_EN_ALL 0xF0007FFF
2356#define GEN7_WR_WATERMARK _MMIO(0x4028)
2357#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2358#define ARB_MODE _MMIO(0x4030)
2359#define ARB_MODE_SWIZZLE_SNB (1 << 4)
2360#define ARB_MODE_SWIZZLE_IVB (1 << 5)
2361#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2362#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2363
2364#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2365#define GEN7_LRA_LIMITS_REG_NUM 13
2366#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2367#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2368
2369#define GAMTARBMODE _MMIO(0x04a08)
2370#define ARB_MODE_BWGTLB_DISABLE (1 << 9)
2371#define ARB_MODE_SWIZZLE_BDW (1 << 1)
2372#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2373#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2374#define GEN8_RING_FAULT_REG _MMIO(0x4094)
2375#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2376#define RING_FAULT_GTTSEL_MASK (1 << 11)
2377#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2378#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2379#define RING_FAULT_VALID (1 << 0)
2380#define DONE_REG _MMIO(0x40b0)
2381#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2382#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2383#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
2384#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2385#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2386#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2387#define RING_ACTHD(base) _MMIO((base) + 0x74)
2388#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
2389#define RING_NOPID(base) _MMIO((base) + 0x94)
2390#define RING_IMR(base) _MMIO((base) + 0xa8)
2391#define RING_HWSTAM(base) _MMIO((base) + 0x98)
2392#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
2393#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
2394#define TAIL_ADDR 0x001FFFF8
2395#define HEAD_WRAP_COUNT 0xFFE00000
2396#define HEAD_WRAP_ONE 0x00200000
2397#define HEAD_ADDR 0x001FFFFC
2398#define RING_NR_PAGES 0x001FF000
2399#define RING_REPORT_MASK 0x00000006
2400#define RING_REPORT_64K 0x00000002
2401#define RING_REPORT_128K 0x00000004
2402#define RING_NO_REPORT 0x00000000
2403#define RING_VALID_MASK 0x00000001
2404#define RING_VALID 0x00000001
2405#define RING_INVALID 0x00000000
2406#define RING_WAIT_I8XX (1 << 0)
2407#define RING_WAIT (1 << 11)
2408#define RING_WAIT_SEMAPHORE (1 << 10)
2409
2410#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2411#define RING_MAX_NONPRIV_SLOTS 12
2412
2413#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2414
2415#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2416#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
2417
2418#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2419#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2420
2421#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2422#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
2423#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
2424#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
2425
2426#if 0
2427#define PRB0_TAIL _MMIO(0x2030)
2428#define PRB0_HEAD _MMIO(0x2034)
2429#define PRB0_START _MMIO(0x2038)
2430#define PRB0_CTL _MMIO(0x203c)
2431#define PRB1_TAIL _MMIO(0x2040)
2432#define PRB1_HEAD _MMIO(0x2044)
2433#define PRB1_START _MMIO(0x2048)
2434#define PRB1_CTL _MMIO(0x204c)
2435#endif
2436#define IPEIR_I965 _MMIO(0x2064)
2437#define IPEHR_I965 _MMIO(0x2068)
2438#define GEN7_SC_INSTDONE _MMIO(0x7100)
2439#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2440#define GEN7_ROW_INSTDONE _MMIO(0xe164)
2441#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2442#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2443#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2444#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2445#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2446#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2447#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2448#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2449#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
2450#define RING_IPEIR(base) _MMIO((base) + 0x64)
2451#define RING_IPEHR(base) _MMIO((base) + 0x68)
2452
2453
2454
2455
2456
2457#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
2458#define RING_INSTPS(base) _MMIO((base) + 0x70)
2459#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
2460#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60)
2461#define RING_INSTPM(base) _MMIO((base) + 0xc0)
2462#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
2463#define INSTPS _MMIO(0x2070)
2464#define GEN4_INSTDONE1 _MMIO(0x207c)
2465#define ACTHD_I965 _MMIO(0x2074)
2466#define HWS_PGA _MMIO(0x2080)
2467#define HWS_ADDRESS_MASK 0xfffff000
2468#define HWS_START_ADDRESS_SHIFT 4
2469#define PWRCTXA _MMIO(0x2088)
2470#define PWRCTX_EN (1 << 0)
2471#define IPEIR _MMIO(0x2088)
2472#define IPEHR _MMIO(0x208c)
2473#define GEN2_INSTDONE _MMIO(0x2090)
2474#define NOPID _MMIO(0x2094)
2475#define HWSTAM _MMIO(0x2098)
2476#define DMA_FADD_I8XX _MMIO(0x20d0)
2477#define RING_BBSTATE(base) _MMIO((base) + 0x110)
2478#define RING_BB_PPGTT (1 << 5)
2479#define RING_SBBADDR(base) _MMIO((base) + 0x114)
2480#define RING_SBBSTATE(base) _MMIO((base) + 0x118)
2481#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c)
2482#define RING_BBADDR(base) _MMIO((base) + 0x140)
2483#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168)
2484#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0)
2485#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4)
2486#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8)
2487#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8)
2488
2489#define ERROR_GEN6 _MMIO(0x40a0)
2490#define GEN7_ERR_INT _MMIO(0x44040)
2491#define ERR_INT_POISON (1 << 31)
2492#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
2493#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
2494#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
2495#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
2496#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
2497#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
2498#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
2499#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
2500#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
2501
2502#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2503#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2504#define FAULT_VA_HIGH_BITS (0xf << 0)
2505#define FAULT_GTT_SEL (1 << 4)
2506
2507#define FPGA_DBG _MMIO(0x42300)
2508#define FPGA_DBG_RM_NOCLAIM (1 << 31)
2509
2510#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2511#define CLAIM_ER_CLR (1 << 31)
2512#define CLAIM_ER_OVERFLOW (1 << 16)
2513#define CLAIM_ER_CTR_MASK 0xffff
2514
2515#define DERRMR _MMIO(0x44050)
2516
2517#define DERRMR_PIPEA_SCANLINE (1 << 0)
2518#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
2519#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
2520#define DERRMR_PIPEA_VBLANK (1 << 3)
2521#define DERRMR_PIPEA_HBLANK (1 << 5)
2522#define DERRMR_PIPEB_SCANLINE (1 << 8)
2523#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
2524#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
2525#define DERRMR_PIPEB_VBLANK (1 << 11)
2526#define DERRMR_PIPEB_HBLANK (1 << 13)
2527
2528#define DERRMR_PIPEC_SCANLINE (1 << 14)
2529#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
2530#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
2531#define DERRMR_PIPEC_VBLANK (1 << 21)
2532#define DERRMR_PIPEC_HBLANK (1 << 22)
2533
2534
2535
2536
2537
2538
2539#define _3D_CHICKEN _MMIO(0x2084)
2540#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2541#define _3D_CHICKEN2 _MMIO(0x208c)
2542
2543#define FF_SLICE_CHICKEN _MMIO(0x2088)
2544#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
2545
2546
2547
2548
2549
2550# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2551#define _3D_CHICKEN3 _MMIO(0x2090)
2552#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
2553#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2554#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2555#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2556#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1)
2557#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1)
2558
2559#define MI_MODE _MMIO(0x209c)
2560# define VS_TIMER_DISPATCH (1 << 6)
2561# define MI_FLUSH_ENABLE (1 << 12)
2562# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2563# define MODE_IDLE (1 << 9)
2564# define STOP_RING (1 << 8)
2565
2566#define GEN6_GT_MODE _MMIO(0x20d0)
2567#define GEN7_GT_MODE _MMIO(0x7008)
2568#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2569#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2570#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2571#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2572#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2573#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2574#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2575#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2576
2577
2578#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2579#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2580
2581
2582#define GEN8_STATE_ACK _MMIO(0x20F0)
2583#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2584#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2585#define GEN9_STATE_ACK_TDL0 (1 << 12)
2586#define GEN9_STATE_ACK_TDL1 (1 << 13)
2587#define GEN9_STATE_ACK_TDL2 (1 << 14)
2588#define GEN9_STATE_ACK_TDL3 (1 << 15)
2589#define GEN9_SUBSLICE_TDL_ACK_BITS \
2590 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2591 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2592
2593#define GFX_MODE _MMIO(0x2520)
2594#define GFX_MODE_GEN7 _MMIO(0x229c)
2595#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
2596#define GFX_RUN_LIST_ENABLE (1 << 15)
2597#define GFX_INTERRUPT_STEERING (1 << 14)
2598#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
2599#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
2600#define GFX_REPLAY_MODE (1 << 11)
2601#define GFX_PSMI_GRANULARITY (1 << 10)
2602#define GFX_PPGTT_ENABLE (1 << 9)
2603#define GEN8_GFX_PPGTT_48B (1 << 7)
2604
2605#define GFX_FORWARD_VBLANK_MASK (3 << 5)
2606#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
2607#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
2608#define GFX_FORWARD_VBLANK_COND (2 << 5)
2609
2610#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2611
2612#define VLV_DISPLAY_BASE 0x180000
2613#define VLV_MIPI_BASE VLV_DISPLAY_BASE
2614#define BXT_MIPI_BASE 0x60000
2615
2616#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2617#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2618#define SCPD0 _MMIO(0x209c)
2619#define IER _MMIO(0x20a0)
2620#define IIR _MMIO(0x20a4)
2621#define IMR _MMIO(0x20a8)
2622#define ISR _MMIO(0x20ac)
2623#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2624#define GINT_DIS (1 << 22)
2625#define GCFG_DIS (1 << 8)
2626#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2627#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2628#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2629#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2630#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2631#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2632#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2633#define VLV_PCBR_ADDR_SHIFT 12
2634
2635#define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane)))
2636#define EIR _MMIO(0x20b0)
2637#define EMR _MMIO(0x20b4)
2638#define ESR _MMIO(0x20b8)
2639#define GM45_ERROR_PAGE_TABLE (1 << 5)
2640#define GM45_ERROR_MEM_PRIV (1 << 4)
2641#define I915_ERROR_PAGE_TABLE (1 << 4)
2642#define GM45_ERROR_CP_PRIV (1 << 3)
2643#define I915_ERROR_MEMORY_REFRESH (1 << 1)
2644#define I915_ERROR_INSTRUCTION (1 << 0)
2645#define INSTPM _MMIO(0x20c0)
2646#define INSTPM_SELF_EN (1 << 12)
2647#define INSTPM_AGPBUSY_INT_EN (1 << 11)
2648
2649
2650#define INSTPM_FORCE_ORDERING (1 << 7)
2651#define INSTPM_TLB_INVALIDATE (1 << 9)
2652#define INSTPM_SYNC_FLUSH (1 << 5)
2653#define ACTHD _MMIO(0x20c8)
2654#define MEM_MODE _MMIO(0x20cc)
2655#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3)
2656#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2)
2657#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2658#define FW_BLC _MMIO(0x20d8)
2659#define FW_BLC2 _MMIO(0x20dc)
2660#define FW_BLC_SELF _MMIO(0x20e0)
2661#define FW_BLC_SELF_EN_MASK (1 << 31)
2662#define FW_BLC_SELF_FIFO_MASK (1 << 16)
2663#define FW_BLC_SELF_EN (1 << 15)
2664#define MM_BURST_LENGTH 0x00700000
2665#define MM_FIFO_WATERMARK 0x0001F000
2666#define LM_BURST_LENGTH 0x00000700
2667#define LM_FIFO_WATERMARK 0x0000001F
2668#define MI_ARB_STATE _MMIO(0x20e4)
2669
2670#define MBUS_ABOX_CTL _MMIO(0x45038)
2671#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2672#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2673#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
2674#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
2675#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
2676#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
2677#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
2678#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
2679
2680#define _PIPEA_MBUS_DBOX_CTL 0x7003C
2681#define _PIPEB_MBUS_DBOX_CTL 0x7103C
2682#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2683 _PIPEB_MBUS_DBOX_CTL)
2684#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
2685#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
2686#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
2687#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
2688#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
2689#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
2690
2691#define MBUS_UBOX_CTL _MMIO(0x4503C)
2692#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2693#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
2694
2695
2696
2697
2698#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2699
2700
2701
2702
2703
2704#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2705
2706
2707
2708
2709#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2710#define MI_ARB_BLOCK_GRANT_8 (0 << 12)
2711#define MI_ARB_BLOCK_GRANT_4 (1 << 12)
2712#define MI_ARB_BLOCK_GRANT_2 (2 << 12)
2713#define MI_ARB_BLOCK_GRANT_0 (3 << 12)
2714
2715
2716
2717
2718
2719#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2720
2721
2722
2723
2724#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2725
2726
2727
2728#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
2729
2730
2731
2732
2733#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2734
2735
2736#define MI_ARB_TIME_SLICE_MASK (7 << 5)
2737#define MI_ARB_TIME_SLICE_1 (0 << 5)
2738#define MI_ARB_TIME_SLICE_2 (1 << 5)
2739#define MI_ARB_TIME_SLICE_4 (2 << 5)
2740#define MI_ARB_TIME_SLICE_6 (3 << 5)
2741#define MI_ARB_TIME_SLICE_8 (4 << 5)
2742#define MI_ARB_TIME_SLICE_10 (5 << 5)
2743#define MI_ARB_TIME_SLICE_14 (6 << 5)
2744#define MI_ARB_TIME_SLICE_16 (7 << 5)
2745
2746
2747#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4)
2748#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2749
2750
2751#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2752
2753
2754#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0)
2755#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0)
2756
2757#define MI_STATE _MMIO(0x20e4)
2758#define MI_AGPBUSY_INT_EN (1 << 1)
2759#define MI_AGPBUSY_830_MODE (1 << 0)
2760
2761#define CACHE_MODE_0 _MMIO(0x2120)
2762#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
2763#define CM0_IZ_OPT_DISABLE (1 << 6)
2764#define CM0_ZR_OPT_DISABLE (1 << 5)
2765#define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
2766#define CM0_DEPTH_EVICT_DISABLE (1 << 4)
2767#define CM0_COLOR_EVICT_DISABLE (1 << 3)
2768#define CM0_DEPTH_WRITE_DISABLE (1 << 1)
2769#define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
2770#define GFX_FLSH_CNTL _MMIO(0x2170)
2771#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
2772#define GFX_FLSH_CNTL_EN (1 << 0)
2773#define ECOSKPD _MMIO(0x21d0)
2774#define ECO_GATING_CX_ONLY (1 << 3)
2775#define ECO_FLIP_DONE (1 << 0)
2776
2777#define CACHE_MODE_0_GEN7 _MMIO(0x7000)
2778#define RC_OP_FLUSH_ENABLE (1 << 0)
2779#define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
2780#define CACHE_MODE_1 _MMIO(0x7004)
2781#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
2782#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
2783#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
2784
2785#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
2786#define GEN6_BLITTER_LOCK_SHIFT 16
2787#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
2788
2789#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2790#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
2791#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2792#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
2793
2794#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2795#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2796
2797
2798#define HSW_PAVP_FUSE1 _MMIO(0x911C)
2799#define HSW_F1_EU_DIS_SHIFT 16
2800#define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT)
2801#define HSW_F1_EU_DIS_10EUS 0
2802#define HSW_F1_EU_DIS_8EUS 1
2803#define HSW_F1_EU_DIS_6EUS 2
2804
2805#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2806#define CHV_FGT_DISABLE_SS0 (1 << 10)
2807#define CHV_FGT_DISABLE_SS1 (1 << 11)
2808#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2809#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2810#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2811#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2812#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2813#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2814#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2815#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2816
2817#define GEN8_FUSE2 _MMIO(0x9120)
2818#define GEN8_F2_SS_DIS_SHIFT 21
2819#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
2820#define GEN8_F2_S_ENA_SHIFT 25
2821#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2822
2823#define GEN9_F2_SS_DIS_SHIFT 20
2824#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2825
2826#define GEN10_F2_S_ENA_SHIFT 22
2827#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
2828#define GEN10_F2_SS_DIS_SHIFT 18
2829#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
2830
2831#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
2832#define GEN10_L3BANK_PAIR_COUNT 4
2833#define GEN10_L3BANK_MASK 0x0F
2834
2835#define GEN8_EU_DISABLE0 _MMIO(0x9134)
2836#define GEN8_EU_DIS0_S0_MASK 0xffffff
2837#define GEN8_EU_DIS0_S1_SHIFT 24
2838#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2839
2840#define GEN8_EU_DISABLE1 _MMIO(0x9138)
2841#define GEN8_EU_DIS1_S1_MASK 0xffff
2842#define GEN8_EU_DIS1_S2_SHIFT 16
2843#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2844
2845#define GEN8_EU_DISABLE2 _MMIO(0x913c)
2846#define GEN8_EU_DIS2_S2_MASK 0xff
2847
2848#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
2849
2850#define GEN10_EU_DISABLE3 _MMIO(0x9140)
2851#define GEN10_EU_DIS_SS_MASK 0xff
2852
2853#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
2854#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
2855#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
2856#define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
2857
2858#define GEN11_EU_DISABLE _MMIO(0x9134)
2859#define GEN11_EU_DIS_MASK 0xFF
2860
2861#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
2862#define GEN11_GT_S_ENA_MASK 0xFF
2863
2864#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
2865
2866#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
2867#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2868#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2869#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2870#define GEN6_BSD_GO_INDICATOR (1 << 4)
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2884#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2885#define GT_BLT_USER_INTERRUPT (1 << 22)
2886#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2887#define GT_BSD_USER_INTERRUPT (1 << 12)
2888#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11)
2889#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2890#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5)
2891#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2892#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2893#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2894#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2895#define GT_RENDER_USER_INTERRUPT (1 << 0)
2896
2897#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12)
2898#define PM_VEBOX_USER_INTERRUPT (1 << 10)
2899
2900#define GT_PARITY_ERROR(dev_priv) \
2901 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2902 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2903
2904
2905#define ILK_BSD_USER_INTERRUPT (1 << 5)
2906
2907#define I915_PM_INTERRUPT (1 << 31)
2908#define I915_ISP_INTERRUPT (1 << 22)
2909#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
2910#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
2911#define I915_MIPIC_INTERRUPT (1 << 19)
2912#define I915_MIPIA_INTERRUPT (1 << 18)
2913#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
2914#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
2915#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
2916#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
2917#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
2918#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14)
2919#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
2920#define I915_HWB_OOM_INTERRUPT (1 << 13)
2921#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
2922#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
2923#define I915_MISC_INTERRUPT (1 << 11)
2924#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
2925#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
2926#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
2927#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
2928#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
2929#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
2930#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
2931#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
2932#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
2933#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
2934#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
2935#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
2936#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
2937#define I915_DEBUG_INTERRUPT (1 << 2)
2938#define I915_WINVALID_INTERRUPT (1 << 1)
2939#define I915_USER_INTERRUPT (1 << 1)
2940#define I915_ASLE_INTERRUPT (1 << 0)
2941#define I915_BSD_USER_INTERRUPT (1 << 25)
2942
2943#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
2944#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
2945
2946
2947#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
2948#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
2949
2950#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
2951#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
2952#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
2953#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
2954 _VLV_AUD_PORT_EN_B_DBG, \
2955 _VLV_AUD_PORT_EN_C_DBG, \
2956 _VLV_AUD_PORT_EN_D_DBG)
2957#define VLV_AMP_MUTE (1 << 1)
2958
2959#define GEN6_BSD_RNCID _MMIO(0x12198)
2960
2961#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2962#define GEN7_FF_SCHED_MASK 0x0077070
2963#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2964#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
2965#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
2966#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
2967#define GEN7_FF_TS_SCHED_HW (0x0 << 16)
2968#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
2969#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
2970#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
2971#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12)
2972#define GEN7_FF_VS_SCHED_HW (0x0 << 12)
2973#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
2974#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
2975#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4)
2976#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
2977
2978
2979
2980
2981
2982#define FBC_CFB_BASE _MMIO(0x3200)
2983#define FBC_LL_BASE _MMIO(0x3204)
2984#define FBC_CONTROL _MMIO(0x3208)
2985#define FBC_CTL_EN (1 << 31)
2986#define FBC_CTL_PERIODIC (1 << 30)
2987#define FBC_CTL_INTERVAL_SHIFT (16)
2988#define FBC_CTL_UNCOMPRESSIBLE (1 << 14)
2989#define FBC_CTL_C3_IDLE (1 << 13)
2990#define FBC_CTL_STRIDE_SHIFT (5)
2991#define FBC_CTL_FENCENO_SHIFT (0)
2992#define FBC_COMMAND _MMIO(0x320c)
2993#define FBC_CMD_COMPRESS (1 << 0)
2994#define FBC_STATUS _MMIO(0x3210)
2995#define FBC_STAT_COMPRESSING (1 << 31)
2996#define FBC_STAT_COMPRESSED (1 << 30)
2997#define FBC_STAT_MODIFIED (1 << 29)
2998#define FBC_STAT_CURRENT_LINE_SHIFT (0)
2999#define FBC_CONTROL2 _MMIO(0x3214)
3000#define FBC_CTL_FENCE_DBL (0 << 4)
3001#define FBC_CTL_IDLE_IMM (0 << 2)
3002#define FBC_CTL_IDLE_FULL (1 << 2)
3003#define FBC_CTL_IDLE_LINE (2 << 2)
3004#define FBC_CTL_IDLE_DEBUG (3 << 2)
3005#define FBC_CTL_CPU_FENCE (1 << 1)
3006#define FBC_CTL_PLANE(plane) ((plane) << 0)
3007#define FBC_FENCE_OFF _MMIO(0x3218)
3008#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
3009
3010#define FBC_LL_SIZE (1536)
3011
3012#define FBC_LLC_READ_CTRL _MMIO(0x9044)
3013#define FBC_LLC_FULLY_OPEN (1 << 30)
3014
3015
3016#define DPFC_CB_BASE _MMIO(0x3200)
3017#define DPFC_CONTROL _MMIO(0x3208)
3018#define DPFC_CTL_EN (1 << 31)
3019#define DPFC_CTL_PLANE(plane) ((plane) << 30)
3020#define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29)
3021#define DPFC_CTL_FENCE_EN (1 << 29)
3022#define IVB_DPFC_CTL_FENCE_EN (1 << 28)
3023#define DPFC_CTL_PERSISTENT_MODE (1 << 25)
3024#define DPFC_SR_EN (1 << 10)
3025#define DPFC_CTL_LIMIT_1X (0 << 6)
3026#define DPFC_CTL_LIMIT_2X (1 << 6)
3027#define DPFC_CTL_LIMIT_4X (2 << 6)
3028#define DPFC_RECOMP_CTL _MMIO(0x320c)
3029#define DPFC_RECOMP_STALL_EN (1 << 27)
3030#define DPFC_RECOMP_STALL_WM_SHIFT (16)
3031#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3032#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3033#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3034#define DPFC_STATUS _MMIO(0x3210)
3035#define DPFC_INVAL_SEG_SHIFT (16)
3036#define DPFC_INVAL_SEG_MASK (0x07ff0000)
3037#define DPFC_COMP_SEG_SHIFT (0)
3038#define DPFC_COMP_SEG_MASK (0x000007ff)
3039#define DPFC_STATUS2 _MMIO(0x3214)
3040#define DPFC_FENCE_YOFF _MMIO(0x3218)
3041#define DPFC_CHICKEN _MMIO(0x3224)
3042#define DPFC_HT_MODIFY (1 << 31)
3043
3044
3045#define ILK_DPFC_CB_BASE _MMIO(0x43200)
3046#define ILK_DPFC_CONTROL _MMIO(0x43208)
3047#define FBC_CTL_FALSE_COLOR (1 << 10)
3048
3049#define DPFC_RESERVED (0x1FFFFF00)
3050#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3051#define ILK_DPFC_STATUS _MMIO(0x43210)
3052#define ILK_DPFC_COMP_SEG_MASK 0x7ff
3053#define IVB_FBC_STATUS2 _MMIO(0x43214)
3054#define IVB_FBC_COMP_SEG_MASK 0x7ff
3055#define BDW_FBC_COMP_SEG_MASK 0xfff
3056#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3057#define ILK_DPFC_CHICKEN _MMIO(0x43224)
3058#define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3059#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
3060#define ILK_FBC_RT_BASE _MMIO(0x2128)
3061#define ILK_FBC_RT_VALID (1 << 0)
3062#define SNB_FBC_FRONT_BUFFER (1 << 1)
3063
3064#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3065#define ILK_FBCQ_DIS (1 << 22)
3066#define ILK_PABSTRETCH_DIS (1 << 21)
3067
3068
3069
3070
3071
3072
3073
3074#define SNB_DPFC_CTL_SA _MMIO(0x100100)
3075#define SNB_CPU_FENCE_ENABLE (1 << 29)
3076#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3077
3078
3079#define IVB_FBC_RT_BASE _MMIO(0x7020)
3080
3081#define IPS_CTL _MMIO(0x43408)
3082#define IPS_ENABLE (1 << 31)
3083
3084#define MSG_FBC_REND_STATE _MMIO(0x50380)
3085#define FBC_REND_NUKE (1 << 2)
3086#define FBC_REND_CACHE_CLEAN (1 << 1)
3087
3088
3089
3090
3091#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3092 4 * (gpio))
3093
3094# define GPIO_CLOCK_DIR_MASK (1 << 0)
3095# define GPIO_CLOCK_DIR_IN (0 << 1)
3096# define GPIO_CLOCK_DIR_OUT (1 << 1)
3097# define GPIO_CLOCK_VAL_MASK (1 << 2)
3098# define GPIO_CLOCK_VAL_OUT (1 << 3)
3099# define GPIO_CLOCK_VAL_IN (1 << 4)
3100# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3101# define GPIO_DATA_DIR_MASK (1 << 8)
3102# define GPIO_DATA_DIR_IN (0 << 9)
3103# define GPIO_DATA_DIR_OUT (1 << 9)
3104# define GPIO_DATA_VAL_MASK (1 << 10)
3105# define GPIO_DATA_VAL_OUT (1 << 11)
3106# define GPIO_DATA_VAL_IN (1 << 12)
3107# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3108
3109#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100)
3110#define GMBUS_AKSV_SELECT (1 << 11)
3111#define GMBUS_RATE_100KHZ (0 << 8)
3112#define GMBUS_RATE_50KHZ (1 << 8)
3113#define GMBUS_RATE_400KHZ (2 << 8)
3114#define GMBUS_RATE_1MHZ (3 << 8)
3115#define GMBUS_HOLD_EXT (1 << 7)
3116#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3117#define GMBUS_PIN_DISABLED 0
3118#define GMBUS_PIN_SSC 1
3119#define GMBUS_PIN_VGADDC 2
3120#define GMBUS_PIN_PANEL 3
3121#define GMBUS_PIN_DPD_CHV 3
3122#define GMBUS_PIN_DPC 4
3123#define GMBUS_PIN_DPB 5
3124#define GMBUS_PIN_DPD 6
3125#define GMBUS_PIN_RESERVED 7
3126#define GMBUS_PIN_1_BXT 1
3127#define GMBUS_PIN_2_BXT 2
3128#define GMBUS_PIN_3_BXT 3
3129#define GMBUS_PIN_4_CNP 4
3130#define GMBUS_PIN_9_TC1_ICP 9
3131#define GMBUS_PIN_10_TC2_ICP 10
3132#define GMBUS_PIN_11_TC3_ICP 11
3133#define GMBUS_PIN_12_TC4_ICP 12
3134
3135#define GMBUS_NUM_PINS 13
3136#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104)
3137#define GMBUS_SW_CLR_INT (1 << 31)
3138#define GMBUS_SW_RDY (1 << 30)
3139#define GMBUS_ENT (1 << 29)
3140#define GMBUS_CYCLE_NONE (0 << 25)
3141#define GMBUS_CYCLE_WAIT (1 << 25)
3142#define GMBUS_CYCLE_INDEX (2 << 25)
3143#define GMBUS_CYCLE_STOP (4 << 25)
3144#define GMBUS_BYTE_COUNT_SHIFT 16
3145#define GMBUS_BYTE_COUNT_MAX 256U
3146#define GEN9_GMBUS_BYTE_COUNT_MAX 511U
3147#define GMBUS_SLAVE_INDEX_SHIFT 8
3148#define GMBUS_SLAVE_ADDR_SHIFT 1
3149#define GMBUS_SLAVE_READ (1 << 0)
3150#define GMBUS_SLAVE_WRITE (0 << 0)
3151#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108)
3152#define GMBUS_INUSE (1 << 15)
3153#define GMBUS_HW_WAIT_PHASE (1 << 14)
3154#define GMBUS_STALL_TIMEOUT (1 << 13)
3155#define GMBUS_INT (1 << 12)
3156#define GMBUS_HW_RDY (1 << 11)
3157#define GMBUS_SATOER (1 << 10)
3158#define GMBUS_ACTIVE (1 << 9)
3159#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c)
3160#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110)
3161#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3162#define GMBUS_NAK_EN (1 << 3)
3163#define GMBUS_IDLE_EN (1 << 2)
3164#define GMBUS_HW_WAIT_EN (1 << 1)
3165#define GMBUS_HW_RDY_EN (1 << 0)
3166#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120)
3167#define GMBUS_2BYTE_INDEX_EN (1 << 31)
3168
3169
3170
3171
3172#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
3173#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
3174#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
3175#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3176
3177#define VGA0 _MMIO(0x6000)
3178#define VGA1 _MMIO(0x6004)
3179#define VGA_PD _MMIO(0x6010)
3180#define VGA0_PD_P2_DIV_4 (1 << 7)
3181#define VGA0_PD_P1_DIV_2 (1 << 5)
3182#define VGA0_PD_P1_SHIFT 0
3183#define VGA0_PD_P1_MASK (0x1f << 0)
3184#define VGA1_PD_P2_DIV_4 (1 << 15)
3185#define VGA1_PD_P1_DIV_2 (1 << 13)
3186#define VGA1_PD_P1_SHIFT 8
3187#define VGA1_PD_P1_MASK (0x1f << 8)
3188#define DPLL_VCO_ENABLE (1 << 31)
3189#define DPLL_SDVO_HIGH_SPEED (1 << 30)
3190#define DPLL_DVO_2X_MODE (1 << 30)
3191#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3192#define DPLL_SYNCLOCK_ENABLE (1 << 29)
3193#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3194#define DPLL_VGA_MODE_DIS (1 << 28)
3195#define DPLLB_MODE_DAC_SERIAL (1 << 26)
3196#define DPLLB_MODE_LVDS (2 << 26)
3197#define DPLL_MODE_MASK (3 << 26)
3198#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24)
3199#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24)
3200#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24)
3201#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24)
3202#define DPLL_P2_CLOCK_DIV_MASK 0x03000000
3203#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000
3204#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000
3205#define DPLL_LOCK_VLV (1 << 15)
3206#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
3207#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
3208#define DPLL_SSC_REF_CLK_CHV (1 << 13)
3209#define DPLL_PORTC_READY_MASK (0xf << 4)
3210#define DPLL_PORTB_READY_MASK (0xf)
3211
3212#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3213
3214
3215#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3216#define DPLL_PORTD_READY_MASK (0xf)
3217#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3218#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
3219#define PHY_LDO_DELAY_0NS 0x0
3220#define PHY_LDO_DELAY_200NS 0x1
3221#define PHY_LDO_DELAY_600NS 0x2
3222#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
3223#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3224#define PHY_CH_SU_PSR 0x1
3225#define PHY_CH_DEEP_PSR 0x7
3226#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
3227#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3228#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3229#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3230#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3231#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3232
3233
3234
3235
3236
3237#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3238#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3239#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3240
3241#define PLL_P2_DIVIDE_BY_4 (1 << 23)
3242#define PLL_P1_DIVIDE_BY_TWO (1 << 21)
3243#define PLL_REF_INPUT_DREFCLK (0 << 13)
3244#define PLL_REF_INPUT_TVCLKINA (1 << 13)
3245#define PLL_REF_INPUT_TVCLKINBC (2 << 13)
3246#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3247#define PLL_REF_INPUT_MASK (3 << 13)
3248#define PLL_LOAD_PULSE_PHASE_SHIFT 9
3249
3250# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3251# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3252# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
3253# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3254# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3255
3256
3257
3258
3259
3260
3261
3262#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3263#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3264
3265
3266
3267#define SDVO_MULTIPLIER_MASK 0x000000ff
3268#define SDVO_MULTIPLIER_SHIFT_HIRES 4
3269#define SDVO_MULTIPLIER_SHIFT_VGA 0
3270
3271#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
3272#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
3273#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
3274#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3275
3276
3277
3278
3279
3280
3281#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3282#define DPLL_MD_UDI_DIVIDER_SHIFT 24
3283
3284#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3285#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3304#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3305
3306
3307
3308
3309
3310#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3311#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3312
3313#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3314
3315#define _FPA0 0x6040
3316#define _FPA1 0x6044
3317#define _FPB0 0x6048
3318#define _FPB1 0x604c
3319#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3320#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3321#define FP_N_DIV_MASK 0x003f0000
3322#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3323#define FP_N_DIV_SHIFT 16
3324#define FP_M1_DIV_MASK 0x00003f00
3325#define FP_M1_DIV_SHIFT 8
3326#define FP_M2_DIV_MASK 0x0000003f
3327#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3328#define FP_M2_DIV_SHIFT 0
3329#define DPLL_TEST _MMIO(0x606c)
3330#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3331#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3332#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3333#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3334#define DPLLB_TEST_N_BYPASS (1 << 19)
3335#define DPLLB_TEST_M_BYPASS (1 << 18)
3336#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3337#define DPLLA_TEST_N_BYPASS (1 << 3)
3338#define DPLLA_TEST_M_BYPASS (1 << 2)
3339#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3340#define D_STATE _MMIO(0x6104)
3341#define DSTATE_GFX_RESET_I830 (1 << 6)
3342#define DSTATE_PLL_D3_OFF (1 << 3)
3343#define DSTATE_GFX_CLOCK_GATING (1 << 1)
3344#define DSTATE_DOT_CLOCK_GATING (1 << 0)
3345#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
3346# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30)
3347# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29)
3348# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
3349# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27)
3350# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26)
3351# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25)
3352# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)
3353# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24)
3354# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23)
3355# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22)
3356# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21)
3357# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20)
3358# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19)
3359# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18)
3360# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17)
3361# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16)
3362# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15)
3363# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14)
3364# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13)
3365# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12)
3366# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3367# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3368# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3369# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3370# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7)
3371# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6)
3372# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6)
3373# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3374# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3375
3376
3377
3378
3379# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3380# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3381# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3382# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0)
3383# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0)
3384
3385#define RENCLK_GATE_D1 _MMIO(0x6204)
3386# define BLITTER_CLOCK_GATE_DISABLE (1 << 13)
3387# define MPEG_CLOCK_GATE_DISABLE (1 << 12)
3388# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3389# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3390# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3391# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3392# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3393# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3394# define MAG_CLOCK_GATE_DISABLE (1 << 5)
3395
3396# define MECI_CLOCK_GATE_DISABLE (1 << 4)
3397# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3398# define MEC_CLOCK_GATE_DISABLE (1 << 2)
3399# define MECO_CLOCK_GATE_DISABLE (1 << 1)
3400
3401# define SV_CLOCK_GATE_DISABLE (1 << 0)
3402# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3403# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3404# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3405# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3406# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3407# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3408# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3409# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3410# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3411# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3412# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3413# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3414# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3415# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3416# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3417# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3418# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3419
3420# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3421
3422# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3423# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3424# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3425# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3426# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3427# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3428
3429# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3430# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3431# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3432# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3433# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3434# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3435# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3436# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3437# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3438# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3439# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3440# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3441# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3442# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3443# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3444# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3445# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3446# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3447# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3448
3449#define RENCLK_GATE_D2 _MMIO(0x6208)
3450#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3451#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3452#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3453
3454#define VDECCLK_GATE_D _MMIO(0x620C)
3455#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3456
3457#define RAMCLK_GATE_D _MMIO(0x6210)
3458#define DEUC _MMIO(0x6214)
3459
3460#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3461#define FW_CSPWRDWNEN (1 << 15)
3462
3463#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3464
3465#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3466#define CDCLK_FREQ_SHIFT 4
3467#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3468#define CZCLK_FREQ_MASK 0xf
3469
3470#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3471#define PFI_CREDIT_63 (9 << 28)
3472#define PFI_CREDIT_31 (8 << 28)
3473#define PFI_CREDIT(x) (((x) - 8) << 28)
3474#define PFI_CREDIT_RESEND (1 << 27)
3475#define VGA_FAST_MODE_DISABLE (1 << 14)
3476
3477#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3478
3479
3480
3481
3482#define PALETTE_A_OFFSET 0xa000
3483#define PALETTE_B_OFFSET 0xa800
3484#define CHV_PALETTE_C_OFFSET 0xc000
3485#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
3486 dev_priv->info.display_mmio_offset + (i) * 4)
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500#define MCHBAR_MIRROR_BASE 0x10000
3501
3502#define MCHBAR_MIRROR_BASE_SNB 0x140000
3503
3504#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3505#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3506#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3507#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3508#define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3509
3510
3511#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3512
3513
3514#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3515#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3516#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3517#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3518#define DCC_ADDRESSING_MODE_MASK (3 << 0)
3519#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3520#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3521#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3522#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3523
3524
3525#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3526#define CSHRDDR3CTL_DDR3 (1 << 2)
3527
3528
3529#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3530#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3531
3532
3533#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3534#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3535#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3536#define MAD_DIMM_ECC_MASK (0x3 << 24)
3537#define MAD_DIMM_ECC_OFF (0x0 << 24)
3538#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3539#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3540#define MAD_DIMM_ECC_ON (0x3 << 24)
3541#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3542#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3543#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20)
3544#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19)
3545#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3546#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3547#define MAD_DIMM_A_SELECT (0x1 << 16)
3548
3549#define MAD_DIMM_B_SIZE_SHIFT 8
3550#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3551#define MAD_DIMM_A_SIZE_SHIFT 0
3552#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3553
3554
3555#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3556#define MCH_SSKPD_WM0_MASK 0x3f
3557#define MCH_SSKPD_WM0_VAL 0xc
3558
3559#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3560
3561
3562#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3563#define CLKCFG_FSB_400 (5 << 0)
3564#define CLKCFG_FSB_533 (1 << 0)
3565#define CLKCFG_FSB_667 (3 << 0)
3566#define CLKCFG_FSB_800 (2 << 0)
3567#define CLKCFG_FSB_1067 (6 << 0)
3568#define CLKCFG_FSB_1067_ALT (0 << 0)
3569#define CLKCFG_FSB_1333 (7 << 0)
3570
3571
3572
3573
3574
3575#define CLKCFG_FSB_1333_ALT (4 << 0)
3576#define CLKCFG_FSB_MASK (7 << 0)
3577#define CLKCFG_MEM_533 (1 << 4)
3578#define CLKCFG_MEM_667 (2 << 4)
3579#define CLKCFG_MEM_800 (3 << 4)
3580#define CLKCFG_MEM_MASK (7 << 4)
3581
3582#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3583#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3584
3585#define TSC1 _MMIO(0x11001)
3586#define TSE (1 << 0)
3587#define TR1 _MMIO(0x11006)
3588#define TSFS _MMIO(0x11020)
3589#define TSFS_SLOPE_MASK 0x0000ff00
3590#define TSFS_SLOPE_SHIFT 8
3591#define TSFS_INTR_MASK 0x000000ff
3592
3593#define CRSTANDVID _MMIO(0x11100)
3594#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4)
3595#define PXVFREQ_PX_MASK 0x7f000000
3596#define PXVFREQ_PX_SHIFT 24
3597#define VIDFREQ_BASE _MMIO(0x11110)
3598#define VIDFREQ1 _MMIO(0x11110)
3599#define VIDFREQ2 _MMIO(0x11114)
3600#define VIDFREQ3 _MMIO(0x11118)
3601#define VIDFREQ4 _MMIO(0x1111c)
3602#define VIDFREQ_P0_MASK 0x1f000000
3603#define VIDFREQ_P0_SHIFT 24
3604#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3605#define VIDFREQ_P0_CSCLK_SHIFT 20
3606#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3607#define VIDFREQ_P0_CRCLK_SHIFT 16
3608#define VIDFREQ_P1_MASK 0x00001f00
3609#define VIDFREQ_P1_SHIFT 8
3610#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3611#define VIDFREQ_P1_CSCLK_SHIFT 4
3612#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3613#define INTTOEXT_BASE_ILK _MMIO(0x11300)
3614#define INTTOEXT_BASE _MMIO(0x11120)
3615#define INTTOEXT_MAP3_SHIFT 24
3616#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3617#define INTTOEXT_MAP2_SHIFT 16
3618#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3619#define INTTOEXT_MAP1_SHIFT 8
3620#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3621#define INTTOEXT_MAP0_SHIFT 0
3622#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
3623#define MEMSWCTL _MMIO(0x11170)
3624#define MEMCTL_CMD_MASK 0xe000
3625#define MEMCTL_CMD_SHIFT 13
3626#define MEMCTL_CMD_RCLK_OFF 0
3627#define MEMCTL_CMD_RCLK_ON 1
3628#define MEMCTL_CMD_CHFREQ 2
3629#define MEMCTL_CMD_CHVID 3
3630#define MEMCTL_CMD_VMMOFF 4
3631#define MEMCTL_CMD_VMMON 5
3632#define MEMCTL_CMD_STS (1 << 12)
3633
3634#define MEMCTL_FREQ_MASK 0x0f00
3635#define MEMCTL_FREQ_SHIFT 8
3636#define MEMCTL_SFCAVM (1 << 7)
3637#define MEMCTL_TGT_VID_MASK 0x007f
3638#define MEMIHYST _MMIO(0x1117c)
3639#define MEMINTREN _MMIO(0x11180)
3640#define MEMINT_RSEXIT_EN (1 << 8)
3641#define MEMINT_CX_SUPR_EN (1 << 7)
3642#define MEMINT_CONT_BUSY_EN (1 << 6)
3643#define MEMINT_AVG_BUSY_EN (1 << 5)
3644#define MEMINT_EVAL_CHG_EN (1 << 4)
3645#define MEMINT_MON_IDLE_EN (1 << 3)
3646#define MEMINT_UP_EVAL_EN (1 << 2)
3647#define MEMINT_DOWN_EVAL_EN (1 << 1)
3648#define MEMINT_SW_CMD_EN (1 << 0)
3649#define MEMINTRSTR _MMIO(0x11182)
3650#define MEM_RSEXIT_MASK 0xc000
3651#define MEM_RSEXIT_SHIFT 14
3652#define MEM_CONT_BUSY_MASK 0x3000
3653#define MEM_CONT_BUSY_SHIFT 12
3654#define MEM_AVG_BUSY_MASK 0x0c00
3655#define MEM_AVG_BUSY_SHIFT 10
3656#define MEM_EVAL_CHG_MASK 0x0300
3657#define MEM_EVAL_BUSY_SHIFT 8
3658#define MEM_MON_IDLE_MASK 0x00c0
3659#define MEM_MON_IDLE_SHIFT 6
3660#define MEM_UP_EVAL_MASK 0x0030
3661#define MEM_UP_EVAL_SHIFT 4
3662#define MEM_DOWN_EVAL_MASK 0x000c
3663#define MEM_DOWN_EVAL_SHIFT 2
3664#define MEM_SW_CMD_MASK 0x0003
3665#define MEM_INT_STEER_GFX 0
3666#define MEM_INT_STEER_CMR 1
3667#define MEM_INT_STEER_SMI 2
3668#define MEM_INT_STEER_SCI 3
3669#define MEMINTRSTS _MMIO(0x11184)
3670#define MEMINT_RSEXIT (1 << 7)
3671#define MEMINT_CONT_BUSY (1 << 6)
3672#define MEMINT_AVG_BUSY (1 << 5)
3673#define MEMINT_EVAL_CHG (1 << 4)
3674#define MEMINT_MON_IDLE (1 << 3)
3675#define MEMINT_UP_EVAL (1 << 2)
3676#define MEMINT_DOWN_EVAL (1 << 1)
3677#define MEMINT_SW_CMD (1 << 0)
3678#define MEMMODECTL _MMIO(0x11190)
3679#define MEMMODE_BOOST_EN (1 << 31)
3680#define MEMMODE_BOOST_FREQ_MASK 0x0f000000
3681#define MEMMODE_BOOST_FREQ_SHIFT 24
3682#define MEMMODE_IDLE_MODE_MASK 0x00030000
3683#define MEMMODE_IDLE_MODE_SHIFT 16
3684#define MEMMODE_IDLE_MODE_EVAL 0
3685#define MEMMODE_IDLE_MODE_CONT 1
3686#define MEMMODE_HWIDLE_EN (1 << 15)
3687#define MEMMODE_SWMODE_EN (1 << 14)
3688#define MEMMODE_RCLK_GATE (1 << 13)
3689#define MEMMODE_HW_UPDATE (1 << 12)
3690#define MEMMODE_FSTART_MASK 0x00000f00
3691#define MEMMODE_FSTART_SHIFT 8
3692#define MEMMODE_FMAX_MASK 0x000000f0
3693#define MEMMODE_FMAX_SHIFT 4
3694#define MEMMODE_FMIN_MASK 0x0000000f
3695#define RCBMAXAVG _MMIO(0x1119c)
3696#define MEMSWCTL2 _MMIO(0x1119e)
3697#define SWMEMCMD_RENDER_OFF (0 << 13)
3698#define SWMEMCMD_RENDER_ON (1 << 13)
3699#define SWMEMCMD_SWFREQ (2 << 13)
3700#define SWMEMCMD_TARVID (3 << 13)
3701#define SWMEMCMD_VRM_OFF (4 << 13)
3702#define SWMEMCMD_VRM_ON (5 << 13)
3703#define CMDSTS (1 << 12)
3704#define SFCAVM (1 << 11)
3705#define SWFREQ_MASK 0x0380
3706#define SWFREQ_SHIFT 7
3707#define TARVID_MASK 0x001f
3708#define MEMSTAT_CTG _MMIO(0x111a0)
3709#define RCBMINAVG _MMIO(0x111a0)
3710#define RCUPEI _MMIO(0x111b0)
3711#define RCDNEI _MMIO(0x111b4)
3712#define RSTDBYCTL _MMIO(0x111b8)
3713#define RS1EN (1 << 31)
3714#define RS2EN (1 << 30)
3715#define RS3EN (1 << 29)
3716#define D3RS3EN (1 << 28)
3717#define SWPROMORSX (1 << 27)
3718#define RCWAKERW (1 << 26)
3719#define DPRSLPVREN (1 << 25)
3720#define GFXTGHYST (1 << 24)
3721#define RCX_SW_EXIT (1 << 23)
3722#define RSX_STATUS_MASK (7 << 20)
3723#define RSX_STATUS_ON (0 << 20)
3724#define RSX_STATUS_RC1 (1 << 20)
3725#define RSX_STATUS_RC1E (2 << 20)
3726#define RSX_STATUS_RS1 (3 << 20)
3727#define RSX_STATUS_RS2 (4 << 20)
3728#define RSX_STATUS_RSVD (5 << 20)
3729#define RSX_STATUS_RS3 (6 << 20)
3730#define RSX_STATUS_RSVD2 (7 << 20)
3731#define UWRCRSXE (1 << 19)
3732#define RSCRP (1 << 18)
3733#define JRSC (1 << 17)
3734#define RS2INC0 (1 << 16)
3735#define RS1CONTSAV_MASK (3 << 14)
3736#define RS1CONTSAV_NO_RS1 (0 << 14)
3737#define RS1CONTSAV_RSVD (1 << 14)
3738#define RS1CONTSAV_SAVE_RS1 (2 << 14)
3739#define RS1CONTSAV_FULL_RS1 (3 << 14)
3740#define NORMSLEXLAT_MASK (3 << 12)
3741#define SLOW_RS123 (0 << 12)
3742#define SLOW_RS23 (1 << 12)
3743#define SLOW_RS3 (2 << 12)
3744#define NORMAL_RS123 (3 << 12)
3745#define RCMODE_TIMEOUT (1 << 11)
3746#define IMPROMOEN (1 << 10)
3747#define RCENTSYNC (1 << 9)
3748#define STATELOCK (1 << 7)
3749#define RS_CSTATE_MASK (3 << 4)
3750#define RS_CSTATE_C367_RS1 (0 << 4)
3751#define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3752#define RS_CSTATE_RSVD (2 << 4)
3753#define RS_CSTATE_C367_RS2 (3 << 4)
3754#define REDSAVES (1 << 3)
3755#define REDRESTORES (1 << 2)
3756#define VIDCTL _MMIO(0x111c0)
3757#define VIDSTS _MMIO(0x111c8)
3758#define VIDSTART _MMIO(0x111cc)
3759#define MEMSTAT_ILK _MMIO(0x111f8)
3760#define MEMSTAT_VID_MASK 0x7f00
3761#define MEMSTAT_VID_SHIFT 8
3762#define MEMSTAT_PSTATE_MASK 0x00f8
3763#define MEMSTAT_PSTATE_SHIFT 3
3764#define MEMSTAT_MON_ACTV (1 << 2)
3765#define MEMSTAT_SRC_CTL_MASK 0x0003
3766#define MEMSTAT_SRC_CTL_CORE 0
3767#define MEMSTAT_SRC_CTL_TRB 1
3768#define MEMSTAT_SRC_CTL_THM 2
3769#define MEMSTAT_SRC_CTL_STDBY 3
3770#define RCPREVBSYTUPAVG _MMIO(0x113b8)
3771#define RCPREVBSYTDNAVG _MMIO(0x113bc)
3772#define PMMISC _MMIO(0x11214)
3773#define MCPPCE_EN (1 << 0)
3774#define SDEW _MMIO(0x1124c)
3775#define CSIEW0 _MMIO(0x11250)
3776#define CSIEW1 _MMIO(0x11254)
3777#define CSIEW2 _MMIO(0x11258)
3778#define PEW(i) _MMIO(0x1125c + (i) * 4)
3779#define DEW(i) _MMIO(0x11270 + (i) * 4)
3780#define MCHAFE _MMIO(0x112c0)
3781#define CSIEC _MMIO(0x112e0)
3782#define DMIEC _MMIO(0x112e4)
3783#define DDREC _MMIO(0x112e8)
3784#define PEG0EC _MMIO(0x112ec)
3785#define PEG1EC _MMIO(0x112f0)
3786#define GFXEC _MMIO(0x112f4)
3787#define RPPREVBSYTUPAVG _MMIO(0x113b8)
3788#define RPPREVBSYTDNAVG _MMIO(0x113bc)
3789#define ECR _MMIO(0x11600)
3790#define ECR_GPFE (1 << 31)
3791#define ECR_IMONE (1 << 30)
3792#define ECR_CAP_MASK 0x0000001f
3793#define OGW0 _MMIO(0x11608)
3794#define OGW1 _MMIO(0x1160c)
3795#define EG0 _MMIO(0x11610)
3796#define EG1 _MMIO(0x11614)
3797#define EG2 _MMIO(0x11618)
3798#define EG3 _MMIO(0x1161c)
3799#define EG4 _MMIO(0x11620)
3800#define EG5 _MMIO(0x11624)
3801#define EG6 _MMIO(0x11628)
3802#define EG7 _MMIO(0x1162c)
3803#define PXW(i) _MMIO(0x11664 + (i) * 4)
3804#define PXWL(i) _MMIO(0x11680 + (i) * 8)
3805#define LCFUSE02 _MMIO(0x116c0)
3806#define LCFUSE_HIV_MASK 0x000000ff
3807#define CSIPLL0 _MMIO(0x12c10)
3808#define DDRMPLL1 _MMIO(0X12c20)
3809#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
3810
3811#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3812#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3813
3814#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3815#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3816#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3817#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3818#define BXT_RP_STATE_CAP _MMIO(0x138170)
3819
3820
3821
3822
3823
3824
3825
3826
3827#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
3828#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
3829#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
3830#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3831 (IS_GEN9_LP(dev_priv) ? \
3832 INTERVAL_0_833_US(us) : \
3833 INTERVAL_1_33_US(us)) : \
3834 INTERVAL_1_28_US(us))
3835
3836#define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3837#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3838#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3839#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3840 (IS_GEN9_LP(dev_priv) ? \
3841 INTERVAL_0_833_TO_US(interval) : \
3842 INTERVAL_1_33_TO_US(interval)) : \
3843 INTERVAL_1_28_TO_US(interval))
3844
3845
3846
3847
3848#define CCID _MMIO(0x2180)
3849#define CCID_EN BIT(0)
3850#define CCID_EXTENDED_STATE_RESTORE BIT(2)
3851#define CCID_EXTENDED_STATE_SAVE BIT(3)
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865#define CXT_SIZE _MMIO(0x21a0)
3866#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3867#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3868#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3869#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3870#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
3871#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
3872 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3873 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3874#define GEN7_CXT_SIZE _MMIO(0x21a8)
3875#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3876#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3877#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3878#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3879#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3880#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
3881#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3882 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3883
3884enum {
3885 INTEL_ADVANCED_CONTEXT = 0,
3886 INTEL_LEGACY_32B_CONTEXT,
3887 INTEL_ADVANCED_AD_CONTEXT,
3888 INTEL_LEGACY_64B_CONTEXT
3889};
3890
3891enum {
3892 FAULT_AND_HANG = 0,
3893 FAULT_AND_HALT,
3894 FAULT_AND_STREAM,
3895 FAULT_AND_CONTINUE
3896};
3897
3898#define GEN8_CTX_VALID (1 << 0)
3899#define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
3900#define GEN8_CTX_FORCE_RESTORE (1 << 2)
3901#define GEN8_CTX_L3LLC_COHERENT (1 << 5)
3902#define GEN8_CTX_PRIVILEGE (1 << 8)
3903#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3904
3905#define GEN8_CTX_ID_SHIFT 32
3906#define GEN8_CTX_ID_WIDTH 21
3907#define GEN11_SW_CTX_ID_SHIFT 37
3908#define GEN11_SW_CTX_ID_WIDTH 11
3909#define GEN11_ENGINE_CLASS_SHIFT 61
3910#define GEN11_ENGINE_CLASS_WIDTH 3
3911#define GEN11_ENGINE_INSTANCE_SHIFT 48
3912#define GEN11_ENGINE_INSTANCE_WIDTH 6
3913
3914#define CHV_CLK_CTL1 _MMIO(0x101100)
3915#define VLV_CLK_CTL2 _MMIO(0x101104)
3916#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
3917
3918
3919
3920
3921
3922#define OVADD _MMIO(0x30000)
3923#define DOVSTA _MMIO(0x30008)
3924#define OC_BUF (0x3 << 20)
3925#define OGAMC5 _MMIO(0x30010)
3926#define OGAMC4 _MMIO(0x30014)
3927#define OGAMC3 _MMIO(0x30018)
3928#define OGAMC2 _MMIO(0x3001c)
3929#define OGAMC1 _MMIO(0x30020)
3930#define OGAMC0 _MMIO(0x30024)
3931
3932
3933
3934
3935#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
3936#define DARBF_GATING_DIS (1 << 27)
3937#define PWM2_GATING_DIS (1 << 14)
3938#define PWM1_GATING_DIS (1 << 13)
3939
3940#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
3941#define BXT_GMBUS_GATING_DIS (1 << 14)
3942
3943#define _CLKGATE_DIS_PSL_A 0x46520
3944#define _CLKGATE_DIS_PSL_B 0x46524
3945#define _CLKGATE_DIS_PSL_C 0x46528
3946#define DUPS1_GATING_DIS (1 << 15)
3947#define DUPS2_GATING_DIS (1 << 19)
3948#define DUPS3_GATING_DIS (1 << 23)
3949#define DPF_GATING_DIS (1 << 10)
3950#define DPF_RAM_GATING_DIS (1 << 9)
3951#define DPFR_GATING_DIS (1 << 8)
3952
3953#define CLKGATE_DIS_PSL(pipe) \
3954 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
3955
3956
3957
3958
3959#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
3960#define SARBUNIT_CLKGATE_DIS (1 << 5)
3961#define RCCUNIT_CLKGATE_DIS (1 << 7)
3962#define MSCUNIT_CLKGATE_DIS (1 << 10)
3963
3964#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
3965#define GWUNIT_CLKGATE_DIS (1 << 16)
3966
3967#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
3968#define VFUNIT_CLKGATE_DIS (1 << 20)
3969
3970#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
3971#define CGPSF_CLKGATE_DIS (1 << 3)
3972
3973
3974
3975
3976
3977
3978#define _PIPE_CRC_CTL_A 0x60050
3979#define PIPE_CRC_ENABLE (1 << 31)
3980
3981#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3982#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3983#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
3984
3985#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3986#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3987#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
3988
3989#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
3990#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28)
3991
3992#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
3993#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
3994#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
3995
3996#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
3997#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
3998#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
3999
4000#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
4001#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
4002#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
4003
4004#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
4005#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
4006#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
4007#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
4008#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
4009
4010#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
4011
4012#define _PIPE_CRC_RES_1_A_IVB 0x60064
4013#define _PIPE_CRC_RES_2_A_IVB 0x60068
4014#define _PIPE_CRC_RES_3_A_IVB 0x6006c
4015#define _PIPE_CRC_RES_4_A_IVB 0x60070
4016#define _PIPE_CRC_RES_5_A_IVB 0x60074
4017
4018#define _PIPE_CRC_RES_RED_A 0x60060
4019#define _PIPE_CRC_RES_GREEN_A 0x60064
4020#define _PIPE_CRC_RES_BLUE_A 0x60068
4021#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4022#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
4023
4024
4025#define _PIPE_CRC_RES_1_B_IVB 0x61064
4026#define _PIPE_CRC_RES_2_B_IVB 0x61068
4027#define _PIPE_CRC_RES_3_B_IVB 0x6106c
4028#define _PIPE_CRC_RES_4_B_IVB 0x61070
4029#define _PIPE_CRC_RES_5_B_IVB 0x61074
4030
4031#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4032#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4033#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4034#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4035#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4036#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4037
4038#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4039#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4040#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4041#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4042#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4043
4044
4045#define _HTOTAL_A 0x60000
4046#define _HBLANK_A 0x60004
4047#define _HSYNC_A 0x60008
4048#define _VTOTAL_A 0x6000c
4049#define _VBLANK_A 0x60010
4050#define _VSYNC_A 0x60014
4051#define _PIPEASRC 0x6001c
4052#define _BCLRPAT_A 0x60020
4053#define _VSYNCSHIFT_A 0x60028
4054#define _PIPE_MULT_A 0x6002c
4055
4056
4057#define _HTOTAL_B 0x61000
4058#define _HBLANK_B 0x61004
4059#define _HSYNC_B 0x61008
4060#define _VTOTAL_B 0x6100c
4061#define _VBLANK_B 0x61010
4062#define _VSYNC_B 0x61014
4063#define _PIPEBSRC 0x6101c
4064#define _BCLRPAT_B 0x61020
4065#define _VSYNCSHIFT_B 0x61028
4066#define _PIPE_MULT_B 0x6102c
4067
4068#define TRANSCODER_A_OFFSET 0x60000
4069#define TRANSCODER_B_OFFSET 0x61000
4070#define TRANSCODER_C_OFFSET 0x62000
4071#define CHV_TRANSCODER_C_OFFSET 0x63000
4072#define TRANSCODER_EDP_OFFSET 0x6f000
4073
4074#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
4075 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
4076 dev_priv->info.display_mmio_offset)
4077
4078#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4079#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4080#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4081#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4082#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4083#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4084#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4085#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4086#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4087#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4088
4089
4090#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
4091#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
4092#define VLV_EDP_PSR_ENABLE (1 << 0)
4093#define VLV_EDP_PSR_RESET (1 << 1)
4094#define VLV_EDP_PSR_MODE_MASK (7 << 2)
4095#define VLV_EDP_PSR_MODE_HW_TIMER (1 << 3)
4096#define VLV_EDP_PSR_MODE_SW_TIMER (1 << 2)
4097#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1 << 7)
4098#define VLV_EDP_PSR_ACTIVE_ENTRY (1 << 8)
4099#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1 << 9)
4100#define VLV_EDP_PSR_DBL_FRAME (1 << 10)
4101#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff << 16)
4102#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
4103#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
4104
4105#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
4106#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
4107#define VLV_EDP_PSR_SDP_FREQ_MASK (3 << 30)
4108#define VLV_EDP_PSR_SDP_FREQ_ONCE (1 << 31)
4109#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1 << 30)
4110#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
4111
4112#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
4113#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
4114#define VLV_EDP_PSR_LAST_STATE_MASK (7 << 3)
4115#define VLV_EDP_PSR_CURR_STATE_MASK 7
4116#define VLV_EDP_PSR_DISABLED (0 << 0)
4117#define VLV_EDP_PSR_INACTIVE (1 << 0)
4118#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2 << 0)
4119#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3 << 0)
4120#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4 << 0)
4121#define VLV_EDP_PSR_EXIT (5 << 0)
4122#define VLV_EDP_PSR_IN_TRANS (1 << 7)
4123#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
4124
4125
4126#define HSW_EDP_PSR_BASE 0x64800
4127#define BDW_EDP_PSR_BASE 0x6f800
4128#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
4129#define EDP_PSR_ENABLE (1 << 31)
4130#define BDW_PSR_SINGLE_FRAME (1 << 30)
4131#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29)
4132#define EDP_PSR_LINK_STANDBY (1 << 27)
4133#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
4134#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
4135#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
4136#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
4137#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
4138#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4139#define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
4140#define EDP_PSR_TP1_TP2_SEL (0 << 11)
4141#define EDP_PSR_TP1_TP3_SEL (1 << 11)
4142#define EDP_PSR_CRC_ENABLE (1 << 10)
4143#define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
4144#define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
4145#define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
4146#define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
4147#define EDP_PSR_TP1_TIME_500us (0 << 4)
4148#define EDP_PSR_TP1_TIME_100us (1 << 4)
4149#define EDP_PSR_TP1_TIME_2500us (2 << 4)
4150#define EDP_PSR_TP1_TIME_0us (3 << 4)
4151#define EDP_PSR_IDLE_FRAME_SHIFT 0
4152
4153
4154#define EDP_PSR_IMR _MMIO(0x64834)
4155#define EDP_PSR_IIR _MMIO(0x64838)
4156#define EDP_PSR_ERROR(trans) (1 << (((trans) * 8 + 10) & 31))
4157#define EDP_PSR_POST_EXIT(trans) (1 << (((trans) * 8 + 9) & 31))
4158#define EDP_PSR_PRE_ENTRY(trans) (1 << (((trans) * 8 + 8) & 31))
4159
4160#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4161#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
4162#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4163#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
4164#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
4165#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4166
4167#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4)
4168
4169#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
4170#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
4171#define EDP_PSR_STATUS_STATE_SHIFT 29
4172#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
4173#define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
4174#define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
4175#define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
4176#define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
4177#define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
4178#define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
4179#define EDP_PSR_STATUS_LINK_MASK (3 << 26)
4180#define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
4181#define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
4182#define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
4183#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4184#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4185#define EDP_PSR_STATUS_COUNT_SHIFT 16
4186#define EDP_PSR_STATUS_COUNT_MASK 0xf
4187#define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
4188#define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
4189#define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
4190#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
4191#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
4192#define EDP_PSR_STATUS_IDLE_MASK 0xf
4193
4194#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
4195#define EDP_PSR_PERF_CNT_MASK 0xffffff
4196
4197#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60)
4198#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
4199#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4200#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4201#define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
4202#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16)
4203#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15)
4204
4205#define EDP_PSR2_CTL _MMIO(0x6f900)
4206#define EDP_PSR2_ENABLE (1 << 31)
4207#define EDP_SU_TRACK_ENABLE (1 << 30)
4208#define EDP_Y_COORDINATE_VALID (1 << 26)
4209#define EDP_Y_COORDINATE_ENABLE (1 << 25)
4210#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
4211#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
4212#define EDP_PSR2_TP2_TIME_500us (0 << 8)
4213#define EDP_PSR2_TP2_TIME_100us (1 << 8)
4214#define EDP_PSR2_TP2_TIME_2500us (2 << 8)
4215#define EDP_PSR2_TP2_TIME_50us (3 << 8)
4216#define EDP_PSR2_TP2_TIME_MASK (3 << 8)
4217#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4218#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4219#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
4220#define EDP_PSR2_IDLE_FRAME_MASK 0xf
4221#define EDP_PSR2_IDLE_FRAME_SHIFT 0
4222
4223#define _PSR_EVENT_TRANS_A 0x60848
4224#define _PSR_EVENT_TRANS_B 0x61848
4225#define _PSR_EVENT_TRANS_C 0x62848
4226#define _PSR_EVENT_TRANS_D 0x63848
4227#define _PSR_EVENT_TRANS_EDP 0x6F848
4228#define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
4229#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
4230#define PSR_EVENT_PSR2_DISABLED (1 << 16)
4231#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
4232#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
4233#define PSR_EVENT_GRAPHICS_RESET (1 << 12)
4234#define PSR_EVENT_PCH_INTERRUPT (1 << 11)
4235#define PSR_EVENT_MEMORY_UP (1 << 10)
4236#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4237#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4238#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
4239#define PSR_EVENT_REGISTER_UPDATE (1 << 5)
4240#define PSR_EVENT_HDCP_ENABLE (1 << 4)
4241#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4242#define PSR_EVENT_VBI_ENABLE (1 << 2)
4243#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
4244#define PSR_EVENT_PSR_DISABLE (1 << 0)
4245
4246#define EDP_PSR2_STATUS _MMIO(0x6f940)
4247#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
4248#define EDP_PSR2_STATUS_STATE_SHIFT 28
4249
4250
4251#define ADPA _MMIO(0x61100)
4252#define PCH_ADPA _MMIO(0xe1100)
4253#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4254
4255#define ADPA_DAC_ENABLE (1 << 31)
4256#define ADPA_DAC_DISABLE 0
4257#define ADPA_PIPE_SEL_SHIFT 30
4258#define ADPA_PIPE_SEL_MASK (1 << 30)
4259#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
4260#define ADPA_PIPE_SEL_SHIFT_CPT 29
4261#define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
4262#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4263#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000
4264#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
4265#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
4266#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4267#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
4268#define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
4269#define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
4270#define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
4271#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
4272#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
4273#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
4274#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
4275#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
4276#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
4277#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
4278#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
4279#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
4280#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
4281#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4282#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
4283#define ADPA_SETS_HVPOLARITY 0
4284#define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4285#define ADPA_VSYNC_CNTL_ENABLE 0
4286#define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4287#define ADPA_HSYNC_CNTL_ENABLE 0
4288#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4289#define ADPA_VSYNC_ACTIVE_LOW 0
4290#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4291#define ADPA_HSYNC_ACTIVE_LOW 0
4292#define ADPA_DPMS_MASK (~(3 << 10))
4293#define ADPA_DPMS_ON (0 << 10)
4294#define ADPA_DPMS_SUSPEND (1 << 10)
4295#define ADPA_DPMS_STANDBY (2 << 10)
4296#define ADPA_DPMS_OFF (3 << 10)
4297
4298
4299
4300#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
4301#define PORTB_HOTPLUG_INT_EN (1 << 29)
4302#define PORTC_HOTPLUG_INT_EN (1 << 28)
4303#define PORTD_HOTPLUG_INT_EN (1 << 27)
4304#define SDVOB_HOTPLUG_INT_EN (1 << 26)
4305#define SDVOC_HOTPLUG_INT_EN (1 << 25)
4306#define TV_HOTPLUG_INT_EN (1 << 18)
4307#define CRT_HOTPLUG_INT_EN (1 << 9)
4308#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4309 PORTC_HOTPLUG_INT_EN | \
4310 PORTD_HOTPLUG_INT_EN | \
4311 SDVOC_HOTPLUG_INT_EN | \
4312 SDVOB_HOTPLUG_INT_EN | \
4313 CRT_HOTPLUG_INT_EN)
4314#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
4315#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4316
4317#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4318#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4319#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4320#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4321#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4322#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4323#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4324#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4325#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4326#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4327#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4328#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4329
4330#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
4331
4332
4333
4334
4335
4336
4337
4338
4339#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4340#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4341#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4342
4343#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
4344#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
4345#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
4346#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
4347#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4348#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
4349#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
4350#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4351#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
4352#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
4353#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4354#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
4355
4356#define CRT_HOTPLUG_INT_STATUS (1 << 11)
4357#define TV_HOTPLUG_INT_STATUS (1 << 10)
4358#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4359#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4360#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4361#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4362#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4363#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4364#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
4365#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4366
4367
4368#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4369#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4370
4371
4372
4373
4374
4375
4376#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4377#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4378#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4379#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
4380#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4381 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4382 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4383 PORTB_HOTPLUG_INT_STATUS | \
4384 PORTC_HOTPLUG_INT_STATUS | \
4385 PORTD_HOTPLUG_INT_STATUS)
4386
4387#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4388 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4389 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4390 PORTB_HOTPLUG_INT_STATUS | \
4391 PORTC_HOTPLUG_INT_STATUS | \
4392 PORTD_HOTPLUG_INT_STATUS)
4393
4394
4395
4396#define _GEN3_SDVOB 0x61140
4397#define _GEN3_SDVOC 0x61160
4398#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4399#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
4400#define GEN4_HDMIB GEN3_SDVOB
4401#define GEN4_HDMIC GEN3_SDVOC
4402#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4403#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4404#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4405#define PCH_SDVOB _MMIO(0xe1140)
4406#define PCH_HDMIB PCH_SDVOB
4407#define PCH_HDMIC _MMIO(0xe1150)
4408#define PCH_HDMID _MMIO(0xe1160)
4409
4410#define PORT_DFT_I9XX _MMIO(0x61150)
4411#define DC_BALANCE_RESET (1 << 25)
4412#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
4413#define DC_BALANCE_RESET_VLV (1 << 31)
4414#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4415#define PIPE_C_SCRAMBLE_RESET (1 << 14)
4416#define PIPE_B_SCRAMBLE_RESET (1 << 1)
4417#define PIPE_A_SCRAMBLE_RESET (1 << 0)
4418
4419
4420#define SDVO_ENABLE (1 << 31)
4421#define SDVO_PIPE_SEL_SHIFT 30
4422#define SDVO_PIPE_SEL_MASK (1 << 30)
4423#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4424#define SDVO_STALL_SELECT (1 << 29)
4425#define SDVO_INTERRUPT_ENABLE (1 << 26)
4426
4427
4428
4429
4430
4431#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
4432#define SDVO_PORT_MULTIPLY_SHIFT 23
4433#define SDVO_PHASE_SELECT_MASK (15 << 19)
4434#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4435#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4436#define SDVOC_GANG_MODE (1 << 16)
4437#define SDVO_BORDER_ENABLE (1 << 7)
4438#define SDVOB_PCIE_CONCURRENCY (1 << 3)
4439#define SDVO_DETECTED (1 << 2)
4440
4441#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4442 SDVO_INTERRUPT_ENABLE)
4443#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4444
4445
4446#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
4447#define SDVO_COLOR_FORMAT_MASK (7 << 26)
4448#define SDVO_ENCODING_SDVO (0 << 10)
4449#define SDVO_ENCODING_HDMI (2 << 10)
4450#define HDMI_MODE_SELECT_HDMI (1 << 9)
4451#define HDMI_MODE_SELECT_DVI (0 << 9)
4452#define HDMI_COLOR_RANGE_16_235 (1 << 8)
4453#define SDVO_AUDIO_ENABLE (1 << 6)
4454
4455#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4456#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4457
4458
4459#define HDMI_COLOR_FORMAT_12bpc (3 << 26)
4460#define SDVOB_HOTPLUG_ENABLE (1 << 23)
4461
4462
4463#define SDVO_PIPE_SEL_SHIFT_CPT 29
4464#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
4465#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4466
4467
4468#define SDVO_PIPE_SEL_SHIFT_CHV 24
4469#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4470#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4471
4472
4473
4474#define _DVOA 0x61120
4475#define DVOA _MMIO(_DVOA)
4476#define _DVOB 0x61140
4477#define DVOB _MMIO(_DVOB)
4478#define _DVOC 0x61160
4479#define DVOC _MMIO(_DVOC)
4480#define DVO_ENABLE (1 << 31)
4481#define DVO_PIPE_SEL_SHIFT 30
4482#define DVO_PIPE_SEL_MASK (1 << 30)
4483#define DVO_PIPE_SEL(pipe) ((pipe) << 30)
4484#define DVO_PIPE_STALL_UNUSED (0 << 28)
4485#define DVO_PIPE_STALL (1 << 28)
4486#define DVO_PIPE_STALL_TV (2 << 28)
4487#define DVO_PIPE_STALL_MASK (3 << 28)
4488#define DVO_USE_VGA_SYNC (1 << 15)
4489#define DVO_DATA_ORDER_I740 (0 << 14)
4490#define DVO_DATA_ORDER_FP (1 << 14)
4491#define DVO_VSYNC_DISABLE (1 << 11)
4492#define DVO_HSYNC_DISABLE (1 << 10)
4493#define DVO_VSYNC_TRISTATE (1 << 9)
4494#define DVO_HSYNC_TRISTATE (1 << 8)
4495#define DVO_BORDER_ENABLE (1 << 7)
4496#define DVO_DATA_ORDER_GBRG (1 << 6)
4497#define DVO_DATA_ORDER_RGGB (0 << 6)
4498#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4499#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4500#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4501#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4502#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4503#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1)
4504#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0)
4505#define DVO_PRESERVE_MASK (0x7 << 24)
4506#define DVOA_SRCDIM _MMIO(0x61124)
4507#define DVOB_SRCDIM _MMIO(0x61144)
4508#define DVOC_SRCDIM _MMIO(0x61164)
4509#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4510#define DVO_SRCDIM_VERTICAL_SHIFT 0
4511
4512
4513#define LVDS _MMIO(0x61180)
4514
4515
4516
4517
4518#define LVDS_PORT_EN (1 << 31)
4519
4520#define LVDS_PIPE_SEL_SHIFT 30
4521#define LVDS_PIPE_SEL_MASK (1 << 30)
4522#define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
4523#define LVDS_PIPE_SEL_SHIFT_CPT 29
4524#define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
4525#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4526
4527#define LVDS_ENABLE_DITHER (1 << 25)
4528
4529#define LVDS_VSYNC_POLARITY (1 << 21)
4530#define LVDS_HSYNC_POLARITY (1 << 20)
4531
4532
4533#define LVDS_BORDER_ENABLE (1 << 15)
4534
4535
4536
4537
4538#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
4539#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
4540#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
4541
4542
4543
4544
4545
4546#define LVDS_A3_POWER_MASK (3 << 6)
4547#define LVDS_A3_POWER_DOWN (0 << 6)
4548#define LVDS_A3_POWER_UP (3 << 6)
4549
4550
4551
4552
4553#define LVDS_CLKB_POWER_MASK (3 << 4)
4554#define LVDS_CLKB_POWER_DOWN (0 << 4)
4555#define LVDS_CLKB_POWER_UP (3 << 4)
4556
4557
4558
4559
4560
4561#define LVDS_B0B3_POWER_MASK (3 << 2)
4562#define LVDS_B0B3_POWER_DOWN (0 << 2)
4563#define LVDS_B0B3_POWER_UP (3 << 2)
4564
4565
4566#define VIDEO_DIP_DATA _MMIO(0x61178)
4567
4568
4569
4570#define VIDEO_DIP_DATA_SIZE 32
4571#define VIDEO_DIP_VSC_DATA_SIZE 36
4572#define VIDEO_DIP_CTL _MMIO(0x61170)
4573
4574#define VIDEO_DIP_ENABLE (1 << 31)
4575#define VIDEO_DIP_PORT(port) ((port) << 29)
4576#define VIDEO_DIP_PORT_MASK (3 << 29)
4577#define VIDEO_DIP_ENABLE_GCP (1 << 25)
4578#define VIDEO_DIP_ENABLE_AVI (1 << 21)
4579#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
4580#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
4581#define VIDEO_DIP_ENABLE_SPD (8 << 21)
4582#define VIDEO_DIP_SELECT_AVI (0 << 19)
4583#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
4584#define VIDEO_DIP_SELECT_SPD (3 << 19)
4585#define VIDEO_DIP_SELECT_MASK (3 << 19)
4586#define VIDEO_DIP_FREQ_ONCE (0 << 16)
4587#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
4588#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4589#define VIDEO_DIP_FREQ_MASK (3 << 16)
4590
4591#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4592#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4593#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
4594#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4595#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4596#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4597
4598#define DRM_DIP_ENABLE (1 << 28)
4599#define PSR_VSC_BIT_7_SET (1 << 27)
4600#define VSC_SELECT_MASK (0x3 << 25)
4601#define VSC_SELECT_SHIFT 25
4602#define VSC_DIP_HW_HEA_DATA (0 << 25)
4603#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
4604#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
4605#define VSC_DIP_SW_HEA_DATA (3 << 25)
4606#define VDIP_ENABLE_PPS (1 << 24)
4607
4608
4609#define PPS_BASE 0x61200
4610#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
4611#define PCH_PPS_BASE 0xC7200
4612
4613#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4614 PPS_BASE + (reg) + \
4615 (pps_idx) * 0x100)
4616
4617#define _PP_STATUS 0x61200
4618#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4619#define PP_ON (1 << 31)
4620
4621
4622
4623
4624
4625
4626
4627#define PP_READY (1 << 30)
4628#define PP_SEQUENCE_NONE (0 << 28)
4629#define PP_SEQUENCE_POWER_UP (1 << 28)
4630#define PP_SEQUENCE_POWER_DOWN (2 << 28)
4631#define PP_SEQUENCE_MASK (3 << 28)
4632#define PP_SEQUENCE_SHIFT 28
4633#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
4634#define PP_SEQUENCE_STATE_MASK 0x0000000f
4635#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
4636#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
4637#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
4638#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
4639#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
4640#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
4641#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
4642#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
4643#define PP_SEQUENCE_STATE_RESET (0xf << 0)
4644
4645#define _PP_CONTROL 0x61204
4646#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4647#define PANEL_UNLOCK_REGS (0xabcd << 16)
4648#define PANEL_UNLOCK_MASK (0xffff << 16)
4649#define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
4650#define BXT_POWER_CYCLE_DELAY_SHIFT 4
4651#define EDP_FORCE_VDD (1 << 3)
4652#define EDP_BLC_ENABLE (1 << 2)
4653#define PANEL_POWER_RESET (1 << 1)
4654#define PANEL_POWER_OFF (0 << 0)
4655#define PANEL_POWER_ON (1 << 0)
4656
4657#define _PP_ON_DELAYS 0x61208
4658#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4659#define PANEL_PORT_SELECT_SHIFT 30
4660#define PANEL_PORT_SELECT_MASK (3 << 30)
4661#define PANEL_PORT_SELECT_LVDS (0 << 30)
4662#define PANEL_PORT_SELECT_DPA (1 << 30)
4663#define PANEL_PORT_SELECT_DPC (2 << 30)
4664#define PANEL_PORT_SELECT_DPD (3 << 30)
4665#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
4666#define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
4667#define PANEL_POWER_UP_DELAY_SHIFT 16
4668#define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
4669#define PANEL_LIGHT_ON_DELAY_SHIFT 0
4670
4671#define _PP_OFF_DELAYS 0x6120C
4672#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4673#define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
4674#define PANEL_POWER_DOWN_DELAY_SHIFT 16
4675#define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
4676#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4677
4678#define _PP_DIVISOR 0x61210
4679#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4680#define PP_REFERENCE_DIVIDER_MASK 0xffffff00
4681#define PP_REFERENCE_DIVIDER_SHIFT 8
4682#define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
4683#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4684
4685
4686#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
4687#define PFIT_ENABLE (1 << 31)
4688#define PFIT_PIPE_MASK (3 << 29)
4689#define PFIT_PIPE_SHIFT 29
4690#define VERT_INTERP_DISABLE (0 << 10)
4691#define VERT_INTERP_BILINEAR (1 << 10)
4692#define VERT_INTERP_MASK (3 << 10)
4693#define VERT_AUTO_SCALE (1 << 9)
4694#define HORIZ_INTERP_DISABLE (0 << 6)
4695#define HORIZ_INTERP_BILINEAR (1 << 6)
4696#define HORIZ_INTERP_MASK (3 << 6)
4697#define HORIZ_AUTO_SCALE (1 << 5)
4698#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
4699#define PFIT_FILTER_FUZZY (0 << 24)
4700#define PFIT_SCALING_AUTO (0 << 26)
4701#define PFIT_SCALING_PROGRAMMED (1 << 26)
4702#define PFIT_SCALING_PILLAR (2 << 26)
4703#define PFIT_SCALING_LETTER (3 << 26)
4704#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
4705
4706#define PFIT_VERT_SCALE_SHIFT 20
4707#define PFIT_VERT_SCALE_MASK 0xfff00000
4708#define PFIT_HORIZ_SCALE_SHIFT 4
4709#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
4710
4711#define PFIT_VERT_SCALE_SHIFT_965 16
4712#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
4713#define PFIT_HORIZ_SCALE_SHIFT_965 0
4714#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4715
4716#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
4717
4718#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
4719#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
4720#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4721 _VLV_BLC_PWM_CTL2_B)
4722
4723#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
4724#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
4725#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4726 _VLV_BLC_PWM_CTL_B)
4727
4728#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
4729#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
4730#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4731 _VLV_BLC_HIST_CTL_B)
4732
4733
4734#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250)
4735#define BLM_PWM_ENABLE (1 << 31)
4736#define BLM_COMBINATION_MODE (1 << 30)
4737#define BLM_PIPE_SELECT (1 << 29)
4738#define BLM_PIPE_SELECT_IVB (3 << 29)
4739#define BLM_PIPE_A (0 << 29)
4740#define BLM_PIPE_B (1 << 29)
4741#define BLM_PIPE_C (2 << 29)
4742#define BLM_TRANSCODER_A BLM_PIPE_A
4743#define BLM_TRANSCODER_B BLM_PIPE_B
4744#define BLM_TRANSCODER_C BLM_PIPE_C
4745#define BLM_TRANSCODER_EDP (3 << 29)
4746#define BLM_PIPE(pipe) ((pipe) << 29)
4747#define BLM_POLARITY_I965 (1 << 28)
4748#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
4749#define BLM_PHASE_IN_ENABLE (1 << 25)
4750#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
4751#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
4752#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
4753#define BLM_PHASE_IN_COUNT_SHIFT (8)
4754#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4755#define BLM_PHASE_IN_INCR_SHIFT (0)
4756#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
4757#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
4758
4759
4760
4761
4762
4763
4764#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
4765#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
4766#define BLM_LEGACY_MODE (1 << 16)
4767
4768
4769
4770
4771
4772
4773
4774#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
4775#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
4776#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4777#define BLM_POLARITY_PNV (1 << 0)
4778
4779#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
4780#define BLM_HISTOGRAM_ENABLE (1 << 31)
4781
4782
4783
4784#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
4785#define BLC_PWM_CPU_CTL _MMIO(0x48254)
4786
4787#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
4788
4789
4790
4791#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
4792#define BLM_PCH_PWM_ENABLE (1 << 31)
4793#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
4794#define BLM_PCH_POLARITY (1 << 29)
4795#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
4796
4797#define UTIL_PIN_CTL _MMIO(0x48400)
4798#define UTIL_PIN_ENABLE (1 << 31)
4799
4800#define UTIL_PIN_PIPE(x) ((x) << 29)
4801#define UTIL_PIN_PIPE_MASK (3 << 29)
4802#define UTIL_PIN_MODE_PWM (1 << 24)
4803#define UTIL_PIN_MODE_MASK (0xf << 24)
4804#define UTIL_PIN_POLARITY (1 << 22)
4805
4806
4807#define _BXT_BLC_PWM_CTL1 0xC8250
4808#define BXT_BLC_PWM_ENABLE (1 << 31)
4809#define BXT_BLC_PWM_POLARITY (1 << 29)
4810#define _BXT_BLC_PWM_FREQ1 0xC8254
4811#define _BXT_BLC_PWM_DUTY1 0xC8258
4812
4813#define _BXT_BLC_PWM_CTL2 0xC8350
4814#define _BXT_BLC_PWM_FREQ2 0xC8354
4815#define _BXT_BLC_PWM_DUTY2 0xC8358
4816
4817#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
4818 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4819#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
4820 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4821#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
4822 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4823
4824#define PCH_GTC_CTL _MMIO(0xe7000)
4825#define PCH_GTC_ENABLE (1 << 31)
4826
4827
4828#define TV_CTL _MMIO(0x68000)
4829
4830# define TV_ENC_ENABLE (1 << 31)
4831
4832# define TV_ENC_PIPE_SEL_SHIFT 30
4833# define TV_ENC_PIPE_SEL_MASK (1 << 30)
4834# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
4835
4836# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
4837
4838# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
4839
4840# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
4841
4842# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4843# define TV_TRILEVEL_SYNC (1 << 21)
4844
4845# define TV_SLOW_SYNC (1 << 20)
4846
4847# define TV_OVERSAMPLE_4X (0 << 18)
4848
4849# define TV_OVERSAMPLE_2X (1 << 18)
4850
4851# define TV_OVERSAMPLE_NONE (2 << 18)
4852
4853# define TV_OVERSAMPLE_8X (3 << 18)
4854
4855# define TV_PROGRESSIVE (1 << 17)
4856
4857# define TV_PAL_BURST (1 << 16)
4858
4859# define TV_YC_SKEW_MASK (7 << 12)
4860
4861# define TV_ENC_SDP_FIX (1 << 11)
4862
4863
4864
4865
4866
4867# define TV_ENC_C0_FIX (1 << 10)
4868
4869# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
4870# define TV_FUSE_STATE_MASK (3 << 4)
4871
4872# define TV_FUSE_STATE_ENABLED (0 << 4)
4873
4874# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
4875
4876# define TV_FUSE_STATE_DISABLED (2 << 4)
4877
4878# define TV_TEST_MODE_NORMAL (0 << 0)
4879
4880# define TV_TEST_MODE_PATTERN_1 (1 << 0)
4881
4882# define TV_TEST_MODE_PATTERN_2 (2 << 0)
4883
4884# define TV_TEST_MODE_PATTERN_3 (3 << 0)
4885
4886# define TV_TEST_MODE_PATTERN_4 (4 << 0)
4887
4888# define TV_TEST_MODE_PATTERN_5 (5 << 0)
4889
4890
4891
4892
4893
4894# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
4895# define TV_TEST_MODE_MASK (7 << 0)
4896
4897#define TV_DAC _MMIO(0x68004)
4898# define TV_DAC_SAVE 0x00ffff00
4899
4900
4901
4902
4903
4904# define TVDAC_STATE_CHG (1 << 31)
4905# define TVDAC_SENSE_MASK (7 << 28)
4906
4907# define TVDAC_A_SENSE (1 << 30)
4908
4909# define TVDAC_B_SENSE (1 << 29)
4910
4911# define TVDAC_C_SENSE (1 << 28)
4912
4913
4914
4915
4916
4917
4918# define TVDAC_STATE_CHG_EN (1 << 27)
4919
4920# define TVDAC_A_SENSE_CTL (1 << 26)
4921
4922# define TVDAC_B_SENSE_CTL (1 << 25)
4923
4924# define TVDAC_C_SENSE_CTL (1 << 24)
4925
4926# define DAC_CTL_OVERRIDE (1 << 7)
4927
4928# define ENC_TVDAC_SLEW_FAST (1 << 6)
4929# define DAC_A_1_3_V (0 << 4)
4930# define DAC_A_1_1_V (1 << 4)
4931# define DAC_A_0_7_V (2 << 4)
4932# define DAC_A_MASK (3 << 4)
4933# define DAC_B_1_3_V (0 << 2)
4934# define DAC_B_1_1_V (1 << 2)
4935# define DAC_B_0_7_V (2 << 2)
4936# define DAC_B_MASK (3 << 2)
4937# define DAC_C_1_3_V (0 << 0)
4938# define DAC_C_1_1_V (1 << 0)
4939# define DAC_C_0_7_V (2 << 0)
4940# define DAC_C_MASK (3 << 0)
4941
4942
4943
4944
4945
4946
4947
4948#define TV_CSC_Y _MMIO(0x68010)
4949# define TV_RY_MASK 0x07ff0000
4950# define TV_RY_SHIFT 16
4951# define TV_GY_MASK 0x00000fff
4952# define TV_GY_SHIFT 0
4953
4954#define TV_CSC_Y2 _MMIO(0x68014)
4955# define TV_BY_MASK 0x07ff0000
4956# define TV_BY_SHIFT 16
4957
4958
4959
4960
4961
4962# define TV_AY_MASK 0x000003ff
4963# define TV_AY_SHIFT 0
4964
4965#define TV_CSC_U _MMIO(0x68018)
4966# define TV_RU_MASK 0x07ff0000
4967# define TV_RU_SHIFT 16
4968# define TV_GU_MASK 0x000007ff
4969# define TV_GU_SHIFT 0
4970
4971#define TV_CSC_U2 _MMIO(0x6801c)
4972# define TV_BU_MASK 0x07ff0000
4973# define TV_BU_SHIFT 16
4974
4975
4976
4977
4978
4979# define TV_AU_MASK 0x000003ff
4980# define TV_AU_SHIFT 0
4981
4982#define TV_CSC_V _MMIO(0x68020)
4983# define TV_RV_MASK 0x0fff0000
4984# define TV_RV_SHIFT 16
4985# define TV_GV_MASK 0x000007ff
4986# define TV_GV_SHIFT 0
4987
4988#define TV_CSC_V2 _MMIO(0x68024)
4989# define TV_BV_MASK 0x07ff0000
4990# define TV_BV_SHIFT 16
4991
4992
4993
4994
4995
4996# define TV_AV_MASK 0x000007ff
4997# define TV_AV_SHIFT 0
4998
4999#define TV_CLR_KNOBS _MMIO(0x68028)
5000
5001# define TV_BRIGHTNESS_MASK 0xff000000
5002# define TV_BRIGHTNESS_SHIFT 24
5003
5004# define TV_CONTRAST_MASK 0x00ff0000
5005# define TV_CONTRAST_SHIFT 16
5006
5007# define TV_SATURATION_MASK 0x0000ff00
5008# define TV_SATURATION_SHIFT 8
5009
5010# define TV_HUE_MASK 0x000000ff
5011# define TV_HUE_SHIFT 0
5012
5013#define TV_CLR_LEVEL _MMIO(0x6802c)
5014
5015# define TV_BLACK_LEVEL_MASK 0x01ff0000
5016# define TV_BLACK_LEVEL_SHIFT 16
5017
5018# define TV_BLANK_LEVEL_MASK 0x000001ff
5019# define TV_BLANK_LEVEL_SHIFT 0
5020
5021#define TV_H_CTL_1 _MMIO(0x68030)
5022
5023# define TV_HSYNC_END_MASK 0x1fff0000
5024# define TV_HSYNC_END_SHIFT 16
5025
5026# define TV_HTOTAL_MASK 0x00001fff
5027# define TV_HTOTAL_SHIFT 0
5028
5029#define TV_H_CTL_2 _MMIO(0x68034)
5030
5031# define TV_BURST_ENA (1 << 31)
5032
5033# define TV_HBURST_START_SHIFT 16
5034# define TV_HBURST_START_MASK 0x1fff0000
5035
5036# define TV_HBURST_LEN_SHIFT 0
5037# define TV_HBURST_LEN_MASK 0x0001fff
5038
5039#define TV_H_CTL_3 _MMIO(0x68038)
5040
5041# define TV_HBLANK_END_SHIFT 16
5042# define TV_HBLANK_END_MASK 0x1fff0000
5043
5044# define TV_HBLANK_START_SHIFT 0
5045# define TV_HBLANK_START_MASK 0x0001fff
5046
5047#define TV_V_CTL_1 _MMIO(0x6803c)
5048
5049# define TV_NBR_END_SHIFT 16
5050# define TV_NBR_END_MASK 0x07ff0000
5051
5052# define TV_VI_END_F1_SHIFT 8
5053# define TV_VI_END_F1_MASK 0x00003f00
5054
5055# define TV_VI_END_F2_SHIFT 0
5056# define TV_VI_END_F2_MASK 0x0000003f
5057
5058#define TV_V_CTL_2 _MMIO(0x68040)
5059
5060# define TV_VSYNC_LEN_MASK 0x07ff0000
5061# define TV_VSYNC_LEN_SHIFT 16
5062
5063
5064
5065# define TV_VSYNC_START_F1_MASK 0x00007f00
5066# define TV_VSYNC_START_F1_SHIFT 8
5067
5068
5069
5070
5071# define TV_VSYNC_START_F2_MASK 0x0000007f
5072# define TV_VSYNC_START_F2_SHIFT 0
5073
5074#define TV_V_CTL_3 _MMIO(0x68044)
5075
5076# define TV_EQUAL_ENA (1 << 31)
5077
5078# define TV_VEQ_LEN_MASK 0x007f0000
5079# define TV_VEQ_LEN_SHIFT 16
5080
5081
5082
5083# define TV_VEQ_START_F1_MASK 0x0007f00
5084# define TV_VEQ_START_F1_SHIFT 8
5085
5086
5087
5088
5089# define TV_VEQ_START_F2_MASK 0x000007f
5090# define TV_VEQ_START_F2_SHIFT 0
5091
5092#define TV_V_CTL_4 _MMIO(0x68048)
5093
5094
5095
5096
5097# define TV_VBURST_START_F1_MASK 0x003f0000
5098# define TV_VBURST_START_F1_SHIFT 16
5099
5100
5101
5102
5103# define TV_VBURST_END_F1_MASK 0x000000ff
5104# define TV_VBURST_END_F1_SHIFT 0
5105
5106#define TV_V_CTL_5 _MMIO(0x6804c)
5107
5108
5109
5110
5111# define TV_VBURST_START_F2_MASK 0x003f0000
5112# define TV_VBURST_START_F2_SHIFT 16
5113
5114
5115
5116
5117# define TV_VBURST_END_F2_MASK 0x000000ff
5118# define TV_VBURST_END_F2_SHIFT 0
5119
5120#define TV_V_CTL_6 _MMIO(0x68050)
5121
5122
5123
5124
5125# define TV_VBURST_START_F3_MASK 0x003f0000
5126# define TV_VBURST_START_F3_SHIFT 16
5127
5128
5129
5130
5131# define TV_VBURST_END_F3_MASK 0x000000ff
5132# define TV_VBURST_END_F3_SHIFT 0
5133
5134#define TV_V_CTL_7 _MMIO(0x68054)
5135
5136
5137
5138
5139# define TV_VBURST_START_F4_MASK 0x003f0000
5140# define TV_VBURST_START_F4_SHIFT 16
5141
5142
5143
5144
5145# define TV_VBURST_END_F4_MASK 0x000000ff
5146# define TV_VBURST_END_F4_SHIFT 0
5147
5148#define TV_SC_CTL_1 _MMIO(0x68060)
5149
5150# define TV_SC_DDA1_EN (1 << 31)
5151
5152# define TV_SC_DDA2_EN (1 << 30)
5153
5154# define TV_SC_DDA3_EN (1 << 29)
5155
5156# define TV_SC_RESET_EVERY_2 (0 << 24)
5157
5158# define TV_SC_RESET_EVERY_4 (1 << 24)
5159
5160# define TV_SC_RESET_EVERY_8 (2 << 24)
5161
5162# define TV_SC_RESET_NEVER (3 << 24)
5163
5164# define TV_BURST_LEVEL_MASK 0x00ff0000
5165# define TV_BURST_LEVEL_SHIFT 16
5166
5167# define TV_SCDDA1_INC_MASK 0x00000fff
5168# define TV_SCDDA1_INC_SHIFT 0
5169
5170#define TV_SC_CTL_2 _MMIO(0x68064)
5171
5172# define TV_SCDDA2_SIZE_MASK 0x7fff0000
5173# define TV_SCDDA2_SIZE_SHIFT 16
5174
5175# define TV_SCDDA2_INC_MASK 0x00007fff
5176# define TV_SCDDA2_INC_SHIFT 0
5177
5178#define TV_SC_CTL_3 _MMIO(0x68068)
5179
5180# define TV_SCDDA3_SIZE_MASK 0x7fff0000
5181# define TV_SCDDA3_SIZE_SHIFT 16
5182
5183# define TV_SCDDA3_INC_MASK 0x00007fff
5184# define TV_SCDDA3_INC_SHIFT 0
5185
5186#define TV_WIN_POS _MMIO(0x68070)
5187
5188# define TV_XPOS_MASK 0x1fff0000
5189# define TV_XPOS_SHIFT 16
5190
5191# define TV_YPOS_MASK 0x00000fff
5192# define TV_YPOS_SHIFT 0
5193
5194#define TV_WIN_SIZE _MMIO(0x68074)
5195
5196# define TV_XSIZE_MASK 0x1fff0000
5197# define TV_XSIZE_SHIFT 16
5198
5199
5200
5201
5202
5203# define TV_YSIZE_MASK 0x00000fff
5204# define TV_YSIZE_SHIFT 0
5205
5206#define TV_FILTER_CTL_1 _MMIO(0x68080)
5207
5208
5209
5210
5211
5212
5213# define TV_AUTO_SCALE (1 << 31)
5214
5215
5216
5217
5218# define TV_V_FILTER_BYPASS (1 << 29)
5219
5220# define TV_VADAPT (1 << 28)
5221# define TV_VADAPT_MODE_MASK (3 << 26)
5222
5223# define TV_VADAPT_MODE_LEAST (0 << 26)
5224
5225# define TV_VADAPT_MODE_MODERATE (1 << 26)
5226
5227# define TV_VADAPT_MODE_MOST (3 << 26)
5228
5229
5230
5231
5232
5233
5234
5235
5236# define TV_HSCALE_FRAC_MASK 0x00003fff
5237# define TV_HSCALE_FRAC_SHIFT 0
5238
5239#define TV_FILTER_CTL_2 _MMIO(0x68084)
5240
5241
5242
5243
5244
5245# define TV_VSCALE_INT_MASK 0x00038000
5246# define TV_VSCALE_INT_SHIFT 15
5247
5248
5249
5250
5251
5252# define TV_VSCALE_FRAC_MASK 0x00007fff
5253# define TV_VSCALE_FRAC_SHIFT 0
5254
5255#define TV_FILTER_CTL_3 _MMIO(0x68088)
5256
5257
5258
5259
5260
5261
5262
5263# define TV_VSCALE_IP_INT_MASK 0x00038000
5264# define TV_VSCALE_IP_INT_SHIFT 15
5265
5266
5267
5268
5269
5270
5271
5272# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5273# define TV_VSCALE_IP_FRAC_SHIFT 0
5274
5275#define TV_CC_CONTROL _MMIO(0x68090)
5276# define TV_CC_ENABLE (1 << 31)
5277
5278
5279
5280
5281
5282# define TV_CC_FID_MASK (1 << 27)
5283# define TV_CC_FID_SHIFT 27
5284
5285# define TV_CC_HOFF_MASK 0x03ff0000
5286# define TV_CC_HOFF_SHIFT 16
5287
5288# define TV_CC_LINE_MASK 0x0000003f
5289# define TV_CC_LINE_SHIFT 0
5290
5291#define TV_CC_DATA _MMIO(0x68094)
5292# define TV_CC_RDY (1 << 31)
5293
5294# define TV_CC_DATA_2_MASK 0x007f0000
5295# define TV_CC_DATA_2_SHIFT 16
5296
5297# define TV_CC_DATA_1_MASK 0x0000007f
5298# define TV_CC_DATA_1_SHIFT 0
5299
5300#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4)
5301#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4)
5302#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4)
5303#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4)
5304
5305
5306#define DP_A _MMIO(0x64000)
5307#define DP_B _MMIO(0x64100)
5308#define DP_C _MMIO(0x64200)
5309#define DP_D _MMIO(0x64300)
5310
5311#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5312#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5313#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5314
5315#define DP_PORT_EN (1 << 31)
5316#define DP_PIPE_SEL_SHIFT 30
5317#define DP_PIPE_SEL_MASK (1 << 30)
5318#define DP_PIPE_SEL(pipe) ((pipe) << 30)
5319#define DP_PIPE_SEL_SHIFT_IVB 29
5320#define DP_PIPE_SEL_MASK_IVB (3 << 29)
5321#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
5322#define DP_PIPE_SEL_SHIFT_CHV 16
5323#define DP_PIPE_SEL_MASK_CHV (3 << 16)
5324#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
5325
5326
5327#define DP_LINK_TRAIN_PAT_1 (0 << 28)
5328#define DP_LINK_TRAIN_PAT_2 (1 << 28)
5329#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5330#define DP_LINK_TRAIN_OFF (3 << 28)
5331#define DP_LINK_TRAIN_MASK (3 << 28)
5332#define DP_LINK_TRAIN_SHIFT 28
5333
5334
5335#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5336#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5337#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5338#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5339#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5340#define DP_LINK_TRAIN_SHIFT_CPT 8
5341
5342
5343#define DP_VOLTAGE_0_4 (0 << 25)
5344#define DP_VOLTAGE_0_6 (1 << 25)
5345#define DP_VOLTAGE_0_8 (2 << 25)
5346#define DP_VOLTAGE_1_2 (3 << 25)
5347#define DP_VOLTAGE_MASK (7 << 25)
5348#define DP_VOLTAGE_SHIFT 25
5349
5350
5351
5352
5353#define DP_PRE_EMPHASIS_0 (0 << 22)
5354#define DP_PRE_EMPHASIS_3_5 (1 << 22)
5355#define DP_PRE_EMPHASIS_6 (2 << 22)
5356#define DP_PRE_EMPHASIS_9_5 (3 << 22)
5357#define DP_PRE_EMPHASIS_MASK (7 << 22)
5358#define DP_PRE_EMPHASIS_SHIFT 22
5359
5360
5361#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5362#define DP_PORT_WIDTH_MASK (7 << 19)
5363#define DP_PORT_WIDTH_SHIFT 19
5364
5365
5366#define DP_ENHANCED_FRAMING (1 << 18)
5367
5368
5369#define DP_PLL_FREQ_270MHZ (0 << 16)
5370#define DP_PLL_FREQ_162MHZ (1 << 16)
5371#define DP_PLL_FREQ_MASK (3 << 16)
5372
5373
5374#define DP_PORT_REVERSAL (1 << 15)
5375
5376
5377#define DP_PLL_ENABLE (1 << 14)
5378
5379
5380#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5381
5382#define DP_SCRAMBLING_DISABLE (1 << 12)
5383#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
5384
5385
5386#define DP_COLOR_RANGE_16_235 (1 << 8)
5387
5388
5389#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5390
5391
5392#define DP_SYNC_VS_HIGH (1 << 4)
5393#define DP_SYNC_HS_HIGH (1 << 3)
5394
5395
5396#define DP_DETECTED (1 << 2)
5397
5398
5399
5400
5401
5402
5403#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
5404#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
5405#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
5406#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
5407#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
5408#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
5409
5410#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
5411#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
5412#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
5413#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
5414#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
5415#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
5416
5417#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
5418#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
5419#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
5420#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
5421#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
5422#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
5423
5424#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
5425#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
5426#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
5427#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
5428#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
5429#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
5430
5431#define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410)
5432#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414)
5433#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418)
5434#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c)
5435#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420)
5436#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424)
5437
5438#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
5439#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
5440#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
5441#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
5442#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
5443#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
5444
5445#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5446#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4)
5447
5448#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5449#define DP_AUX_CH_CTL_DONE (1 << 30)
5450#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5451#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5452#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5453#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5454#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
5455#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26)
5456#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5457#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5458#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5459#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5460#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5461#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5462#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5463#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5464#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5465#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5466#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5467#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5468#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
5469#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5470#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5471#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5472#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
5473#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5474#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5475#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490#define _PIPEA_DATA_M_G4X 0x70050
5491#define _PIPEB_DATA_M_G4X 0x71050
5492
5493
5494#define TU_SIZE(x) (((x) - 1) << 25)
5495#define TU_SIZE_SHIFT 25
5496#define TU_SIZE_MASK (0x3f << 25)
5497
5498#define DATA_LINK_M_N_MASK (0xffffff)
5499#define DATA_LINK_N_MAX (0x800000)
5500
5501#define _PIPEA_DATA_N_G4X 0x70054
5502#define _PIPEB_DATA_N_G4X 0x71054
5503#define PIPE_GMCH_DATA_N_MASK (0xffffff)
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516#define _PIPEA_LINK_M_G4X 0x70060
5517#define _PIPEB_LINK_M_G4X 0x71060
5518#define PIPEA_DP_LINK_M_MASK (0xffffff)
5519
5520#define _PIPEA_LINK_N_G4X 0x70064
5521#define _PIPEB_LINK_N_G4X 0x71064
5522#define PIPEA_DP_LINK_N_MASK (0xffffff)
5523
5524#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5525#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5526#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5527#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5528
5529
5530
5531
5532#define _PIPEADSL 0x70000
5533#define DSL_LINEMASK_GEN2 0x00000fff
5534#define DSL_LINEMASK_GEN3 0x00001fff
5535#define _PIPEACONF 0x70008
5536#define PIPECONF_ENABLE (1 << 31)
5537#define PIPECONF_DISABLE 0
5538#define PIPECONF_DOUBLE_WIDE (1 << 30)
5539#define I965_PIPECONF_ACTIVE (1 << 30)
5540#define PIPECONF_DSI_PLL_LOCKED (1 << 29)
5541#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
5542#define PIPECONF_SINGLE_WIDE 0
5543#define PIPECONF_PIPE_UNLOCKED 0
5544#define PIPECONF_PIPE_LOCKED (1 << 25)
5545#define PIPECONF_PALETTE 0
5546#define PIPECONF_GAMMA (1 << 24)
5547#define PIPECONF_FORCE_BORDER (1 << 25)
5548#define PIPECONF_INTERLACE_MASK (7 << 21)
5549#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
5550
5551
5552#define PIPECONF_PROGRESSIVE (0 << 21)
5553#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21)
5554#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21)
5555#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5556#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
5557
5558
5559
5560#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
5561#define PIPECONF_INTERLACED_ILK (3 << 21)
5562#define PIPECONF_INTERLACED_DBL_ILK (4 << 21)
5563#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21)
5564#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
5565#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
5566#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
5567#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
5568#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
5569#define PIPECONF_BPC_MASK (0x7 << 5)
5570#define PIPECONF_8BPC (0 << 5)
5571#define PIPECONF_10BPC (1 << 5)
5572#define PIPECONF_6BPC (2 << 5)
5573#define PIPECONF_12BPC (3 << 5)
5574#define PIPECONF_DITHER_EN (1 << 4)
5575#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5576#define PIPECONF_DITHER_TYPE_SP (0 << 2)
5577#define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
5578#define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
5579#define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
5580#define _PIPEASTAT 0x70024
5581#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
5582#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
5583#define PIPE_CRC_ERROR_ENABLE (1UL << 29)
5584#define PIPE_CRC_DONE_ENABLE (1UL << 28)
5585#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
5586#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
5587#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
5588#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
5589#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
5590#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
5591#define PIPE_DPST_EVENT_ENABLE (1UL << 23)
5592#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
5593#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
5594#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
5595#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
5596#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
5597#define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
5598#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18)
5599#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18)
5600#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
5601#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
5602#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
5603#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
5604#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
5605#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
5606#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
5607#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
5608#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
5609#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
5610#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
5611#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
5612#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
5613#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
5614#define PIPE_DPST_EVENT_STATUS (1UL << 7)
5615#define PIPE_A_PSR_STATUS_VLV (1UL << 6)
5616#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
5617#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
5618#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
5619#define PIPE_B_PSR_STATUS_VLV (1UL << 3)
5620#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
5621#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2)
5622#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2)
5623#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
5624#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
5625#define PIPE_HBLANK_INT_STATUS (1UL << 0)
5626#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
5627
5628#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
5629#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
5630
5631#define PIPE_A_OFFSET 0x70000
5632#define PIPE_B_OFFSET 0x71000
5633#define PIPE_C_OFFSET 0x72000
5634#define CHV_PIPE_C_OFFSET 0x74000
5635
5636
5637
5638
5639
5640
5641#define PIPE_EDP_OFFSET 0x7f000
5642
5643#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
5644 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
5645 dev_priv->info.display_mmio_offset)
5646
5647#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5648#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
5649#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5650#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5651#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
5652
5653#define _PIPE_MISC_A 0x70030
5654#define _PIPE_MISC_B 0x71030
5655#define PIPEMISC_YUV420_ENABLE (1 << 27)
5656#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
5657#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
5658#define PIPEMISC_DITHER_BPC_MASK (7 << 5)
5659#define PIPEMISC_DITHER_8_BPC (0 << 5)
5660#define PIPEMISC_DITHER_10_BPC (1 << 5)
5661#define PIPEMISC_DITHER_6_BPC (2 << 5)
5662#define PIPEMISC_DITHER_12_BPC (3 << 5)
5663#define PIPEMISC_DITHER_ENABLE (1 << 4)
5664#define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
5665#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
5666#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5667
5668#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5669#define PIPEB_LINE_COMPARE_INT_EN (1 << 29)
5670#define PIPEB_HLINE_INT_EN (1 << 28)
5671#define PIPEB_VBLANK_INT_EN (1 << 27)
5672#define SPRITED_FLIP_DONE_INT_EN (1 << 26)
5673#define SPRITEC_FLIP_DONE_INT_EN (1 << 25)
5674#define PLANEB_FLIP_DONE_INT_EN (1 << 24)
5675#define PIPE_PSR_INT_EN (1 << 22)
5676#define PIPEA_LINE_COMPARE_INT_EN (1 << 21)
5677#define PIPEA_HLINE_INT_EN (1 << 20)
5678#define PIPEA_VBLANK_INT_EN (1 << 19)
5679#define SPRITEB_FLIP_DONE_INT_EN (1 << 18)
5680#define SPRITEA_FLIP_DONE_INT_EN (1 << 17)
5681#define PLANEA_FLIPDONE_INT_EN (1 << 16)
5682#define PIPEC_LINE_COMPARE_INT_EN (1 << 13)
5683#define PIPEC_HLINE_INT_EN (1 << 12)
5684#define PIPEC_VBLANK_INT_EN (1 << 11)
5685#define SPRITEF_FLIPDONE_INT_EN (1 << 10)
5686#define SPRITEE_FLIPDONE_INT_EN (1 << 9)
5687#define PLANEC_FLIPDONE_INT_EN (1 << 8)
5688
5689#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c)
5690#define SPRITEF_INVALID_GTT_INT_EN (1 << 27)
5691#define SPRITEE_INVALID_GTT_INT_EN (1 << 26)
5692#define PLANEC_INVALID_GTT_INT_EN (1 << 25)
5693#define CURSORC_INVALID_GTT_INT_EN (1 << 24)
5694#define CURSORB_INVALID_GTT_INT_EN (1 << 23)
5695#define CURSORA_INVALID_GTT_INT_EN (1 << 22)
5696#define SPRITED_INVALID_GTT_INT_EN (1 << 21)
5697#define SPRITEC_INVALID_GTT_INT_EN (1 << 20)
5698#define PLANEB_INVALID_GTT_INT_EN (1 << 19)
5699#define SPRITEB_INVALID_GTT_INT_EN (1 << 18)
5700#define SPRITEA_INVALID_GTT_INT_EN (1 << 17)
5701#define PLANEA_INVALID_GTT_INT_EN (1 << 16)
5702#define DPINVGTT_EN_MASK 0xff0000
5703#define DPINVGTT_EN_MASK_CHV 0xfff0000
5704#define SPRITEF_INVALID_GTT_STATUS (1 << 11)
5705#define SPRITEE_INVALID_GTT_STATUS (1 << 10)
5706#define PLANEC_INVALID_GTT_STATUS (1 << 9)
5707#define CURSORC_INVALID_GTT_STATUS (1 << 8)
5708#define CURSORB_INVALID_GTT_STATUS (1 << 7)
5709#define CURSORA_INVALID_GTT_STATUS (1 << 6)
5710#define SPRITED_INVALID_GTT_STATUS (1 << 5)
5711#define SPRITEC_INVALID_GTT_STATUS (1 << 4)
5712#define PLANEB_INVALID_GTT_STATUS (1 << 3)
5713#define SPRITEB_INVALID_GTT_STATUS (1 << 2)
5714#define SPRITEA_INVALID_GTT_STATUS (1 << 1)
5715#define PLANEA_INVALID_GTT_STATUS (1 << 0)
5716#define DPINVGTT_STATUS_MASK 0xff
5717#define DPINVGTT_STATUS_MASK_CHV 0xfff
5718
5719#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
5720#define DSPARB_CSTART_MASK (0x7f << 7)
5721#define DSPARB_CSTART_SHIFT 7
5722#define DSPARB_BSTART_MASK (0x7f)
5723#define DSPARB_BSTART_SHIFT 0
5724#define DSPARB_BEND_SHIFT 9
5725#define DSPARB_AEND_SHIFT 0
5726#define DSPARB_SPRITEA_SHIFT_VLV 0
5727#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
5728#define DSPARB_SPRITEB_SHIFT_VLV 8
5729#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
5730#define DSPARB_SPRITEC_SHIFT_VLV 16
5731#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
5732#define DSPARB_SPRITED_SHIFT_VLV 24
5733#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
5734#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060)
5735#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
5736#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
5737#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
5738#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
5739#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
5740#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
5741#define DSPARB_SPRITED_HI_SHIFT_VLV 12
5742#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
5743#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
5744#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
5745#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
5746#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
5747#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c)
5748#define DSPARB_SPRITEE_SHIFT_VLV 0
5749#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
5750#define DSPARB_SPRITEF_SHIFT_VLV 8
5751#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
5752
5753
5754#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
5755#define DSPFW_SR_SHIFT 23
5756#define DSPFW_SR_MASK (0x1ff << 23)
5757#define DSPFW_CURSORB_SHIFT 16
5758#define DSPFW_CURSORB_MASK (0x3f << 16)
5759#define DSPFW_PLANEB_SHIFT 8
5760#define DSPFW_PLANEB_MASK (0x7f << 8)
5761#define DSPFW_PLANEB_MASK_VLV (0xff << 8)
5762#define DSPFW_PLANEA_SHIFT 0
5763#define DSPFW_PLANEA_MASK (0x7f << 0)
5764#define DSPFW_PLANEA_MASK_VLV (0xff << 0)
5765#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
5766#define DSPFW_FBC_SR_EN (1 << 31)
5767#define DSPFW_FBC_SR_SHIFT 28
5768#define DSPFW_FBC_SR_MASK (0x7 << 28)
5769#define DSPFW_FBC_HPLL_SR_SHIFT 24
5770#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24)
5771#define DSPFW_SPRITEB_SHIFT (16)
5772#define DSPFW_SPRITEB_MASK (0x7f << 16)
5773#define DSPFW_SPRITEB_MASK_VLV (0xff << 16)
5774#define DSPFW_CURSORA_SHIFT 8
5775#define DSPFW_CURSORA_MASK (0x3f << 8)
5776#define DSPFW_PLANEC_OLD_SHIFT 0
5777#define DSPFW_PLANEC_OLD_MASK (0x7f << 0)
5778#define DSPFW_SPRITEA_SHIFT 0
5779#define DSPFW_SPRITEA_MASK (0x7f << 0)
5780#define DSPFW_SPRITEA_MASK_VLV (0xff << 0)
5781#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
5782#define DSPFW_HPLL_SR_EN (1 << 31)
5783#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
5784#define DSPFW_CURSOR_SR_SHIFT 24
5785#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
5786#define DSPFW_HPLL_CURSOR_SHIFT 16
5787#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
5788#define DSPFW_HPLL_SR_SHIFT 0
5789#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
5790
5791
5792#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5793#define DSPFW_SPRITEB_WM1_SHIFT 16
5794#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
5795#define DSPFW_CURSORA_WM1_SHIFT 8
5796#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
5797#define DSPFW_SPRITEA_WM1_SHIFT 0
5798#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
5799#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5800#define DSPFW_PLANEB_WM1_SHIFT 24
5801#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
5802#define DSPFW_PLANEA_WM1_SHIFT 16
5803#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
5804#define DSPFW_CURSORB_WM1_SHIFT 8
5805#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
5806#define DSPFW_CURSOR_SR_WM1_SHIFT 0
5807#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
5808#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5809#define DSPFW_SR_WM1_SHIFT 0
5810#define DSPFW_SR_WM1_MASK (0x1ff << 0)
5811#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5812#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4)
5813#define DSPFW_SPRITED_WM1_SHIFT 24
5814#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
5815#define DSPFW_SPRITED_SHIFT 16
5816#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
5817#define DSPFW_SPRITEC_WM1_SHIFT 8
5818#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
5819#define DSPFW_SPRITEC_SHIFT 0
5820#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
5821#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5822#define DSPFW_SPRITEF_WM1_SHIFT 24
5823#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
5824#define DSPFW_SPRITEF_SHIFT 16
5825#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
5826#define DSPFW_SPRITEE_WM1_SHIFT 8
5827#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
5828#define DSPFW_SPRITEE_SHIFT 0
5829#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
5830#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5831#define DSPFW_PLANEC_WM1_SHIFT 24
5832#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
5833#define DSPFW_PLANEC_SHIFT 16
5834#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
5835#define DSPFW_CURSORC_WM1_SHIFT 8
5836#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
5837#define DSPFW_CURSORC_SHIFT 0
5838#define DSPFW_CURSORC_MASK (0x3f << 0)
5839
5840
5841#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
5842#define DSPFW_SR_HI_SHIFT 24
5843#define DSPFW_SR_HI_MASK (3 << 24)
5844#define DSPFW_SPRITEF_HI_SHIFT 23
5845#define DSPFW_SPRITEF_HI_MASK (1 << 23)
5846#define DSPFW_SPRITEE_HI_SHIFT 22
5847#define DSPFW_SPRITEE_HI_MASK (1 << 22)
5848#define DSPFW_PLANEC_HI_SHIFT 21
5849#define DSPFW_PLANEC_HI_MASK (1 << 21)
5850#define DSPFW_SPRITED_HI_SHIFT 20
5851#define DSPFW_SPRITED_HI_MASK (1 << 20)
5852#define DSPFW_SPRITEC_HI_SHIFT 16
5853#define DSPFW_SPRITEC_HI_MASK (1 << 16)
5854#define DSPFW_PLANEB_HI_SHIFT 12
5855#define DSPFW_PLANEB_HI_MASK (1 << 12)
5856#define DSPFW_SPRITEB_HI_SHIFT 8
5857#define DSPFW_SPRITEB_HI_MASK (1 << 8)
5858#define DSPFW_SPRITEA_HI_SHIFT 4
5859#define DSPFW_SPRITEA_HI_MASK (1 << 4)
5860#define DSPFW_PLANEA_HI_SHIFT 0
5861#define DSPFW_PLANEA_HI_MASK (1 << 0)
5862#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
5863#define DSPFW_SR_WM1_HI_SHIFT 24
5864#define DSPFW_SR_WM1_HI_MASK (3 << 24)
5865#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
5866#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
5867#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
5868#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
5869#define DSPFW_PLANEC_WM1_HI_SHIFT 21
5870#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
5871#define DSPFW_SPRITED_WM1_HI_SHIFT 20
5872#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
5873#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
5874#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
5875#define DSPFW_PLANEB_WM1_HI_SHIFT 12
5876#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
5877#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
5878#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
5879#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
5880#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
5881#define DSPFW_PLANEA_WM1_HI_SHIFT 0
5882#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
5883
5884
5885#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5886#define DDL_CURSOR_SHIFT 24
5887#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
5888#define DDL_PLANE_SHIFT 0
5889#define DDL_PRECISION_HIGH (1 << 7)
5890#define DDL_PRECISION_LOW (0 << 7)
5891#define DRAIN_LATENCY_MASK 0x7f
5892
5893#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
5894#define CBR_PND_DEADLINE_DISABLE (1 << 31)
5895#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
5896
5897#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
5898#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11))
5899
5900
5901#define G4X_FIFO_LINE_SIZE 64
5902#define I915_FIFO_LINE_SIZE 64
5903#define I830_FIFO_LINE_SIZE 32
5904
5905#define VALLEYVIEW_FIFO_SIZE 255
5906#define G4X_FIFO_SIZE 127
5907#define I965_FIFO_SIZE 512
5908#define I945_FIFO_SIZE 127
5909#define I915_FIFO_SIZE 95
5910#define I855GM_FIFO_SIZE 127
5911#define I830_FIFO_SIZE 95
5912
5913#define VALLEYVIEW_MAX_WM 0xff
5914#define G4X_MAX_WM 0x3f
5915#define I915_MAX_WM 0x3f
5916
5917#define PINEVIEW_DISPLAY_FIFO 512
5918#define PINEVIEW_FIFO_LINE_SIZE 64
5919#define PINEVIEW_MAX_WM 0x1ff
5920#define PINEVIEW_DFT_WM 0x3f
5921#define PINEVIEW_DFT_HPLLOFF_WM 0
5922#define PINEVIEW_GUARD_WM 10
5923#define PINEVIEW_CURSOR_FIFO 64
5924#define PINEVIEW_CURSOR_MAX_WM 0x3f
5925#define PINEVIEW_CURSOR_DFT_WM 0
5926#define PINEVIEW_CURSOR_GUARD_WM 5
5927
5928#define VALLEYVIEW_CURSOR_MAX_WM 64
5929#define I965_CURSOR_FIFO 64
5930#define I965_CURSOR_MAX_WM 32
5931#define I965_CURSOR_DFT_WM 8
5932
5933
5934#define _CUR_WM_A_0 0x70140
5935#define _CUR_WM_B_0 0x71140
5936#define _PLANE_WM_1_A_0 0x70240
5937#define _PLANE_WM_1_B_0 0x71240
5938#define _PLANE_WM_2_A_0 0x70340
5939#define _PLANE_WM_2_B_0 0x71340
5940#define _PLANE_WM_TRANS_1_A_0 0x70268
5941#define _PLANE_WM_TRANS_1_B_0 0x71268
5942#define _PLANE_WM_TRANS_2_A_0 0x70368
5943#define _PLANE_WM_TRANS_2_B_0 0x71368
5944#define _CUR_WM_TRANS_A_0 0x70168
5945#define _CUR_WM_TRANS_B_0 0x71168
5946#define PLANE_WM_EN (1 << 31)
5947#define PLANE_WM_LINES_SHIFT 14
5948#define PLANE_WM_LINES_MASK 0x1f
5949#define PLANE_WM_BLOCKS_MASK 0x3ff
5950
5951#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
5952#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
5953#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
5954
5955#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
5956#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
5957#define _PLANE_WM_BASE(pipe, plane) \
5958 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
5959#define PLANE_WM(pipe, plane, level) \
5960 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
5961#define _PLANE_WM_TRANS_1(pipe) \
5962 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
5963#define _PLANE_WM_TRANS_2(pipe) \
5964 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
5965#define PLANE_WM_TRANS(pipe, plane) \
5966 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
5967
5968
5969#define WM0_PIPEA_ILK _MMIO(0x45100)
5970#define WM0_PIPE_PLANE_MASK (0xffff << 16)
5971#define WM0_PIPE_PLANE_SHIFT 16
5972#define WM0_PIPE_SPRITE_MASK (0xff << 8)
5973#define WM0_PIPE_SPRITE_SHIFT 8
5974#define WM0_PIPE_CURSOR_MASK (0xff)
5975
5976#define WM0_PIPEB_ILK _MMIO(0x45104)
5977#define WM0_PIPEC_IVB _MMIO(0x45200)
5978#define WM1_LP_ILK _MMIO(0x45108)
5979#define WM1_LP_SR_EN (1 << 31)
5980#define WM1_LP_LATENCY_SHIFT 24
5981#define WM1_LP_LATENCY_MASK (0x7f << 24)
5982#define WM1_LP_FBC_MASK (0xf << 20)
5983#define WM1_LP_FBC_SHIFT 20
5984#define WM1_LP_FBC_SHIFT_BDW 19
5985#define WM1_LP_SR_MASK (0x7ff << 8)
5986#define WM1_LP_SR_SHIFT 8
5987#define WM1_LP_CURSOR_MASK (0xff)
5988#define WM2_LP_ILK _MMIO(0x4510c)
5989#define WM2_LP_EN (1 << 31)
5990#define WM3_LP_ILK _MMIO(0x45110)
5991#define WM3_LP_EN (1 << 31)
5992#define WM1S_LP_ILK _MMIO(0x45120)
5993#define WM2S_LP_IVB _MMIO(0x45124)
5994#define WM3S_LP_IVB _MMIO(0x45128)
5995#define WM1S_LP_EN (1 << 31)
5996
5997#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
5998 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
5999 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6000
6001
6002#define MLTR_ILK _MMIO(0x11222)
6003#define MLTR_WM1_SHIFT 0
6004#define MLTR_WM2_SHIFT 8
6005
6006#define ILK_SRLT_MASK 0x3f
6007
6008
6009
6010#define SSKPD _MMIO(0x5d10)
6011#define SSKPD_WM_MASK 0x3f
6012#define SSKPD_WM0_SHIFT 0
6013#define SSKPD_WM1_SHIFT 8
6014#define SSKPD_WM2_SHIFT 16
6015#define SSKPD_WM3_SHIFT 24
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032#define _PIPEAFRAMEHIGH 0x70040
6033#define PIPE_FRAME_HIGH_MASK 0x0000ffff
6034#define PIPE_FRAME_HIGH_SHIFT 0
6035#define _PIPEAFRAMEPIXEL 0x70044
6036#define PIPE_FRAME_LOW_MASK 0xff000000
6037#define PIPE_FRAME_LOW_SHIFT 24
6038#define PIPE_PIXEL_MASK 0x00ffffff
6039#define PIPE_PIXEL_SHIFT 0
6040
6041#define _PIPEA_FRMCOUNT_G4X 0x70040
6042#define _PIPEA_FLIPCOUNT_G4X 0x70044
6043#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6044#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6045
6046
6047#define _CURACNTR 0x70080
6048
6049#define CURSOR_ENABLE 0x80000000
6050#define CURSOR_GAMMA_ENABLE 0x40000000
6051#define CURSOR_STRIDE_SHIFT 28
6052#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT)
6053#define CURSOR_FORMAT_SHIFT 24
6054#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
6055#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
6056#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
6057#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
6058#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
6059#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
6060
6061#define MCURSOR_MODE 0x27
6062#define MCURSOR_MODE_DISABLE 0x00
6063#define MCURSOR_MODE_128_32B_AX 0x02
6064#define MCURSOR_MODE_256_32B_AX 0x03
6065#define MCURSOR_MODE_64_32B_AX 0x07
6066#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6067#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6068#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6069#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
6070#define MCURSOR_PIPE_SELECT_SHIFT 28
6071#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6072#define MCURSOR_GAMMA_ENABLE (1 << 26)
6073#define MCURSOR_PIPE_CSC_ENABLE (1 << 24)
6074#define MCURSOR_ROTATE_180 (1 << 15)
6075#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
6076#define _CURABASE 0x70084
6077#define _CURAPOS 0x70088
6078#define CURSOR_POS_MASK 0x007FF
6079#define CURSOR_POS_SIGN 0x8000
6080#define CURSOR_X_SHIFT 0
6081#define CURSOR_Y_SHIFT 16
6082#define CURSIZE _MMIO(0x700a0)
6083#define _CUR_FBC_CTL_A 0x700a0
6084#define CUR_FBC_CTL_EN (1 << 31)
6085#define _CURASURFLIVE 0x700ac
6086#define _CURBCNTR 0x700c0
6087#define _CURBBASE 0x700c4
6088#define _CURBPOS 0x700c8
6089
6090#define _CURBCNTR_IVB 0x71080
6091#define _CURBBASE_IVB 0x71084
6092#define _CURBPOS_IVB 0x71088
6093
6094#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
6095 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
6096 dev_priv->info.display_mmio_offset)
6097
6098#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6099#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6100#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6101#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6102#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6103
6104#define CURSOR_A_OFFSET 0x70080
6105#define CURSOR_B_OFFSET 0x700c0
6106#define CHV_CURSOR_C_OFFSET 0x700e0
6107#define IVB_CURSOR_B_OFFSET 0x71080
6108#define IVB_CURSOR_C_OFFSET 0x72080
6109
6110
6111#define _DSPACNTR 0x70180
6112#define DISPLAY_PLANE_ENABLE (1 << 31)
6113#define DISPLAY_PLANE_DISABLE 0
6114#define DISPPLANE_GAMMA_ENABLE (1 << 30)
6115#define DISPPLANE_GAMMA_DISABLE 0
6116#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
6117#define DISPPLANE_YUV422 (0x0 << 26)
6118#define DISPPLANE_8BPP (0x2 << 26)
6119#define DISPPLANE_BGRA555 (0x3 << 26)
6120#define DISPPLANE_BGRX555 (0x4 << 26)
6121#define DISPPLANE_BGRX565 (0x5 << 26)
6122#define DISPPLANE_BGRX888 (0x6 << 26)
6123#define DISPPLANE_BGRA888 (0x7 << 26)
6124#define DISPPLANE_RGBX101010 (0x8 << 26)
6125#define DISPPLANE_RGBA101010 (0x9 << 26)
6126#define DISPPLANE_BGRX101010 (0xa << 26)
6127#define DISPPLANE_RGBX161616 (0xc << 26)
6128#define DISPPLANE_RGBX888 (0xe << 26)
6129#define DISPPLANE_RGBA888 (0xf << 26)
6130#define DISPPLANE_STEREO_ENABLE (1 << 25)
6131#define DISPPLANE_STEREO_DISABLE 0
6132#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24)
6133#define DISPPLANE_SEL_PIPE_SHIFT 24
6134#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6135#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6136#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
6137#define DISPPLANE_SRC_KEY_DISABLE 0
6138#define DISPPLANE_LINE_DOUBLE (1 << 20)
6139#define DISPPLANE_NO_LINE_DOUBLE 0
6140#define DISPPLANE_STEREO_POLARITY_FIRST 0
6141#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
6142#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16)
6143#define DISPPLANE_ROTATE_180 (1 << 15)
6144#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14)
6145#define DISPPLANE_TILED (1 << 10)
6146#define DISPPLANE_MIRROR (1 << 8)
6147#define _DSPAADDR 0x70184
6148#define _DSPASTRIDE 0x70188
6149#define _DSPAPOS 0x7018C
6150#define _DSPASIZE 0x70190
6151#define _DSPASURF 0x7019C
6152#define _DSPATILEOFF 0x701A4
6153#define _DSPAOFFSET 0x701A4
6154#define _DSPASURFLIVE 0x701AC
6155
6156#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6157#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6158#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6159#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6160#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6161#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6162#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6163#define DSPLINOFF(plane) DSPADDR(plane)
6164#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6165#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6166
6167
6168#define _CHV_BLEND_A 0x60a00
6169#define CHV_BLEND_LEGACY (0 << 30)
6170#define CHV_BLEND_ANDROID (1 << 30)
6171#define CHV_BLEND_MPO (2 << 30)
6172#define CHV_BLEND_MASK (3 << 30)
6173#define _CHV_CANVAS_A 0x60a04
6174#define _PRIMPOS_A 0x60a08
6175#define _PRIMSIZE_A 0x60a0c
6176#define _PRIMCNSTALPHA_A 0x60a10
6177#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
6178
6179#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6180#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6181#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6182#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6183#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6184
6185
6186#define DISP_BASEADDR_MASK (0xfffff000)
6187#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
6188#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
6202#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
6203#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
6204#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6205
6206
6207#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
6208#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
6209#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
6210#define _PIPEBFRAMEHIGH 0x71040
6211#define _PIPEBFRAMEPIXEL 0x71044
6212#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
6213#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
6214
6215
6216
6217#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
6218#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
6219#define DISPPLANE_ALPHA_TRANS_DISABLE 0
6220#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6221#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6222#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
6223#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
6224#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
6225#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
6226#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
6227#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
6228#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
6229#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
6230
6231
6232#define _DVSACNTR 0x72180
6233#define DVS_ENABLE (1 << 31)
6234#define DVS_GAMMA_ENABLE (1 << 30)
6235#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
6236#define DVS_PIXFORMAT_MASK (3 << 25)
6237#define DVS_FORMAT_YUV422 (0 << 25)
6238#define DVS_FORMAT_RGBX101010 (1 << 25)
6239#define DVS_FORMAT_RGBX888 (2 << 25)
6240#define DVS_FORMAT_RGBX161616 (3 << 25)
6241#define DVS_PIPE_CSC_ENABLE (1 << 24)
6242#define DVS_SOURCE_KEY (1 << 22)
6243#define DVS_RGB_ORDER_XBGR (1 << 20)
6244#define DVS_YUV_FORMAT_BT709 (1 << 18)
6245#define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6246#define DVS_YUV_ORDER_YUYV (0 << 16)
6247#define DVS_YUV_ORDER_UYVY (1 << 16)
6248#define DVS_YUV_ORDER_YVYU (2 << 16)
6249#define DVS_YUV_ORDER_VYUY (3 << 16)
6250#define DVS_ROTATE_180 (1 << 15)
6251#define DVS_DEST_KEY (1 << 2)
6252#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
6253#define DVS_TILED (1 << 10)
6254#define _DVSALINOFF 0x72184
6255#define _DVSASTRIDE 0x72188
6256#define _DVSAPOS 0x7218c
6257#define _DVSASIZE 0x72190
6258#define _DVSAKEYVAL 0x72194
6259#define _DVSAKEYMSK 0x72198
6260#define _DVSASURF 0x7219c
6261#define _DVSAKEYMAXVAL 0x721a0
6262#define _DVSATILEOFF 0x721a4
6263#define _DVSASURFLIVE 0x721ac
6264#define _DVSASCALE 0x72204
6265#define DVS_SCALE_ENABLE (1 << 31)
6266#define DVS_FILTER_MASK (3 << 29)
6267#define DVS_FILTER_MEDIUM (0 << 29)
6268#define DVS_FILTER_ENHANCING (1 << 29)
6269#define DVS_FILTER_SOFTENING (2 << 29)
6270#define DVS_VERTICAL_OFFSET_HALF (1 << 28)
6271#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6272#define _DVSAGAMC 0x72300
6273
6274#define _DVSBCNTR 0x73180
6275#define _DVSBLINOFF 0x73184
6276#define _DVSBSTRIDE 0x73188
6277#define _DVSBPOS 0x7318c
6278#define _DVSBSIZE 0x73190
6279#define _DVSBKEYVAL 0x73194
6280#define _DVSBKEYMSK 0x73198
6281#define _DVSBSURF 0x7319c
6282#define _DVSBKEYMAXVAL 0x731a0
6283#define _DVSBTILEOFF 0x731a4
6284#define _DVSBSURFLIVE 0x731ac
6285#define _DVSBSCALE 0x73204
6286#define _DVSBGAMC 0x73300
6287
6288#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6289#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6290#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6291#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6292#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6293#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6294#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6295#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6296#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6297#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6298#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6299#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6300
6301#define _SPRA_CTL 0x70280
6302#define SPRITE_ENABLE (1 << 31)
6303#define SPRITE_GAMMA_ENABLE (1 << 30)
6304#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6305#define SPRITE_PIXFORMAT_MASK (7 << 25)
6306#define SPRITE_FORMAT_YUV422 (0 << 25)
6307#define SPRITE_FORMAT_RGBX101010 (1 << 25)
6308#define SPRITE_FORMAT_RGBX888 (2 << 25)
6309#define SPRITE_FORMAT_RGBX161616 (3 << 25)
6310#define SPRITE_FORMAT_YUV444 (4 << 25)
6311#define SPRITE_FORMAT_XR_BGR101010 (5 << 25)
6312#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
6313#define SPRITE_SOURCE_KEY (1 << 22)
6314#define SPRITE_RGB_ORDER_RGBX (1 << 20)
6315#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
6316#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6317#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
6318#define SPRITE_YUV_ORDER_YUYV (0 << 16)
6319#define SPRITE_YUV_ORDER_UYVY (1 << 16)
6320#define SPRITE_YUV_ORDER_YVYU (2 << 16)
6321#define SPRITE_YUV_ORDER_VYUY (3 << 16)
6322#define SPRITE_ROTATE_180 (1 << 15)
6323#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
6324#define SPRITE_INT_GAMMA_ENABLE (1 << 13)
6325#define SPRITE_TILED (1 << 10)
6326#define SPRITE_DEST_KEY (1 << 2)
6327#define _SPRA_LINOFF 0x70284
6328#define _SPRA_STRIDE 0x70288
6329#define _SPRA_POS 0x7028c
6330#define _SPRA_SIZE 0x70290
6331#define _SPRA_KEYVAL 0x70294
6332#define _SPRA_KEYMSK 0x70298
6333#define _SPRA_SURF 0x7029c
6334#define _SPRA_KEYMAX 0x702a0
6335#define _SPRA_TILEOFF 0x702a4
6336#define _SPRA_OFFSET 0x702a4
6337#define _SPRA_SURFLIVE 0x702ac
6338#define _SPRA_SCALE 0x70304
6339#define SPRITE_SCALE_ENABLE (1 << 31)
6340#define SPRITE_FILTER_MASK (3 << 29)
6341#define SPRITE_FILTER_MEDIUM (0 << 29)
6342#define SPRITE_FILTER_ENHANCING (1 << 29)
6343#define SPRITE_FILTER_SOFTENING (2 << 29)
6344#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28)
6345#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
6346#define _SPRA_GAMC 0x70400
6347
6348#define _SPRB_CTL 0x71280
6349#define _SPRB_LINOFF 0x71284
6350#define _SPRB_STRIDE 0x71288
6351#define _SPRB_POS 0x7128c
6352#define _SPRB_SIZE 0x71290
6353#define _SPRB_KEYVAL 0x71294
6354#define _SPRB_KEYMSK 0x71298
6355#define _SPRB_SURF 0x7129c
6356#define _SPRB_KEYMAX 0x712a0
6357#define _SPRB_TILEOFF 0x712a4
6358#define _SPRB_OFFSET 0x712a4
6359#define _SPRB_SURFLIVE 0x712ac
6360#define _SPRB_SCALE 0x71304
6361#define _SPRB_GAMC 0x71400
6362
6363#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6364#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6365#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6366#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6367#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6368#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6369#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6370#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6371#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6372#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6373#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6374#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6375#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
6376#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6377
6378#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6379#define SP_ENABLE (1 << 31)
6380#define SP_GAMMA_ENABLE (1 << 30)
6381#define SP_PIXFORMAT_MASK (0xf << 26)
6382#define SP_FORMAT_YUV422 (0 << 26)
6383#define SP_FORMAT_BGR565 (5 << 26)
6384#define SP_FORMAT_BGRX8888 (6 << 26)
6385#define SP_FORMAT_BGRA8888 (7 << 26)
6386#define SP_FORMAT_RGBX1010102 (8 << 26)
6387#define SP_FORMAT_RGBA1010102 (9 << 26)
6388#define SP_FORMAT_RGBX8888 (0xe << 26)
6389#define SP_FORMAT_RGBA8888 (0xf << 26)
6390#define SP_ALPHA_PREMULTIPLY (1 << 23)
6391#define SP_SOURCE_KEY (1 << 22)
6392#define SP_YUV_FORMAT_BT709 (1 << 18)
6393#define SP_YUV_BYTE_ORDER_MASK (3 << 16)
6394#define SP_YUV_ORDER_YUYV (0 << 16)
6395#define SP_YUV_ORDER_UYVY (1 << 16)
6396#define SP_YUV_ORDER_YVYU (2 << 16)
6397#define SP_YUV_ORDER_VYUY (3 << 16)
6398#define SP_ROTATE_180 (1 << 15)
6399#define SP_TILED (1 << 10)
6400#define SP_MIRROR (1 << 8)
6401#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6402#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6403#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6404#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6405#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6406#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6407#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6408#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6409#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6410#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6411#define SP_CONST_ALPHA_ENABLE (1 << 31)
6412#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
6413#define SP_CONTRAST(x) ((x) << 18)
6414#define SP_BRIGHTNESS(x) ((x) & 0xff)
6415#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6416#define SP_SH_SIN(x) (((x) & 0x7ff) << 16)
6417#define SP_SH_COS(x) (x)
6418#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
6419
6420#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6421#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6422#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6423#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6424#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6425#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6426#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6427#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6428#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6429#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6430#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6431#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6432#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6433#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
6434
6435#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6436 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6437
6438#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6439#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6440#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6441#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6442#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6443#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6444#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6445#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6446#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6447#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6448#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6449#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6450#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6451#define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
6452
6453
6454
6455
6456
6457
6458
6459
6460#define _MMIO_CHV_SPCSC(plane_id, reg) \
6461 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6462
6463#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6464#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6465#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6466#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16)
6467#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0)
6468
6469#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6470#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6471#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6472#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6473#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6474#define SPCSC_C1(x) (((x) & 0x7fff) << 16)
6475#define SPCSC_C0(x) (((x) & 0x7fff) << 0)
6476
6477#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6478#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6479#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6480#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16)
6481#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0)
6482
6483#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6484#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6485#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6486#define SPCSC_OMAX(x) ((x) << 16)
6487#define SPCSC_OMIN(x) ((x) << 0)
6488
6489
6490
6491#define _PLANE_CTL_1_A 0x70180
6492#define _PLANE_CTL_2_A 0x70280
6493#define _PLANE_CTL_3_A 0x70380
6494#define PLANE_CTL_ENABLE (1 << 31)
6495#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
6496#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6497
6498
6499
6500
6501
6502#define PLANE_CTL_FORMAT_MASK (0xf << 24)
6503#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
6504#define PLANE_CTL_FORMAT_NV12 (1 << 24)
6505#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
6506#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
6507#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
6508#define PLANE_CTL_FORMAT_AYUV (8 << 24)
6509#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
6510#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
6511#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
6512#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
6513#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6514#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
6515#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
6516#define PLANE_CTL_ORDER_BGRX (0 << 20)
6517#define PLANE_CTL_ORDER_RGBX (1 << 20)
6518#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6519#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6520#define PLANE_CTL_YUV422_YUYV (0 << 16)
6521#define PLANE_CTL_YUV422_UYVY (1 << 16)
6522#define PLANE_CTL_YUV422_YVYU (2 << 16)
6523#define PLANE_CTL_YUV422_VYUY (3 << 16)
6524#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
6525#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
6526#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
6527#define PLANE_CTL_TILED_MASK (0x7 << 10)
6528#define PLANE_CTL_TILED_LINEAR (0 << 10)
6529#define PLANE_CTL_TILED_X (1 << 10)
6530#define PLANE_CTL_TILED_Y (4 << 10)
6531#define PLANE_CTL_TILED_YF (5 << 10)
6532#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
6533#define PLANE_CTL_ALPHA_MASK (0x3 << 4)
6534#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
6535#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
6536#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
6537#define PLANE_CTL_ROTATE_MASK 0x3
6538#define PLANE_CTL_ROTATE_0 0x0
6539#define PLANE_CTL_ROTATE_90 0x1
6540#define PLANE_CTL_ROTATE_180 0x2
6541#define PLANE_CTL_ROTATE_270 0x3
6542#define _PLANE_STRIDE_1_A 0x70188
6543#define _PLANE_STRIDE_2_A 0x70288
6544#define _PLANE_STRIDE_3_A 0x70388
6545#define _PLANE_POS_1_A 0x7018c
6546#define _PLANE_POS_2_A 0x7028c
6547#define _PLANE_POS_3_A 0x7038c
6548#define _PLANE_SIZE_1_A 0x70190
6549#define _PLANE_SIZE_2_A 0x70290
6550#define _PLANE_SIZE_3_A 0x70390
6551#define _PLANE_SURF_1_A 0x7019c
6552#define _PLANE_SURF_2_A 0x7029c
6553#define _PLANE_SURF_3_A 0x7039c
6554#define _PLANE_OFFSET_1_A 0x701a4
6555#define _PLANE_OFFSET_2_A 0x702a4
6556#define _PLANE_OFFSET_3_A 0x703a4
6557#define _PLANE_KEYVAL_1_A 0x70194
6558#define _PLANE_KEYVAL_2_A 0x70294
6559#define _PLANE_KEYMSK_1_A 0x70198
6560#define _PLANE_KEYMSK_2_A 0x70298
6561#define _PLANE_KEYMAX_1_A 0x701a0
6562#define _PLANE_KEYMAX_2_A 0x702a0
6563#define _PLANE_AUX_DIST_1_A 0x701c0
6564#define _PLANE_AUX_DIST_2_A 0x702c0
6565#define _PLANE_AUX_OFFSET_1_A 0x701c4
6566#define _PLANE_AUX_OFFSET_2_A 0x702c4
6567#define _PLANE_COLOR_CTL_1_A 0x701CC
6568#define _PLANE_COLOR_CTL_2_A 0x702CC
6569#define _PLANE_COLOR_CTL_3_A 0x703CC
6570#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
6571#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6572#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
6573#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
6574#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
6575#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
6576#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
6577#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
6578#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
6579#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
6580#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
6581#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
6582#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
6583#define _PLANE_BUF_CFG_1_A 0x7027c
6584#define _PLANE_BUF_CFG_2_A 0x7037c
6585#define _PLANE_NV12_BUF_CFG_1_A 0x70278
6586#define _PLANE_NV12_BUF_CFG_2_A 0x70378
6587
6588
6589#define _PLANE_CTL_1_B 0x71180
6590#define _PLANE_CTL_2_B 0x71280
6591#define _PLANE_CTL_3_B 0x71380
6592#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6593#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6594#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6595#define PLANE_CTL(pipe, plane) \
6596 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6597
6598#define _PLANE_STRIDE_1_B 0x71188
6599#define _PLANE_STRIDE_2_B 0x71288
6600#define _PLANE_STRIDE_3_B 0x71388
6601#define _PLANE_STRIDE_1(pipe) \
6602 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6603#define _PLANE_STRIDE_2(pipe) \
6604 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6605#define _PLANE_STRIDE_3(pipe) \
6606 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6607#define PLANE_STRIDE(pipe, plane) \
6608 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6609
6610#define _PLANE_POS_1_B 0x7118c
6611#define _PLANE_POS_2_B 0x7128c
6612#define _PLANE_POS_3_B 0x7138c
6613#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6614#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6615#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6616#define PLANE_POS(pipe, plane) \
6617 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6618
6619#define _PLANE_SIZE_1_B 0x71190
6620#define _PLANE_SIZE_2_B 0x71290
6621#define _PLANE_SIZE_3_B 0x71390
6622#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6623#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6624#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6625#define PLANE_SIZE(pipe, plane) \
6626 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6627
6628#define _PLANE_SURF_1_B 0x7119c
6629#define _PLANE_SURF_2_B 0x7129c
6630#define _PLANE_SURF_3_B 0x7139c
6631#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6632#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6633#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6634#define PLANE_SURF(pipe, plane) \
6635 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6636
6637#define _PLANE_OFFSET_1_B 0x711a4
6638#define _PLANE_OFFSET_2_B 0x712a4
6639#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6640#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6641#define PLANE_OFFSET(pipe, plane) \
6642 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6643
6644#define _PLANE_KEYVAL_1_B 0x71194
6645#define _PLANE_KEYVAL_2_B 0x71294
6646#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6647#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6648#define PLANE_KEYVAL(pipe, plane) \
6649 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6650
6651#define _PLANE_KEYMSK_1_B 0x71198
6652#define _PLANE_KEYMSK_2_B 0x71298
6653#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6654#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6655#define PLANE_KEYMSK(pipe, plane) \
6656 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6657
6658#define _PLANE_KEYMAX_1_B 0x711a0
6659#define _PLANE_KEYMAX_2_B 0x712a0
6660#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6661#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6662#define PLANE_KEYMAX(pipe, plane) \
6663 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6664
6665#define _PLANE_BUF_CFG_1_B 0x7127c
6666#define _PLANE_BUF_CFG_2_B 0x7137c
6667#define SKL_DDB_ENTRY_MASK 0x3FF
6668#define ICL_DDB_ENTRY_MASK 0x7FF
6669#define DDB_ENTRY_END_SHIFT 16
6670#define _PLANE_BUF_CFG_1(pipe) \
6671 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6672#define _PLANE_BUF_CFG_2(pipe) \
6673 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6674#define PLANE_BUF_CFG(pipe, plane) \
6675 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6676
6677#define _PLANE_NV12_BUF_CFG_1_B 0x71278
6678#define _PLANE_NV12_BUF_CFG_2_B 0x71378
6679#define _PLANE_NV12_BUF_CFG_1(pipe) \
6680 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6681#define _PLANE_NV12_BUF_CFG_2(pipe) \
6682 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6683#define PLANE_NV12_BUF_CFG(pipe, plane) \
6684 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6685
6686#define _PLANE_AUX_DIST_1_B 0x711c0
6687#define _PLANE_AUX_DIST_2_B 0x712c0
6688#define _PLANE_AUX_DIST_1(pipe) \
6689 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6690#define _PLANE_AUX_DIST_2(pipe) \
6691 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6692#define PLANE_AUX_DIST(pipe, plane) \
6693 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6694
6695#define _PLANE_AUX_OFFSET_1_B 0x711c4
6696#define _PLANE_AUX_OFFSET_2_B 0x712c4
6697#define _PLANE_AUX_OFFSET_1(pipe) \
6698 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6699#define _PLANE_AUX_OFFSET_2(pipe) \
6700 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6701#define PLANE_AUX_OFFSET(pipe, plane) \
6702 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6703
6704#define _PLANE_COLOR_CTL_1_B 0x711CC
6705#define _PLANE_COLOR_CTL_2_B 0x712CC
6706#define _PLANE_COLOR_CTL_3_B 0x713CC
6707#define _PLANE_COLOR_CTL_1(pipe) \
6708 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6709#define _PLANE_COLOR_CTL_2(pipe) \
6710 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6711#define PLANE_COLOR_CTL(pipe, plane) \
6712 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6713
6714#
6715#define _CUR_BUF_CFG_A 0x7017c
6716#define _CUR_BUF_CFG_B 0x7117c
6717#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6718
6719
6720#define VGACNTRL _MMIO(0x71400)
6721# define VGA_DISP_DISABLE (1 << 31)
6722# define VGA_2X_MODE (1 << 30)
6723# define VGA_PIPE_B_SELECT (1 << 29)
6724
6725#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
6726
6727
6728
6729#define CPU_VGACNTRL _MMIO(0x41000)
6730
6731#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
6732#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
6733#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2)
6734#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2)
6735#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2)
6736#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2)
6737#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2)
6738#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
6739#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
6740#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
6741#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
6742
6743
6744#define RR_HW_CTL _MMIO(0x45300)
6745#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
6746#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
6747
6748#define FDI_PLL_BIOS_0 _MMIO(0x46000)
6749#define FDI_PLL_FB_CLOCK_MASK 0xff
6750#define FDI_PLL_BIOS_1 _MMIO(0x46004)
6751#define FDI_PLL_BIOS_2 _MMIO(0x46008)
6752#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
6753#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
6754#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
6755
6756#define PCH_3DCGDIS0 _MMIO(0x46020)
6757# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
6758# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
6759
6760#define PCH_3DCGDIS1 _MMIO(0x46024)
6761# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
6762
6763#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
6764#define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
6765#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
6766#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
6767
6768
6769#define _PIPEA_DATA_M1 0x60030
6770#define PIPE_DATA_M1_OFFSET 0
6771#define _PIPEA_DATA_N1 0x60034
6772#define PIPE_DATA_N1_OFFSET 0
6773
6774#define _PIPEA_DATA_M2 0x60038
6775#define PIPE_DATA_M2_OFFSET 0
6776#define _PIPEA_DATA_N2 0x6003c
6777#define PIPE_DATA_N2_OFFSET 0
6778
6779#define _PIPEA_LINK_M1 0x60040
6780#define PIPE_LINK_M1_OFFSET 0
6781#define _PIPEA_LINK_N1 0x60044
6782#define PIPE_LINK_N1_OFFSET 0
6783
6784#define _PIPEA_LINK_M2 0x60048
6785#define PIPE_LINK_M2_OFFSET 0
6786#define _PIPEA_LINK_N2 0x6004c
6787#define PIPE_LINK_N2_OFFSET 0
6788
6789
6790
6791#define _PIPEB_DATA_M1 0x61030
6792#define _PIPEB_DATA_N1 0x61034
6793#define _PIPEB_DATA_M2 0x61038
6794#define _PIPEB_DATA_N2 0x6103c
6795#define _PIPEB_LINK_M1 0x61040
6796#define _PIPEB_LINK_N1 0x61044
6797#define _PIPEB_LINK_M2 0x61048
6798#define _PIPEB_LINK_N2 0x6104c
6799
6800#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
6801#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
6802#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
6803#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
6804#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
6805#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
6806#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
6807#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
6808
6809
6810
6811#define _PFA_CTL_1 0x68080
6812#define _PFB_CTL_1 0x68880
6813#define PF_ENABLE (1 << 31)
6814#define PF_PIPE_SEL_MASK_IVB (3 << 29)
6815#define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
6816#define PF_FILTER_MASK (3 << 23)
6817#define PF_FILTER_PROGRAMMED (0 << 23)
6818#define PF_FILTER_MED_3x3 (1 << 23)
6819#define PF_FILTER_EDGE_ENHANCE (2 << 23)
6820#define PF_FILTER_EDGE_SOFTEN (3 << 23)
6821#define _PFA_WIN_SZ 0x68074
6822#define _PFB_WIN_SZ 0x68874
6823#define _PFA_WIN_POS 0x68070
6824#define _PFB_WIN_POS 0x68870
6825#define _PFA_VSCALE 0x68084
6826#define _PFB_VSCALE 0x68884
6827#define _PFA_HSCALE 0x68090
6828#define _PFB_HSCALE 0x68890
6829
6830#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
6831#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
6832#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
6833#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
6834#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
6835
6836#define _PSA_CTL 0x68180
6837#define _PSB_CTL 0x68980
6838#define PS_ENABLE (1 << 31)
6839#define _PSA_WIN_SZ 0x68174
6840#define _PSB_WIN_SZ 0x68974
6841#define _PSA_WIN_POS 0x68170
6842#define _PSB_WIN_POS 0x68970
6843
6844#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
6845#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
6846#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
6847
6848
6849
6850
6851#define _PS_1A_CTRL 0x68180
6852#define _PS_2A_CTRL 0x68280
6853#define _PS_1B_CTRL 0x68980
6854#define _PS_2B_CTRL 0x68A80
6855#define _PS_1C_CTRL 0x69180
6856#define PS_SCALER_EN (1 << 31)
6857#define PS_SCALER_MODE_MASK (3 << 28)
6858#define PS_SCALER_MODE_DYN (0 << 28)
6859#define PS_SCALER_MODE_HQ (1 << 28)
6860#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
6861#define PS_SCALER_MODE_PLANAR (1 << 29)
6862#define PS_PLANE_SEL_MASK (7 << 25)
6863#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
6864#define PS_FILTER_MASK (3 << 23)
6865#define PS_FILTER_MEDIUM (0 << 23)
6866#define PS_FILTER_EDGE_ENHANCE (2 << 23)
6867#define PS_FILTER_BILINEAR (3 << 23)
6868#define PS_VERT3TAP (1 << 21)
6869#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
6870#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
6871#define PS_PWRUP_PROGRESS (1 << 17)
6872#define PS_V_FILTER_BYPASS (1 << 8)
6873#define PS_VADAPT_EN (1 << 7)
6874#define PS_VADAPT_MODE_MASK (3 << 5)
6875#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
6876#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
6877#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
6878
6879#define _PS_PWR_GATE_1A 0x68160
6880#define _PS_PWR_GATE_2A 0x68260
6881#define _PS_PWR_GATE_1B 0x68960
6882#define _PS_PWR_GATE_2B 0x68A60
6883#define _PS_PWR_GATE_1C 0x69160
6884#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
6885#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
6886#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
6887#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
6888#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
6889#define PS_PWR_GATE_SLPEN_8 0
6890#define PS_PWR_GATE_SLPEN_16 1
6891#define PS_PWR_GATE_SLPEN_24 2
6892#define PS_PWR_GATE_SLPEN_32 3
6893
6894#define _PS_WIN_POS_1A 0x68170
6895#define _PS_WIN_POS_2A 0x68270
6896#define _PS_WIN_POS_1B 0x68970
6897#define _PS_WIN_POS_2B 0x68A70
6898#define _PS_WIN_POS_1C 0x69170
6899
6900#define _PS_WIN_SZ_1A 0x68174
6901#define _PS_WIN_SZ_2A 0x68274
6902#define _PS_WIN_SZ_1B 0x68974
6903#define _PS_WIN_SZ_2B 0x68A74
6904#define _PS_WIN_SZ_1C 0x69174
6905
6906#define _PS_VSCALE_1A 0x68184
6907#define _PS_VSCALE_2A 0x68284
6908#define _PS_VSCALE_1B 0x68984
6909#define _PS_VSCALE_2B 0x68A84
6910#define _PS_VSCALE_1C 0x69184
6911
6912#define _PS_HSCALE_1A 0x68190
6913#define _PS_HSCALE_2A 0x68290
6914#define _PS_HSCALE_1B 0x68990
6915#define _PS_HSCALE_2B 0x68A90
6916#define _PS_HSCALE_1C 0x69190
6917
6918#define _PS_VPHASE_1A 0x68188
6919#define _PS_VPHASE_2A 0x68288
6920#define _PS_VPHASE_1B 0x68988
6921#define _PS_VPHASE_2B 0x68A88
6922#define _PS_VPHASE_1C 0x69188
6923#define PS_Y_PHASE(x) ((x) << 16)
6924#define PS_UV_RGB_PHASE(x) ((x) << 0)
6925#define PS_PHASE_MASK (0x7fff << 1)
6926#define PS_PHASE_TRIP (1 << 0)
6927
6928#define _PS_HPHASE_1A 0x68194
6929#define _PS_HPHASE_2A 0x68294
6930#define _PS_HPHASE_1B 0x68994
6931#define _PS_HPHASE_2B 0x68A94
6932#define _PS_HPHASE_1C 0x69194
6933
6934#define _PS_ECC_STAT_1A 0x681D0
6935#define _PS_ECC_STAT_2A 0x682D0
6936#define _PS_ECC_STAT_1B 0x689D0
6937#define _PS_ECC_STAT_2B 0x68AD0
6938#define _PS_ECC_STAT_1C 0x691D0
6939
6940#define _ID(id, a, b) _PICK_EVEN(id, a, b)
6941#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
6942 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
6943 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
6944#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
6945 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
6946 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
6947#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
6948 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
6949 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
6950#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
6951 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
6952 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
6953#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
6954 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
6955 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
6956#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
6957 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
6958 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
6959#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
6960 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
6961 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
6962#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
6963 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
6964 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
6965#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
6966 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
6967 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
6968
6969
6970#define _LGC_PALETTE_A 0x4a000
6971#define _LGC_PALETTE_B 0x4a800
6972#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
6973
6974#define _GAMMA_MODE_A 0x4a480
6975#define _GAMMA_MODE_B 0x4ac80
6976#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
6977#define GAMMA_MODE_MODE_MASK (3 << 0)
6978#define GAMMA_MODE_MODE_8BIT (0 << 0)
6979#define GAMMA_MODE_MODE_10BIT (1 << 0)
6980#define GAMMA_MODE_MODE_12BIT (2 << 0)
6981#define GAMMA_MODE_MODE_SPLIT (3 << 0)
6982
6983
6984#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
6985#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
6986#define CSR_HTP_ADDR_SKL 0x00500034
6987#define CSR_SSP_BASE _MMIO(0x8F074)
6988#define CSR_HTP_SKL _MMIO(0x8F004)
6989#define CSR_LAST_WRITE _MMIO(0x8F034)
6990#define CSR_LAST_WRITE_VALUE 0xc003b400
6991
6992#define CSR_MMIO_START_RANGE 0x80000
6993#define CSR_MMIO_END_RANGE 0x8FFFF
6994#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
6995#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
6996#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
6997
6998
6999#define DE_MASTER_IRQ_CONTROL (1 << 31)
7000#define DE_SPRITEB_FLIP_DONE (1 << 29)
7001#define DE_SPRITEA_FLIP_DONE (1 << 28)
7002#define DE_PLANEB_FLIP_DONE (1 << 27)
7003#define DE_PLANEA_FLIP_DONE (1 << 26)
7004#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7005#define DE_PCU_EVENT (1 << 25)
7006#define DE_GTT_FAULT (1 << 24)
7007#define DE_POISON (1 << 23)
7008#define DE_PERFORM_COUNTER (1 << 22)
7009#define DE_PCH_EVENT (1 << 21)
7010#define DE_AUX_CHANNEL_A (1 << 20)
7011#define DE_DP_A_HOTPLUG (1 << 19)
7012#define DE_GSE (1 << 18)
7013#define DE_PIPEB_VBLANK (1 << 15)
7014#define DE_PIPEB_EVEN_FIELD (1 << 14)
7015#define DE_PIPEB_ODD_FIELD (1 << 13)
7016#define DE_PIPEB_LINE_COMPARE (1 << 12)
7017#define DE_PIPEB_VSYNC (1 << 11)
7018#define DE_PIPEB_CRC_DONE (1 << 10)
7019#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
7020#define DE_PIPEA_VBLANK (1 << 7)
7021#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
7022#define DE_PIPEA_EVEN_FIELD (1 << 6)
7023#define DE_PIPEA_ODD_FIELD (1 << 5)
7024#define DE_PIPEA_LINE_COMPARE (1 << 4)
7025#define DE_PIPEA_VSYNC (1 << 3)
7026#define DE_PIPEA_CRC_DONE (1 << 2)
7027#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
7028#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
7029#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
7030
7031
7032#define DE_ERR_INT_IVB (1 << 30)
7033#define DE_GSE_IVB (1 << 29)
7034#define DE_PCH_EVENT_IVB (1 << 28)
7035#define DE_DP_A_HOTPLUG_IVB (1 << 27)
7036#define DE_AUX_CHANNEL_A_IVB (1 << 26)
7037#define DE_EDP_PSR_INT_HSW (1 << 19)
7038#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
7039#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
7040#define DE_PIPEC_VBLANK_IVB (1 << 10)
7041#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
7042#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
7043#define DE_PIPEB_VBLANK_IVB (1 << 5)
7044#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
7045#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
7046#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
7047#define DE_PIPEA_VBLANK_IVB (1 << 0)
7048#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
7049
7050#define VLV_MASTER_IER _MMIO(0x4400c)
7051#define MASTER_INTERRUPT_ENABLE (1 << 31)
7052
7053#define DEISR _MMIO(0x44000)
7054#define DEIMR _MMIO(0x44004)
7055#define DEIIR _MMIO(0x44008)
7056#define DEIER _MMIO(0x4400c)
7057
7058#define GTISR _MMIO(0x44010)
7059#define GTIMR _MMIO(0x44014)
7060#define GTIIR _MMIO(0x44018)
7061#define GTIER _MMIO(0x4401c)
7062
7063#define GEN8_MASTER_IRQ _MMIO(0x44200)
7064#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
7065#define GEN8_PCU_IRQ (1 << 30)
7066#define GEN8_DE_PCH_IRQ (1 << 23)
7067#define GEN8_DE_MISC_IRQ (1 << 22)
7068#define GEN8_DE_PORT_IRQ (1 << 20)
7069#define GEN8_DE_PIPE_C_IRQ (1 << 18)
7070#define GEN8_DE_PIPE_B_IRQ (1 << 17)
7071#define GEN8_DE_PIPE_A_IRQ (1 << 16)
7072#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
7073#define GEN8_GT_VECS_IRQ (1 << 6)
7074#define GEN8_GT_GUC_IRQ (1 << 5)
7075#define GEN8_GT_PM_IRQ (1 << 4)
7076#define GEN8_GT_VCS2_IRQ (1 << 3)
7077#define GEN8_GT_VCS1_IRQ (1 << 2)
7078#define GEN8_GT_BCS_IRQ (1 << 1)
7079#define GEN8_GT_RCS_IRQ (1 << 0)
7080
7081#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7082#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7083#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7084#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7085
7086#define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31)
7087#define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30)
7088#define GEN9_GUC_DISPLAY_EVENT (1 << 29)
7089#define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28)
7090#define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27)
7091#define GEN9_GUC_DB_RING_EVENT (1 << 26)
7092#define GEN9_GUC_DMA_DONE_EVENT (1 << 25)
7093#define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24)
7094#define GEN9_GUC_NOTIFICATION_EVENT (1 << 23)
7095
7096#define GEN8_RCS_IRQ_SHIFT 0
7097#define GEN8_BCS_IRQ_SHIFT 16
7098#define GEN8_VCS1_IRQ_SHIFT 0
7099#define GEN8_VCS2_IRQ_SHIFT 16
7100#define GEN8_VECS_IRQ_SHIFT 0
7101#define GEN8_WD_IRQ_SHIFT 16
7102
7103#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7104#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7105#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7106#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7107#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
7108#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
7109#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
7110#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
7111#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
7112#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
7113#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
7114#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
7115#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
7116#define GEN8_PIPE_VSYNC (1 << 1)
7117#define GEN8_PIPE_VBLANK (1 << 0)
7118#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
7119#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
7120#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
7121#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
7122#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
7123#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
7124#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
7125#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
7126#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
7127#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
7128#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7129 (GEN8_PIPE_CURSOR_FAULT | \
7130 GEN8_PIPE_SPRITE_FAULT | \
7131 GEN8_PIPE_PRIMARY_FAULT)
7132#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7133 (GEN9_PIPE_CURSOR_FAULT | \
7134 GEN9_PIPE_PLANE4_FAULT | \
7135 GEN9_PIPE_PLANE3_FAULT | \
7136 GEN9_PIPE_PLANE2_FAULT | \
7137 GEN9_PIPE_PLANE1_FAULT)
7138
7139#define GEN8_DE_PORT_ISR _MMIO(0x44440)
7140#define GEN8_DE_PORT_IMR _MMIO(0x44444)
7141#define GEN8_DE_PORT_IIR _MMIO(0x44448)
7142#define GEN8_DE_PORT_IER _MMIO(0x4444c)
7143#define ICL_AUX_CHANNEL_E (1 << 29)
7144#define CNL_AUX_CHANNEL_F (1 << 28)
7145#define GEN9_AUX_CHANNEL_D (1 << 27)
7146#define GEN9_AUX_CHANNEL_C (1 << 26)
7147#define GEN9_AUX_CHANNEL_B (1 << 25)
7148#define BXT_DE_PORT_HP_DDIC (1 << 5)
7149#define BXT_DE_PORT_HP_DDIB (1 << 4)
7150#define BXT_DE_PORT_HP_DDIA (1 << 3)
7151#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
7152 BXT_DE_PORT_HP_DDIB | \
7153 BXT_DE_PORT_HP_DDIC)
7154#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
7155#define BXT_DE_PORT_GMBUS (1 << 1)
7156#define GEN8_AUX_CHANNEL_A (1 << 0)
7157
7158#define GEN8_DE_MISC_ISR _MMIO(0x44460)
7159#define GEN8_DE_MISC_IMR _MMIO(0x44464)
7160#define GEN8_DE_MISC_IIR _MMIO(0x44468)
7161#define GEN8_DE_MISC_IER _MMIO(0x4446c)
7162#define GEN8_DE_MISC_GSE (1 << 27)
7163#define GEN8_DE_EDP_PSR (1 << 19)
7164
7165#define GEN8_PCU_ISR _MMIO(0x444e0)
7166#define GEN8_PCU_IMR _MMIO(0x444e4)
7167#define GEN8_PCU_IIR _MMIO(0x444e8)
7168#define GEN8_PCU_IER _MMIO(0x444ec)
7169
7170#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
7171#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
7172#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
7173#define GEN11_GU_MISC_IER _MMIO(0x444fc)
7174#define GEN11_GU_MISC_GSE (1 << 27)
7175
7176#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
7177#define GEN11_MASTER_IRQ (1 << 31)
7178#define GEN11_PCU_IRQ (1 << 30)
7179#define GEN11_GU_MISC_IRQ (1 << 29)
7180#define GEN11_DISPLAY_IRQ (1 << 16)
7181#define GEN11_GT_DW_IRQ(x) (1 << (x))
7182#define GEN11_GT_DW1_IRQ (1 << 1)
7183#define GEN11_GT_DW0_IRQ (1 << 0)
7184
7185#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7186#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7187#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
7188#define GEN11_DE_PCH_IRQ (1 << 23)
7189#define GEN11_DE_MISC_IRQ (1 << 22)
7190#define GEN11_DE_HPD_IRQ (1 << 21)
7191#define GEN11_DE_PORT_IRQ (1 << 20)
7192#define GEN11_DE_PIPE_C (1 << 18)
7193#define GEN11_DE_PIPE_B (1 << 17)
7194#define GEN11_DE_PIPE_A (1 << 16)
7195
7196#define GEN11_DE_HPD_ISR _MMIO(0x44470)
7197#define GEN11_DE_HPD_IMR _MMIO(0x44474)
7198#define GEN11_DE_HPD_IIR _MMIO(0x44478)
7199#define GEN11_DE_HPD_IER _MMIO(0x4447c)
7200#define GEN11_TC4_HOTPLUG (1 << 19)
7201#define GEN11_TC3_HOTPLUG (1 << 18)
7202#define GEN11_TC2_HOTPLUG (1 << 17)
7203#define GEN11_TC1_HOTPLUG (1 << 16)
7204#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
7205#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
7206 GEN11_TC3_HOTPLUG | \
7207 GEN11_TC2_HOTPLUG | \
7208 GEN11_TC1_HOTPLUG)
7209#define GEN11_TBT4_HOTPLUG (1 << 3)
7210#define GEN11_TBT3_HOTPLUG (1 << 2)
7211#define GEN11_TBT2_HOTPLUG (1 << 1)
7212#define GEN11_TBT1_HOTPLUG (1 << 0)
7213#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
7214#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
7215 GEN11_TBT3_HOTPLUG | \
7216 GEN11_TBT2_HOTPLUG | \
7217 GEN11_TBT1_HOTPLUG)
7218
7219#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
7220#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
7221#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
7222#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
7223#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
7224#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4)
7225
7226#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
7227#define GEN11_CSME (31)
7228#define GEN11_GUNIT (28)
7229#define GEN11_GUC (25)
7230#define GEN11_WDPERF (20)
7231#define GEN11_KCR (19)
7232#define GEN11_GTPM (16)
7233#define GEN11_BCS (15)
7234#define GEN11_RCS0 (0)
7235
7236#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7237#define GEN11_VECS(x) (31 - (x))
7238#define GEN11_VCS(x) (x)
7239
7240#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
7241
7242#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7243#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7244#define GEN11_INTR_DATA_VALID (1 << 31)
7245#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
7246#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
7247#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
7248
7249#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
7250
7251#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7252#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7253
7254#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
7255
7256#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7257#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7258#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7259#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7260#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7261#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7262
7263#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7264#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7265#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7266#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7267#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7268#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7269#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7270#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7271#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7272
7273#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7274
7275#define ILK_ELPIN_409_SELECT (1 << 25)
7276#define ILK_DPARB_GATE (1 << 22)
7277#define ILK_VSDPFD_FULL (1 << 21)
7278#define FUSE_STRAP _MMIO(0x42014)
7279#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7280#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7281#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
7282#define IVB_PIPE_C_DISABLE (1 << 28)
7283#define ILK_HDCP_DISABLE (1 << 25)
7284#define ILK_eDP_A_DISABLE (1 << 24)
7285#define HSW_CDCLK_LIMIT (1 << 24)
7286#define ILK_DESKTOP (1 << 23)
7287
7288#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7289#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7290#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7291#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7292#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7293#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7294
7295#define IVB_CHICKEN3 _MMIO(0x4200c)
7296# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7297# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7298
7299#define CHICKEN_PAR1_1 _MMIO(0x42080)
7300#define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
7301#define DPA_MASK_VBLANK_SRD (1 << 15)
7302#define FORCE_ARB_IDLE_PLANES (1 << 14)
7303#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7304
7305#define CHICKEN_PAR2_1 _MMIO(0x42090)
7306#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
7307
7308#define CHICKEN_MISC_2 _MMIO(0x42084)
7309#define CNL_COMP_PWR_DOWN (1 << 23)
7310#define GLK_CL2_PWR_DOWN (1 << 12)
7311#define GLK_CL1_PWR_DOWN (1 << 11)
7312#define GLK_CL0_PWR_DOWN (1 << 10)
7313
7314#define CHICKEN_MISC_4 _MMIO(0x4208c)
7315#define FBC_STRIDE_OVERRIDE (1 << 13)
7316#define FBC_STRIDE_MASK 0x1FFF
7317
7318#define _CHICKEN_PIPESL_1_A 0x420b0
7319#define _CHICKEN_PIPESL_1_B 0x420b4
7320#define HSW_FBCQ_DIS (1 << 22)
7321#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7322#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7323
7324#define CHICKEN_TRANS_A 0x420c0
7325#define CHICKEN_TRANS_B 0x420c4
7326#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
7327#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25)
7328#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
7329#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
7330#define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17)
7331#define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16)
7332#define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15)
7333#define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12)
7334
7335#define DISP_ARB_CTL _MMIO(0x45000)
7336#define DISP_FBC_MEMORY_WAKE (1 << 31)
7337#define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
7338#define DISP_FBC_WM_DIS (1 << 15)
7339#define DISP_ARB_CTL2 _MMIO(0x45004)
7340#define DISP_DATA_PARTITION_5_6 (1 << 6)
7341#define DISP_IPC_ENABLE (1 << 3)
7342#define DBUF_CTL _MMIO(0x45008)
7343#define DBUF_CTL_S1 _MMIO(0x45008)
7344#define DBUF_CTL_S2 _MMIO(0x44FE8)
7345#define DBUF_POWER_REQUEST (1 << 31)
7346#define DBUF_POWER_STATE (1 << 30)
7347#define GEN7_MSG_CTL _MMIO(0x45010)
7348#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
7349#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
7350#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
7351#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
7352
7353#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
7354#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
7355#define MASK_WAKEMEM (1 << 13)
7356#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
7357
7358#define SKL_DFSM _MMIO(0x51000)
7359#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7360#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7361#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7362#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7363#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
7364#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7365#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7366#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
7367
7368#define SKL_DSSM _MMIO(0x51004)
7369#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
7370#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
7371#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
7372#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
7373#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
7374
7375#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
7376#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
7377
7378#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
7379#define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
7380#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
7381
7382#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
7383#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
7384#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
7385#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
7386#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
7387#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7388#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7389#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7390#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7391
7392
7393#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
7394 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
7395 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
7396
7397#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
7398 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
7399 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
7400 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
7401 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
7402
7403#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
7404 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
7405
7406#define HIZ_CHICKEN _MMIO(0x7018)
7407# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
7408# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
7409
7410#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
7411#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
7412
7413#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7414#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
7415
7416#define GEN7_L3SQCREG1 _MMIO(0xB010)
7417#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7418
7419#define GEN8_L3SQCREG1 _MMIO(0xB100)
7420
7421
7422
7423
7424
7425
7426#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
7427#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
7428#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
7429
7430#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
7431#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
7432#define GEN7_L3AGDIS (1 << 19)
7433#define GEN7_L3CNTLREG2 _MMIO(0xB020)
7434#define GEN7_L3CNTLREG3 _MMIO(0xB024)
7435
7436#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
7437#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
7438#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
7439#define GEN11_I2M_WRITE_DISABLE (1 << 28)
7440
7441#define GEN7_L3SQCREG4 _MMIO(0xb034)
7442#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
7443
7444#define GEN8_L3SQCREG4 _MMIO(0xb118)
7445#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
7446#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
7447#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
7448
7449
7450#define HDC_CHICKEN0 _MMIO(0x7300)
7451#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
7452#define ICL_HDC_MODE _MMIO(0xE5F4)
7453#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
7454#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
7455#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
7456#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
7457#define HDC_FORCE_NON_COHERENT (1 << 4)
7458#define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
7459
7460#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
7461
7462
7463#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
7464#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
7465
7466#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
7467#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
7468
7469
7470#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
7471#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
7472
7473#define HSW_SCRATCH1 _MMIO(0xb038)
7474#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
7475
7476#define BDW_SCRATCH1 _MMIO(0xb11c)
7477#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
7478
7479
7480#define _PIPEA_CHICKEN 0x70038
7481#define _PIPEB_CHICKEN 0x71038
7482#define _PIPEC_CHICKEN 0x72038
7483#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
7484#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7485 _PIPEB_CHICKEN)
7486
7487
7488
7489#define PCH_DISPLAY_BASE 0xc0000u
7490
7491
7492#define SDE_AUDIO_POWER_D (1 << 27)
7493#define SDE_AUDIO_POWER_C (1 << 26)
7494#define SDE_AUDIO_POWER_B (1 << 25)
7495#define SDE_AUDIO_POWER_SHIFT (25)
7496#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
7497#define SDE_GMBUS (1 << 24)
7498#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
7499#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
7500#define SDE_AUDIO_HDCP_MASK (3 << 22)
7501#define SDE_AUDIO_TRANSB (1 << 21)
7502#define SDE_AUDIO_TRANSA (1 << 20)
7503#define SDE_AUDIO_TRANS_MASK (3 << 20)
7504#define SDE_POISON (1 << 19)
7505
7506#define SDE_FDI_RXB (1 << 17)
7507#define SDE_FDI_RXA (1 << 16)
7508#define SDE_FDI_MASK (3 << 16)
7509#define SDE_AUXD (1 << 15)
7510#define SDE_AUXC (1 << 14)
7511#define SDE_AUXB (1 << 13)
7512#define SDE_AUX_MASK (7 << 13)
7513
7514#define SDE_CRT_HOTPLUG (1 << 11)
7515#define SDE_PORTD_HOTPLUG (1 << 10)
7516#define SDE_PORTC_HOTPLUG (1 << 9)
7517#define SDE_PORTB_HOTPLUG (1 << 8)
7518#define SDE_SDVOB_HOTPLUG (1 << 6)
7519#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
7520 SDE_SDVOB_HOTPLUG | \
7521 SDE_PORTB_HOTPLUG | \
7522 SDE_PORTC_HOTPLUG | \
7523 SDE_PORTD_HOTPLUG)
7524#define SDE_TRANSB_CRC_DONE (1 << 5)
7525#define SDE_TRANSB_CRC_ERR (1 << 4)
7526#define SDE_TRANSB_FIFO_UNDER (1 << 3)
7527#define SDE_TRANSA_CRC_DONE (1 << 2)
7528#define SDE_TRANSA_CRC_ERR (1 << 1)
7529#define SDE_TRANSA_FIFO_UNDER (1 << 0)
7530#define SDE_TRANS_MASK (0x3f)
7531
7532
7533#define SDE_AUDIO_POWER_D_CPT (1 << 31)
7534#define SDE_AUDIO_POWER_C_CPT (1 << 30)
7535#define SDE_AUDIO_POWER_B_CPT (1 << 29)
7536#define SDE_AUDIO_POWER_SHIFT_CPT 29
7537#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
7538#define SDE_AUXD_CPT (1 << 27)
7539#define SDE_AUXC_CPT (1 << 26)
7540#define SDE_AUXB_CPT (1 << 25)
7541#define SDE_AUX_MASK_CPT (7 << 25)
7542#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
7543#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
7544#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
7545#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
7546#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
7547#define SDE_CRT_HOTPLUG_CPT (1 << 19)
7548#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
7549#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
7550 SDE_SDVOB_HOTPLUG_CPT | \
7551 SDE_PORTD_HOTPLUG_CPT | \
7552 SDE_PORTC_HOTPLUG_CPT | \
7553 SDE_PORTB_HOTPLUG_CPT)
7554#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
7555 SDE_PORTD_HOTPLUG_CPT | \
7556 SDE_PORTC_HOTPLUG_CPT | \
7557 SDE_PORTB_HOTPLUG_CPT | \
7558 SDE_PORTA_HOTPLUG_SPT)
7559#define SDE_GMBUS_CPT (1 << 17)
7560#define SDE_ERROR_CPT (1 << 16)
7561#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
7562#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
7563#define SDE_FDI_RXC_CPT (1 << 8)
7564#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
7565#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
7566#define SDE_FDI_RXB_CPT (1 << 4)
7567#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
7568#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
7569#define SDE_FDI_RXA_CPT (1 << 0)
7570#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
7571 SDE_AUDIO_CP_REQ_B_CPT | \
7572 SDE_AUDIO_CP_REQ_A_CPT)
7573#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
7574 SDE_AUDIO_CP_CHG_B_CPT | \
7575 SDE_AUDIO_CP_CHG_A_CPT)
7576#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
7577 SDE_FDI_RXB_CPT | \
7578 SDE_FDI_RXA_CPT)
7579
7580
7581#define SDE_TC4_HOTPLUG_ICP (1 << 27)
7582#define SDE_TC3_HOTPLUG_ICP (1 << 26)
7583#define SDE_TC2_HOTPLUG_ICP (1 << 25)
7584#define SDE_TC1_HOTPLUG_ICP (1 << 24)
7585#define SDE_GMBUS_ICP (1 << 23)
7586#define SDE_DDIB_HOTPLUG_ICP (1 << 17)
7587#define SDE_DDIA_HOTPLUG_ICP (1 << 16)
7588#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
7589#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
7590#define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \
7591 SDE_DDIA_HOTPLUG_ICP)
7592#define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \
7593 SDE_TC3_HOTPLUG_ICP | \
7594 SDE_TC2_HOTPLUG_ICP | \
7595 SDE_TC1_HOTPLUG_ICP)
7596
7597#define SDEISR _MMIO(0xc4000)
7598#define SDEIMR _MMIO(0xc4004)
7599#define SDEIIR _MMIO(0xc4008)
7600#define SDEIER _MMIO(0xc400c)
7601
7602#define SERR_INT _MMIO(0xc4040)
7603#define SERR_INT_POISON (1 << 31)
7604#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
7605
7606
7607#define PCH_PORT_HOTPLUG _MMIO(0xc4030)
7608#define PORTA_HOTPLUG_ENABLE (1 << 28)
7609#define BXT_DDIA_HPD_INVERT (1 << 27)
7610#define PORTA_HOTPLUG_STATUS_MASK (3 << 24)
7611#define PORTA_HOTPLUG_NO_DETECT (0 << 24)
7612#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24)
7613#define PORTA_HOTPLUG_LONG_DETECT (2 << 24)
7614#define PORTD_HOTPLUG_ENABLE (1 << 20)
7615#define PORTD_PULSE_DURATION_2ms (0 << 18)
7616#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
7617#define PORTD_PULSE_DURATION_6ms (2 << 18)
7618#define PORTD_PULSE_DURATION_100ms (3 << 18)
7619#define PORTD_PULSE_DURATION_MASK (3 << 18)
7620#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
7621#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
7622#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
7623#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
7624#define PORTC_HOTPLUG_ENABLE (1 << 12)
7625#define BXT_DDIC_HPD_INVERT (1 << 11)
7626#define PORTC_PULSE_DURATION_2ms (0 << 10)
7627#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
7628#define PORTC_PULSE_DURATION_6ms (2 << 10)
7629#define PORTC_PULSE_DURATION_100ms (3 << 10)
7630#define PORTC_PULSE_DURATION_MASK (3 << 10)
7631#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
7632#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
7633#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
7634#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
7635#define PORTB_HOTPLUG_ENABLE (1 << 4)
7636#define BXT_DDIB_HPD_INVERT (1 << 3)
7637#define PORTB_PULSE_DURATION_2ms (0 << 2)
7638#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
7639#define PORTB_PULSE_DURATION_6ms (2 << 2)
7640#define PORTB_PULSE_DURATION_100ms (3 << 2)
7641#define PORTB_PULSE_DURATION_MASK (3 << 2)
7642#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
7643#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
7644#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
7645#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
7646#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
7647 BXT_DDIB_HPD_INVERT | \
7648 BXT_DDIC_HPD_INVERT)
7649
7650#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C)
7651#define PORTE_HOTPLUG_ENABLE (1 << 4)
7652#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
7653#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
7654#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
7655#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
7656
7657
7658
7659
7660
7661
7662#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
7663#define ICP_DDIB_HPD_ENABLE (1 << 7)
7664#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
7665#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
7666#define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
7667#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
7668#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
7669#define ICP_DDIA_HPD_ENABLE (1 << 3)
7670#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
7671#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
7672#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
7673#define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
7674#define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
7675
7676#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
7677#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
7678
7679#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
7680#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
7681#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
7682#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
7683#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
7684#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
7685#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
7686#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
7687#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
7688#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
7689#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
7690#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
7691#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7692 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
7693 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
7694#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7695 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
7696 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
7697#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7698 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
7699 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
7700#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7701 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
7702 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
7703#define RC_BPG_OFFSET_SHIFT 10
7704#define RC_MAX_QP_SHIFT 5
7705#define RC_MIN_QP_SHIFT 0
7706
7707#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
7708#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
7709#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
7710#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
7711#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
7712#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
7713#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
7714#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
7715#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
7716#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
7717#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
7718#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
7719#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7720 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
7721 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
7722#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7723 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
7724 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
7725#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7726 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
7727 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
7728#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7729 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
7730 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
7731
7732#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
7733#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
7734#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
7735#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
7736#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
7737#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
7738#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
7739#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
7740#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
7741#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
7742#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
7743#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
7744#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7745 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
7746 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
7747#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7748 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
7749 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
7750#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7751 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
7752 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
7753#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7754 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
7755 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
7756
7757#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
7758#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
7759#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
7760#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
7761#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
7762#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
7763#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
7764#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
7765#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
7766#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
7767#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
7768#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
7769#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7770 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
7771 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
7772#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7773 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
7774 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
7775#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7776 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
7777 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
7778#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7779 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
7780 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
7781
7782#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
7783#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
7784
7785#define _PCH_DPLL_A 0xc6014
7786#define _PCH_DPLL_B 0xc6018
7787#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
7788
7789#define _PCH_FPA0 0xc6040
7790#define FP_CB_TUNE (0x3 << 22)
7791#define _PCH_FPA1 0xc6044
7792#define _PCH_FPB0 0xc6048
7793#define _PCH_FPB1 0xc604c
7794#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
7795#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
7796
7797#define PCH_DPLL_TEST _MMIO(0xc606c)
7798
7799#define PCH_DREF_CONTROL _MMIO(0xC6200)
7800#define DREF_CONTROL_MASK 0x7fc3
7801#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
7802#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
7803#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
7804#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
7805#define DREF_SSC_SOURCE_DISABLE (0 << 11)
7806#define DREF_SSC_SOURCE_ENABLE (2 << 11)
7807#define DREF_SSC_SOURCE_MASK (3 << 11)
7808#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
7809#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
7810#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
7811#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
7812#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
7813#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
7814#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
7815#define DREF_SSC4_DOWNSPREAD (0 << 6)
7816#define DREF_SSC4_CENTERSPREAD (1 << 6)
7817#define DREF_SSC1_DISABLE (0 << 1)
7818#define DREF_SSC1_ENABLE (1 << 1)
7819#define DREF_SSC4_DISABLE (0)
7820#define DREF_SSC4_ENABLE (1)
7821
7822#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
7823#define FDL_TP1_TIMER_SHIFT 12
7824#define FDL_TP1_TIMER_MASK (3 << 12)
7825#define FDL_TP2_TIMER_SHIFT 10
7826#define FDL_TP2_TIMER_MASK (3 << 10)
7827#define RAWCLK_FREQ_MASK 0x3ff
7828#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
7829#define CNP_RAWCLK_DIV(div) ((div) << 16)
7830#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
7831#define CNP_RAWCLK_FRAC(frac) ((frac) << 26)
7832#define ICP_RAWCLK_DEN(den) ((den) << 26)
7833#define ICP_RAWCLK_NUM(num) ((num) << 11)
7834
7835#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
7836
7837#define PCH_SSC4_PARMS _MMIO(0xc6210)
7838#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
7839
7840#define PCH_DPLL_SEL _MMIO(0xc7000)
7841#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
7842#define TRANS_DPLLA_SEL(pipe) 0
7843#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
7844
7845
7846
7847#define _PCH_TRANS_HTOTAL_A 0xe0000
7848#define TRANS_HTOTAL_SHIFT 16
7849#define TRANS_HACTIVE_SHIFT 0
7850#define _PCH_TRANS_HBLANK_A 0xe0004
7851#define TRANS_HBLANK_END_SHIFT 16
7852#define TRANS_HBLANK_START_SHIFT 0
7853#define _PCH_TRANS_HSYNC_A 0xe0008
7854#define TRANS_HSYNC_END_SHIFT 16
7855#define TRANS_HSYNC_START_SHIFT 0
7856#define _PCH_TRANS_VTOTAL_A 0xe000c
7857#define TRANS_VTOTAL_SHIFT 16
7858#define TRANS_VACTIVE_SHIFT 0
7859#define _PCH_TRANS_VBLANK_A 0xe0010
7860#define TRANS_VBLANK_END_SHIFT 16
7861#define TRANS_VBLANK_START_SHIFT 0
7862#define _PCH_TRANS_VSYNC_A 0xe0014
7863#define TRANS_VSYNC_END_SHIFT 16
7864#define TRANS_VSYNC_START_SHIFT 0
7865#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
7866
7867#define _PCH_TRANSA_DATA_M1 0xe0030
7868#define _PCH_TRANSA_DATA_N1 0xe0034
7869#define _PCH_TRANSA_DATA_M2 0xe0038
7870#define _PCH_TRANSA_DATA_N2 0xe003c
7871#define _PCH_TRANSA_LINK_M1 0xe0040
7872#define _PCH_TRANSA_LINK_N1 0xe0044
7873#define _PCH_TRANSA_LINK_M2 0xe0048
7874#define _PCH_TRANSA_LINK_N2 0xe004c
7875
7876
7877#define _VIDEO_DIP_CTL_A 0xe0200
7878#define _VIDEO_DIP_DATA_A 0xe0208
7879#define _VIDEO_DIP_GCP_A 0xe0210
7880#define GCP_COLOR_INDICATION (1 << 2)
7881#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
7882#define GCP_AV_MUTE (1 << 0)
7883
7884#define _VIDEO_DIP_CTL_B 0xe1200
7885#define _VIDEO_DIP_DATA_B 0xe1208
7886#define _VIDEO_DIP_GCP_B 0xe1210
7887
7888#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
7889#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
7890#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
7891
7892
7893#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
7894#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
7895#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
7896
7897#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
7898#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
7899#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
7900
7901#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
7902#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
7903#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
7904
7905#define VLV_TVIDEO_DIP_CTL(pipe) \
7906 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
7907 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
7908#define VLV_TVIDEO_DIP_DATA(pipe) \
7909 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
7910 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
7911#define VLV_TVIDEO_DIP_GCP(pipe) \
7912 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
7913 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
7914
7915
7916
7917#define _HSW_VIDEO_DIP_CTL_A 0x60200
7918#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
7919#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
7920#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
7921#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
7922#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
7923#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
7924#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
7925#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
7926#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
7927#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
7928#define _HSW_VIDEO_DIP_GCP_A 0x60210
7929
7930#define _HSW_VIDEO_DIP_CTL_B 0x61200
7931#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
7932#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
7933#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
7934#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
7935#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
7936#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
7937#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
7938#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
7939#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
7940#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
7941#define _HSW_VIDEO_DIP_GCP_B 0x61210
7942
7943
7944
7945
7946
7947
7948
7949#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
7950#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
7951#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
7952#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
7953
7954#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
7955#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
7956#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
7957#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
7958#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
7959#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
7960#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
7961#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
7962
7963#define _HSW_STEREO_3D_CTL_A 0x70020
7964#define S3D_ENABLE (1 << 31)
7965#define _HSW_STEREO_3D_CTL_B 0x71020
7966
7967#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
7968
7969#define _PCH_TRANS_HTOTAL_B 0xe1000
7970#define _PCH_TRANS_HBLANK_B 0xe1004
7971#define _PCH_TRANS_HSYNC_B 0xe1008
7972#define _PCH_TRANS_VTOTAL_B 0xe100c
7973#define _PCH_TRANS_VBLANK_B 0xe1010
7974#define _PCH_TRANS_VSYNC_B 0xe1014
7975#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
7976
7977#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
7978#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
7979#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
7980#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
7981#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
7982#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
7983#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
7984
7985#define _PCH_TRANSB_DATA_M1 0xe1030
7986#define _PCH_TRANSB_DATA_N1 0xe1034
7987#define _PCH_TRANSB_DATA_M2 0xe1038
7988#define _PCH_TRANSB_DATA_N2 0xe103c
7989#define _PCH_TRANSB_LINK_M1 0xe1040
7990#define _PCH_TRANSB_LINK_N1 0xe1044
7991#define _PCH_TRANSB_LINK_M2 0xe1048
7992#define _PCH_TRANSB_LINK_N2 0xe104c
7993
7994#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
7995#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
7996#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
7997#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
7998#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
7999#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8000#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8001#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8002
8003#define _PCH_TRANSACONF 0xf0008
8004#define _PCH_TRANSBCONF 0xf1008
8005#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8006#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A)
8007#define TRANS_DISABLE (0 << 31)
8008#define TRANS_ENABLE (1 << 31)
8009#define TRANS_STATE_MASK (1 << 30)
8010#define TRANS_STATE_DISABLE (0 << 30)
8011#define TRANS_STATE_ENABLE (1 << 30)
8012#define TRANS_FSYNC_DELAY_HB1 (0 << 27)
8013#define TRANS_FSYNC_DELAY_HB2 (1 << 27)
8014#define TRANS_FSYNC_DELAY_HB3 (2 << 27)
8015#define TRANS_FSYNC_DELAY_HB4 (3 << 27)
8016#define TRANS_INTERLACE_MASK (7 << 21)
8017#define TRANS_PROGRESSIVE (0 << 21)
8018#define TRANS_INTERLACED (3 << 21)
8019#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8020#define TRANS_8BPC (0 << 5)
8021#define TRANS_10BPC (1 << 5)
8022#define TRANS_6BPC (2 << 5)
8023#define TRANS_12BPC (3 << 5)
8024
8025#define _TRANSA_CHICKEN1 0xf0060
8026#define _TRANSB_CHICKEN1 0xf1060
8027#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8028#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
8029#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
8030#define _TRANSA_CHICKEN2 0xf0064
8031#define _TRANSB_CHICKEN2 0xf1064
8032#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8033#define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
8034#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
8035#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
8036#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
8037#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
8038
8039#define SOUTH_CHICKEN1 _MMIO(0xc2000)
8040#define FDIA_PHASE_SYNC_SHIFT_OVR 19
8041#define FDIA_PHASE_SYNC_SHIFT_EN 18
8042#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8043#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8044#define FDI_BC_BIFURCATION_SELECT (1 << 12)
8045#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
8046#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
8047#define SPT_PWM_GRANULARITY (1 << 0)
8048#define SOUTH_CHICKEN2 _MMIO(0xc2004)
8049#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
8050#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
8051#define LPT_PWM_GRANULARITY (1 << 5)
8052#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
8053
8054#define _FDI_RXA_CHICKEN 0xc200c
8055#define _FDI_RXB_CHICKEN 0xc2010
8056#define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
8057#define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
8058#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8059
8060#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
8061#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8062#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8063#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8064#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8065#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8066#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
8067
8068
8069#define _FDI_TXA_CTL 0x60100
8070#define _FDI_TXB_CTL 0x61100
8071#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8072#define FDI_TX_DISABLE (0 << 31)
8073#define FDI_TX_ENABLE (1 << 31)
8074#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
8075#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
8076#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
8077#define FDI_LINK_TRAIN_NONE (3 << 28)
8078#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
8079#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
8080#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
8081#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
8082#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8083#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8084#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
8085#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
8086
8087
8088
8089#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8090#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8091#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8092#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8093
8094#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
8095#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
8096#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
8097#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
8098#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
8099#define FDI_DP_PORT_WIDTH_SHIFT 19
8100#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
8101#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8102#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
8103
8104#define FDI_TX_PLL_ENABLE (1 << 14)
8105
8106
8107#define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
8108#define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
8109#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
8110#define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
8111
8112
8113#define FDI_COMPOSITE_SYNC (1 << 11)
8114#define FDI_LINK_TRAIN_AUTO (1 << 10)
8115#define FDI_SCRAMBLING_ENABLE (0 << 7)
8116#define FDI_SCRAMBLING_DISABLE (1 << 7)
8117
8118
8119#define _FDI_RXA_CTL 0xf000c
8120#define _FDI_RXB_CTL 0xf100c
8121#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8122#define FDI_RX_ENABLE (1 << 31)
8123
8124#define FDI_FS_ERRC_ENABLE (1 << 27)
8125#define FDI_FE_ERRC_ENABLE (1 << 26)
8126#define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
8127#define FDI_8BPC (0 << 16)
8128#define FDI_10BPC (1 << 16)
8129#define FDI_6BPC (2 << 16)
8130#define FDI_12BPC (3 << 16)
8131#define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
8132#define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
8133#define FDI_RX_PLL_ENABLE (1 << 13)
8134#define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
8135#define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
8136#define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
8137#define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
8138#define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
8139#define FDI_PCDCLK (1 << 4)
8140
8141#define FDI_AUTO_TRAINING (1 << 10)
8142#define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
8143#define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
8144#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
8145#define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
8146#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
8147
8148#define _FDI_RXA_MISC 0xf0010
8149#define _FDI_RXB_MISC 0xf1010
8150#define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
8151#define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
8152#define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
8153#define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
8154#define FDI_RX_TP1_TO_TP2_48 (2 << 20)
8155#define FDI_RX_TP1_TO_TP2_64 (3 << 20)
8156#define FDI_RX_FDI_DELAY_90 (0x90 << 0)
8157#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8158
8159#define _FDI_RXA_TUSIZE1 0xf0030
8160#define _FDI_RXA_TUSIZE2 0xf0038
8161#define _FDI_RXB_TUSIZE1 0xf1030
8162#define _FDI_RXB_TUSIZE2 0xf1038
8163#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8164#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8165
8166
8167#define FDI_RX_INTER_LANE_ALIGN (1 << 10)
8168#define FDI_RX_SYMBOL_LOCK (1 << 9)
8169#define FDI_RX_BIT_LOCK (1 << 8)
8170#define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
8171#define FDI_RX_FS_CODE_ERR (1 << 6)
8172#define FDI_RX_FE_CODE_ERR (1 << 5)
8173#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
8174#define FDI_RX_HDCP_LINK_FAIL (1 << 3)
8175#define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
8176#define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
8177#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
8178
8179#define _FDI_RXA_IIR 0xf0014
8180#define _FDI_RXA_IMR 0xf0018
8181#define _FDI_RXB_IIR 0xf1014
8182#define _FDI_RXB_IMR 0xf1018
8183#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8184#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8185
8186#define FDI_PLL_CTL_1 _MMIO(0xfe000)
8187#define FDI_PLL_CTL_2 _MMIO(0xfe004)
8188
8189#define PCH_LVDS _MMIO(0xe1180)
8190#define LVDS_DETECTED (1 << 1)
8191
8192#define _PCH_DP_B 0xe4100
8193#define PCH_DP_B _MMIO(_PCH_DP_B)
8194#define _PCH_DPB_AUX_CH_CTL 0xe4110
8195#define _PCH_DPB_AUX_CH_DATA1 0xe4114
8196#define _PCH_DPB_AUX_CH_DATA2 0xe4118
8197#define _PCH_DPB_AUX_CH_DATA3 0xe411c
8198#define _PCH_DPB_AUX_CH_DATA4 0xe4120
8199#define _PCH_DPB_AUX_CH_DATA5 0xe4124
8200
8201#define _PCH_DP_C 0xe4200
8202#define PCH_DP_C _MMIO(_PCH_DP_C)
8203#define _PCH_DPC_AUX_CH_CTL 0xe4210
8204#define _PCH_DPC_AUX_CH_DATA1 0xe4214
8205#define _PCH_DPC_AUX_CH_DATA2 0xe4218
8206#define _PCH_DPC_AUX_CH_DATA3 0xe421c
8207#define _PCH_DPC_AUX_CH_DATA4 0xe4220
8208#define _PCH_DPC_AUX_CH_DATA5 0xe4224
8209
8210#define _PCH_DP_D 0xe4300
8211#define PCH_DP_D _MMIO(_PCH_DP_D)
8212#define _PCH_DPD_AUX_CH_CTL 0xe4310
8213#define _PCH_DPD_AUX_CH_DATA1 0xe4314
8214#define _PCH_DPD_AUX_CH_DATA2 0xe4318
8215#define _PCH_DPD_AUX_CH_DATA3 0xe431c
8216#define _PCH_DPD_AUX_CH_DATA4 0xe4320
8217#define _PCH_DPD_AUX_CH_DATA5 0xe4324
8218
8219#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8220#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4)
8221
8222
8223#define _TRANS_DP_CTL_A 0xe0300
8224#define _TRANS_DP_CTL_B 0xe1300
8225#define _TRANS_DP_CTL_C 0xe2300
8226#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8227#define TRANS_DP_OUTPUT_ENABLE (1 << 31)
8228#define TRANS_DP_PORT_SEL_MASK (3 << 29)
8229#define TRANS_DP_PORT_SEL_NONE (3 << 29)
8230#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
8231#define TRANS_DP_AUDIO_ONLY (1 << 26)
8232#define TRANS_DP_ENH_FRAMING (1 << 18)
8233#define TRANS_DP_8BPC (0 << 9)
8234#define TRANS_DP_10BPC (1 << 9)
8235#define TRANS_DP_6BPC (2 << 9)
8236#define TRANS_DP_12BPC (3 << 9)
8237#define TRANS_DP_BPC_MASK (3 << 9)
8238#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
8239#define TRANS_DP_VSYNC_ACTIVE_LOW 0
8240#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
8241#define TRANS_DP_HSYNC_ACTIVE_LOW 0
8242#define TRANS_DP_SYNC_MASK (3 << 3)
8243
8244
8245
8246#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8247#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8248#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8249#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8250
8251#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
8252#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
8253#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
8254#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
8255#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
8256#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
8257
8258
8259#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
8260#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
8261#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
8262#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
8263#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
8264#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
8265#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
8266
8267
8268#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
8269#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
8270#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
8271#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
8272#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
8273
8274#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
8275
8276#define VLV_PMWGICZ _MMIO(0x1300a4)
8277
8278#define RC6_LOCATION _MMIO(0xD40)
8279#define RC6_CTX_IN_DRAM (1 << 0)
8280#define RC6_CTX_BASE _MMIO(0xD48)
8281#define RC6_CTX_BASE_MASK 0xFFFFFFF0
8282#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
8283#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
8284#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
8285#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
8286#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
8287#define IDLE_TIME_MASK 0xFFFFF
8288#define FORCEWAKE _MMIO(0xA18C)
8289#define FORCEWAKE_VLV _MMIO(0x1300b0)
8290#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
8291#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
8292#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
8293#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
8294#define FORCEWAKE_ACK _MMIO(0x130090)
8295#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
8296#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
8297#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
8298#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
8299
8300#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
8301#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
8302#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
8303#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
8304#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
8305#define FORCEWAKE_MT _MMIO(0xa188)
8306#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
8307#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
8308#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
8309#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
8310#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
8311#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
8312#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
8313#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
8314#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
8315#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
8316#define FORCEWAKE_KERNEL BIT(0)
8317#define FORCEWAKE_USER BIT(1)
8318#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
8319#define FORCEWAKE_MT_ACK _MMIO(0x130040)
8320#define ECOBUS _MMIO(0xa180)
8321#define FORCEWAKE_MT_ENABLE (1 << 5)
8322#define VLV_SPAREG2H _MMIO(0xA194)
8323#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
8324#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
8325#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
8326
8327#define GTFIFODBG _MMIO(0x120000)
8328#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
8329#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
8330#define GT_FIFO_SBDROPERR (1 << 6)
8331#define GT_FIFO_BLOBDROPERR (1 << 5)
8332#define GT_FIFO_SB_READ_ABORTERR (1 << 4)
8333#define GT_FIFO_DROPERR (1 << 3)
8334#define GT_FIFO_OVFERR (1 << 2)
8335#define GT_FIFO_IAWRERR (1 << 1)
8336#define GT_FIFO_IARDERR (1 << 0)
8337
8338#define GTFIFOCTL _MMIO(0x120008)
8339#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
8340#define GT_FIFO_NUM_RESERVED_ENTRIES 20
8341#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
8342#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
8343
8344#define HSW_IDICR _MMIO(0x9008)
8345#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
8346#define HSW_EDRAM_CAP _MMIO(0x120010)
8347#define EDRAM_ENABLED 0x1
8348#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
8349#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
8350#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
8351
8352#define GEN6_UCGCTL1 _MMIO(0x9400)
8353# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
8354# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
8355# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
8356# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
8357
8358#define GEN6_UCGCTL2 _MMIO(0x9404)
8359# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
8360# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
8361# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
8362# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
8363# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
8364# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
8365
8366#define GEN6_UCGCTL3 _MMIO(0x9408)
8367# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
8368
8369#define GEN7_UCGCTL4 _MMIO(0x940c)
8370#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
8371#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
8372
8373#define GEN6_RCGCTL1 _MMIO(0x9410)
8374#define GEN6_RCGCTL2 _MMIO(0x9414)
8375#define GEN6_RSTCTL _MMIO(0x9420)
8376
8377#define GEN8_UCGCTL6 _MMIO(0x9430)
8378#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
8379#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
8380#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
8381
8382#define GEN6_GFXPAUSE _MMIO(0xA000)
8383#define GEN6_RPNSWREQ _MMIO(0xA008)
8384#define GEN6_TURBO_DISABLE (1 << 31)
8385#define GEN6_FREQUENCY(x) ((x) << 25)
8386#define HSW_FREQUENCY(x) ((x) << 24)
8387#define GEN9_FREQUENCY(x) ((x) << 23)
8388#define GEN6_OFFSET(x) ((x) << 19)
8389#define GEN6_AGGRESSIVE_TURBO (0 << 15)
8390#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
8391#define GEN6_RC_CONTROL _MMIO(0xA090)
8392#define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
8393#define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
8394#define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
8395#define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
8396#define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
8397#define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
8398#define GEN7_RC_CTL_TO_MODE (1 << 28)
8399#define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
8400#define GEN6_RC_CTL_HW_ENABLE (1 << 31)
8401#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
8402#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
8403#define GEN6_RPSTAT1 _MMIO(0xA01C)
8404#define GEN6_CAGF_SHIFT 8
8405#define HSW_CAGF_SHIFT 7
8406#define GEN9_CAGF_SHIFT 23
8407#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
8408#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
8409#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
8410#define GEN6_RP_CONTROL _MMIO(0xA024)
8411#define GEN6_RP_MEDIA_TURBO (1 << 11)
8412#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
8413#define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
8414#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
8415#define GEN6_RP_MEDIA_HW_MODE (1 << 9)
8416#define GEN6_RP_MEDIA_SW_MODE (0 << 9)
8417#define GEN6_RP_MEDIA_IS_GFX (1 << 8)
8418#define GEN6_RP_ENABLE (1 << 7)
8419#define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
8420#define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
8421#define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
8422#define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
8423#define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
8424#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
8425#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
8426#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
8427#define GEN6_RP_EI_MASK 0xffffff
8428#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
8429#define GEN6_RP_CUR_UP _MMIO(0xA054)
8430#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
8431#define GEN6_RP_PREV_UP _MMIO(0xA058)
8432#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
8433#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
8434#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
8435#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
8436#define GEN6_RP_UP_EI _MMIO(0xA068)
8437#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
8438#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
8439#define GEN6_RPDEUHWTC _MMIO(0xA080)
8440#define GEN6_RPDEUC _MMIO(0xA084)
8441#define GEN6_RPDEUCSW _MMIO(0xA088)
8442#define GEN6_RC_STATE _MMIO(0xA094)
8443#define RC_SW_TARGET_STATE_SHIFT 16
8444#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
8445#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
8446#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
8447#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8448#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8449#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
8450#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
8451#define GEN6_RC_SLEEP _MMIO(0xA0B0)
8452#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
8453#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
8454#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
8455#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
8456#define VLV_RCEDATA _MMIO(0xA0BC)
8457#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
8458#define GEN6_PMINTRMSK _MMIO(0xA168)
8459#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
8460#define ARAT_EXPIRED_INTRMSK (1 << 9)
8461#define GEN8_MISC_CTRL0 _MMIO(0xA180)
8462#define VLV_PWRDWNUPCTL _MMIO(0xA294)
8463#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8464#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8465#define GEN9_PG_ENABLE _MMIO(0xA210)
8466#define GEN9_RENDER_PG_ENABLE (1 << 0)
8467#define GEN9_MEDIA_PG_ENABLE (1 << 1)
8468#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8469#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8470#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
8471
8472#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8473#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
8474#define PIXEL_OVERLAP_CNT_SHIFT 30
8475
8476#define GEN6_PMISR _MMIO(0x44020)
8477#define GEN6_PMIMR _MMIO(0x44024)
8478#define GEN6_PMIIR _MMIO(0x44028)
8479#define GEN6_PMIER _MMIO(0x4402C)
8480#define GEN6_PM_MBOX_EVENT (1 << 25)
8481#define GEN6_PM_THERMAL_EVENT (1 << 24)
8482#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
8483#define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
8484#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
8485#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
8486#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
8487#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
8488 GEN6_PM_RP_UP_THRESHOLD | \
8489 GEN6_PM_RP_DOWN_EI_EXPIRED | \
8490 GEN6_PM_RP_DOWN_THRESHOLD | \
8491 GEN6_PM_RP_DOWN_TIMEOUT)
8492
8493#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
8494#define GEN7_GT_SCRATCH_REG_NUM 8
8495
8496#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
8497#define VLV_GFX_CLK_STATUS_BIT (1 << 3)
8498#define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
8499
8500#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
8501#define VLV_COUNTER_CONTROL _MMIO(0x138104)
8502#define VLV_COUNT_RANGE_HIGH (1 << 15)
8503#define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
8504#define VLV_RENDER_RC0_COUNT_EN (1 << 4)
8505#define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
8506#define VLV_RENDER_RC6_COUNT_EN (1 << 0)
8507#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
8508#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
8509#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
8510
8511#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
8512#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
8513#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
8514#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
8515
8516#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8517#define GEN6_PCODE_READY (1 << 31)
8518#define GEN6_PCODE_ERROR_MASK 0xFF
8519#define GEN6_PCODE_SUCCESS 0x0
8520#define GEN6_PCODE_ILLEGAL_CMD 0x1
8521#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8522#define GEN6_PCODE_TIMEOUT 0x3
8523#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8524#define GEN7_PCODE_TIMEOUT 0x2
8525#define GEN7_PCODE_ILLEGAL_DATA 0x3
8526#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8527#define GEN6_PCODE_WRITE_RC6VIDS 0x4
8528#define GEN6_PCODE_READ_RC6VIDS 0x5
8529#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
8530#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
8531#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
8532#define GEN9_PCODE_READ_MEM_LATENCY 0x6
8533#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
8534#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
8535#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
8536#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
8537#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
8538#define SKL_PCODE_CDCLK_CONTROL 0x7
8539#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
8540#define SKL_CDCLK_READY_FOR_CHANGE 0x1
8541#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8542#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8543#define GEN6_READ_OC_PARAMS 0xc
8544#define GEN6_PCODE_READ_D_COMP 0x10
8545#define GEN6_PCODE_WRITE_D_COMP 0x11
8546#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
8547#define DISPLAY_IPS_CONTROL 0x19
8548
8549#define IPS_PCODE_CONTROL (1 << 30)
8550#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
8551#define GEN9_PCODE_SAGV_CONTROL 0x21
8552#define GEN9_SAGV_DISABLE 0x0
8553#define GEN9_SAGV_IS_DISABLED 0x1
8554#define GEN9_SAGV_ENABLE 0x3
8555#define GEN6_PCODE_DATA _MMIO(0x138128)
8556#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
8557#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
8558#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
8559
8560#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
8561#define GEN6_CORE_CPD_STATE_MASK (7 << 4)
8562#define GEN6_RCn_MASK 7
8563#define GEN6_RC0 0
8564#define GEN6_RC3 2
8565#define GEN6_RC6 3
8566#define GEN6_RC7 4
8567
8568#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
8569#define GEN8_LSLICESTAT_MASK 0x7
8570
8571#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
8572#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
8573#define CHV_SS_PG_ENABLE (1 << 1)
8574#define CHV_EU08_PG_ENABLE (1 << 9)
8575#define CHV_EU19_PG_ENABLE (1 << 17)
8576#define CHV_EU210_PG_ENABLE (1 << 25)
8577
8578#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
8579#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
8580#define CHV_EU311_PG_ENABLE (1 << 1)
8581
8582#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
8583#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8584 ((slice) % 3) * 0x4)
8585#define GEN9_PGCTL_SLICE_ACK (1 << 0)
8586#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
8587#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8588
8589#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
8590#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8591 ((slice) % 3) * 0x8)
8592#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
8593#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8594 ((slice) % 3) * 0x8)
8595#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
8596#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
8597#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
8598#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
8599#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
8600#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
8601#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
8602#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
8603
8604#define GEN7_MISCCPCTL _MMIO(0x9424)
8605#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
8606#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
8607#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
8608#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
8609
8610#define GEN8_GARBCNTL _MMIO(0xB004)
8611#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
8612#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
8613#define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
8614#define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
8615
8616#define GEN11_GLBLINVL _MMIO(0xB404)
8617#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
8618#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
8619
8620#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
8621#define DFR_DISABLE (1 << 9)
8622
8623#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
8624#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
8625#define GEN11_HASH_CTRL_BIT0 (1 << 0)
8626#define GEN11_HASH_CTRL_BIT4 (1 << 12)
8627
8628#define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
8629#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
8630#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
8631
8632#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
8633#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
8634
8635
8636#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200)
8637#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
8638#define GEN7_PARITY_ERROR_VALID (1 << 13)
8639#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
8640#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
8641#define GEN7_PARITY_ERROR_ROW(reg) \
8642 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8643#define GEN7_PARITY_ERROR_BANK(reg) \
8644 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8645#define GEN7_PARITY_ERROR_SUBBANK(reg) \
8646 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8647#define GEN7_L3CDERRST1_ENABLE (1 << 7)
8648
8649#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8650#define GEN7_L3LOG_SIZE 0x80
8651
8652#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
8653#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
8654#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
8655#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
8656#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
8657#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
8658
8659#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
8660#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
8661#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
8662
8663#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
8664#define FLOW_CONTROL_ENABLE (1 << 15)
8665#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
8666#define STALL_DOP_GATING_DISABLE (1 << 5)
8667#define THROTTLE_12_5 (7 << 2)
8668#define DISABLE_EARLY_EOT (1 << 1)
8669
8670#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
8671#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
8672#define DOP_CLOCK_GATING_DISABLE (1 << 0)
8673#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
8674#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
8675
8676#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
8677#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
8678
8679#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
8680#define GEN8_ST_PO_DISABLE (1 << 13)
8681
8682#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
8683#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
8684#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
8685#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
8686#define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
8687#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
8688
8689#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
8690#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8)
8691#define GEN9_ENABLE_YV12_BUGFIX (1 << 4)
8692#define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
8693
8694
8695#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
8696#define INTEL_AUDIO_DEVCL 0x808629FB
8697#define INTEL_AUDIO_DEVBLC 0x80862801
8698#define INTEL_AUDIO_DEVCTG 0x80862802
8699
8700#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
8701#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
8702#define G4X_ELDV_DEVCTG (1 << 14)
8703#define G4X_ELD_ADDR_MASK (0xf << 5)
8704#define G4X_ELD_ACK (1 << 4)
8705#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
8706
8707#define _IBX_HDMIW_HDMIEDID_A 0xE2050
8708#define _IBX_HDMIW_HDMIEDID_B 0xE2150
8709#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
8710 _IBX_HDMIW_HDMIEDID_B)
8711#define _IBX_AUD_CNTL_ST_A 0xE20B4
8712#define _IBX_AUD_CNTL_ST_B 0xE21B4
8713#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
8714 _IBX_AUD_CNTL_ST_B)
8715#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
8716#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
8717#define IBX_ELD_ACK (1 << 4)
8718#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
8719#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
8720#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
8721
8722#define _CPT_HDMIW_HDMIEDID_A 0xE5050
8723#define _CPT_HDMIW_HDMIEDID_B 0xE5150
8724#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
8725#define _CPT_AUD_CNTL_ST_A 0xE50B4
8726#define _CPT_AUD_CNTL_ST_B 0xE51B4
8727#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
8728#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
8729
8730#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
8731#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
8732#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
8733#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
8734#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
8735#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
8736#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
8737
8738
8739
8740
8741
8742#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
8743
8744#define _IBX_AUD_CONFIG_A 0xe2000
8745#define _IBX_AUD_CONFIG_B 0xe2100
8746#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
8747#define _CPT_AUD_CONFIG_A 0xe5000
8748#define _CPT_AUD_CONFIG_B 0xe5100
8749#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
8750#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
8751#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
8752#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
8753
8754#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
8755#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
8756#define AUD_CONFIG_UPPER_N_SHIFT 20
8757#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
8758#define AUD_CONFIG_LOWER_N_SHIFT 4
8759#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
8760#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
8761#define AUD_CONFIG_N(n) \
8762 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
8763 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
8764#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
8765#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
8766#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
8767#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
8768#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
8769#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
8770#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
8771#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
8772#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
8773#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
8774#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
8775#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
8776#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
8777
8778
8779#define _HSW_AUD_CONFIG_A 0x65000
8780#define _HSW_AUD_CONFIG_B 0x65100
8781#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
8782
8783#define _HSW_AUD_MISC_CTRL_A 0x65010
8784#define _HSW_AUD_MISC_CTRL_B 0x65110
8785#define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
8786
8787#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
8788#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
8789#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
8790#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
8791#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
8792#define AUD_CONFIG_M_MASK 0xfffff
8793
8794#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
8795#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
8796#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
8797
8798
8799#define _HSW_AUD_DIG_CNVT_1 0x65080
8800#define _HSW_AUD_DIG_CNVT_2 0x65180
8801#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
8802#define DIP_PORT_SEL_MASK 0x3
8803
8804#define _HSW_AUD_EDID_DATA_A 0x65050
8805#define _HSW_AUD_EDID_DATA_B 0x65150
8806#define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
8807
8808#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
8809#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
8810#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
8811#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
8812#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
8813#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
8814
8815#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
8816#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
8817
8818
8819
8820
8821
8822
8823
8824
8825
8826
8827
8828
8829
8830
8831
8832
8833#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
8834#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
8835#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
8836#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
8837#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
8838#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
8839
8840
8841#define HSW_PW_CTL_IDX_GLOBAL 15
8842
8843
8844#define SKL_PW_CTL_IDX_PW_2 15
8845#define SKL_PW_CTL_IDX_PW_1 14
8846#define CNL_PW_CTL_IDX_AUX_F 12
8847#define CNL_PW_CTL_IDX_AUX_D 11
8848#define GLK_PW_CTL_IDX_AUX_C 10
8849#define GLK_PW_CTL_IDX_AUX_B 9
8850#define GLK_PW_CTL_IDX_AUX_A 8
8851#define CNL_PW_CTL_IDX_DDI_F 6
8852#define SKL_PW_CTL_IDX_DDI_D 4
8853#define SKL_PW_CTL_IDX_DDI_C 3
8854#define SKL_PW_CTL_IDX_DDI_B 2
8855#define SKL_PW_CTL_IDX_DDI_A_E 1
8856#define GLK_PW_CTL_IDX_DDI_A 1
8857#define SKL_PW_CTL_IDX_MISC_IO 0
8858
8859
8860#define ICL_PW_CTL_IDX_PW_4 3
8861#define ICL_PW_CTL_IDX_PW_3 2
8862#define ICL_PW_CTL_IDX_PW_2 1
8863#define ICL_PW_CTL_IDX_PW_1 0
8864
8865#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
8866#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
8867#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
8868#define ICL_PW_CTL_IDX_AUX_TBT4 11
8869#define ICL_PW_CTL_IDX_AUX_TBT3 10
8870#define ICL_PW_CTL_IDX_AUX_TBT2 9
8871#define ICL_PW_CTL_IDX_AUX_TBT1 8
8872#define ICL_PW_CTL_IDX_AUX_F 5
8873#define ICL_PW_CTL_IDX_AUX_E 4
8874#define ICL_PW_CTL_IDX_AUX_D 3
8875#define ICL_PW_CTL_IDX_AUX_C 2
8876#define ICL_PW_CTL_IDX_AUX_B 1
8877#define ICL_PW_CTL_IDX_AUX_A 0
8878
8879#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
8880#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
8881#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
8882#define ICL_PW_CTL_IDX_DDI_F 5
8883#define ICL_PW_CTL_IDX_DDI_E 4
8884#define ICL_PW_CTL_IDX_DDI_D 3
8885#define ICL_PW_CTL_IDX_DDI_C 2
8886#define ICL_PW_CTL_IDX_DDI_B 1
8887#define ICL_PW_CTL_IDX_DDI_A 0
8888
8889
8890#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
8891#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
8892#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
8893#define HSW_PWR_WELL_FORCE_ON (1 << 19)
8894#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
8895
8896
8897enum skl_power_gate {
8898 SKL_PG0,
8899 SKL_PG1,
8900 SKL_PG2,
8901 ICL_PG3,
8902 ICL_PG4,
8903};
8904
8905#define SKL_FUSE_STATUS _MMIO(0x42000)
8906#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
8907
8908
8909
8910
8911#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
8912 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
8913
8914
8915
8916
8917#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
8918 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
8919#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
8920
8921#define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
8922#define _CNL_AUX_ANAOVRD1_B 0x162250
8923#define _CNL_AUX_ANAOVRD1_C 0x162210
8924#define _CNL_AUX_ANAOVRD1_D 0x1622D0
8925#define _CNL_AUX_ANAOVRD1_F 0x162A90
8926#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
8927 _CNL_AUX_ANAOVRD1_B, \
8928 _CNL_AUX_ANAOVRD1_C, \
8929 _CNL_AUX_ANAOVRD1_D, \
8930 _CNL_AUX_ANAOVRD1_F))
8931#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
8932#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
8933
8934
8935#define HDCP_KEY_CONF _MMIO(0x66c00)
8936#define HDCP_AKSV_SEND_TRIGGER BIT(31)
8937#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
8938#define HDCP_KEY_LOAD_TRIGGER BIT(8)
8939#define HDCP_KEY_STATUS _MMIO(0x66c04)
8940#define HDCP_FUSE_IN_PROGRESS BIT(7)
8941#define HDCP_FUSE_ERROR BIT(6)
8942#define HDCP_FUSE_DONE BIT(5)
8943#define HDCP_KEY_LOAD_STATUS BIT(1)
8944#define HDCP_KEY_LOAD_DONE BIT(0)
8945#define HDCP_AKSV_LO _MMIO(0x66c10)
8946#define HDCP_AKSV_HI _MMIO(0x66c14)
8947
8948
8949#define HDCP_REP_CTL _MMIO(0x66d00)
8950#define HDCP_DDIB_REP_PRESENT BIT(30)
8951#define HDCP_DDIA_REP_PRESENT BIT(29)
8952#define HDCP_DDIC_REP_PRESENT BIT(28)
8953#define HDCP_DDID_REP_PRESENT BIT(27)
8954#define HDCP_DDIF_REP_PRESENT BIT(26)
8955#define HDCP_DDIE_REP_PRESENT BIT(25)
8956#define HDCP_DDIB_SHA1_M0 (1 << 20)
8957#define HDCP_DDIA_SHA1_M0 (2 << 20)
8958#define HDCP_DDIC_SHA1_M0 (3 << 20)
8959#define HDCP_DDID_SHA1_M0 (4 << 20)
8960#define HDCP_DDIF_SHA1_M0 (5 << 20)
8961#define HDCP_DDIE_SHA1_M0 (6 << 20)
8962#define HDCP_SHA1_BUSY BIT(16)
8963#define HDCP_SHA1_READY BIT(17)
8964#define HDCP_SHA1_COMPLETE BIT(18)
8965#define HDCP_SHA1_V_MATCH BIT(19)
8966#define HDCP_SHA1_TEXT_32 (1 << 1)
8967#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
8968#define HDCP_SHA1_TEXT_24 (4 << 1)
8969#define HDCP_SHA1_TEXT_16 (5 << 1)
8970#define HDCP_SHA1_TEXT_8 (6 << 1)
8971#define HDCP_SHA1_TEXT_0 (7 << 1)
8972#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
8973#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
8974#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
8975#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
8976#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
8977#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
8978#define HDCP_SHA_TEXT _MMIO(0x66d18)
8979
8980
8981#define _PORTA_HDCP_AUTHENC 0x66800
8982#define _PORTB_HDCP_AUTHENC 0x66500
8983#define _PORTC_HDCP_AUTHENC 0x66600
8984#define _PORTD_HDCP_AUTHENC 0x66700
8985#define _PORTE_HDCP_AUTHENC 0x66A00
8986#define _PORTF_HDCP_AUTHENC 0x66900
8987#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
8988 _PORTA_HDCP_AUTHENC, \
8989 _PORTB_HDCP_AUTHENC, \
8990 _PORTC_HDCP_AUTHENC, \
8991 _PORTD_HDCP_AUTHENC, \
8992 _PORTE_HDCP_AUTHENC, \
8993 _PORTF_HDCP_AUTHENC) + (x))
8994#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
8995#define HDCP_CONF_CAPTURE_AN BIT(0)
8996#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
8997#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
8998#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
8999#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
9000#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
9001#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
9002#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
9003#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
9004#define HDCP_STATUS_STREAM_A_ENC BIT(31)
9005#define HDCP_STATUS_STREAM_B_ENC BIT(30)
9006#define HDCP_STATUS_STREAM_C_ENC BIT(29)
9007#define HDCP_STATUS_STREAM_D_ENC BIT(28)
9008#define HDCP_STATUS_AUTH BIT(21)
9009#define HDCP_STATUS_ENC BIT(20)
9010#define HDCP_STATUS_RI_MATCH BIT(19)
9011#define HDCP_STATUS_R0_READY BIT(18)
9012#define HDCP_STATUS_AN_READY BIT(17)
9013#define HDCP_STATUS_CIPHER BIT(16)
9014#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
9015
9016
9017#define _TRANS_DDI_FUNC_CTL_A 0x60400
9018#define _TRANS_DDI_FUNC_CTL_B 0x61400
9019#define _TRANS_DDI_FUNC_CTL_C 0x62400
9020#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
9021#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9022
9023#define TRANS_DDI_FUNC_ENABLE (1 << 31)
9024
9025#define TRANS_DDI_PORT_MASK (7 << 28)
9026#define TRANS_DDI_PORT_SHIFT 28
9027#define TRANS_DDI_SELECT_PORT(x) ((x) << 28)
9028#define TRANS_DDI_PORT_NONE (0 << 28)
9029#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
9030#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
9031#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
9032#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
9033#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
9034#define TRANS_DDI_MODE_SELECT_FDI (4 << 24)
9035#define TRANS_DDI_BPC_MASK (7 << 20)
9036#define TRANS_DDI_BPC_8 (0 << 20)
9037#define TRANS_DDI_BPC_10 (1 << 20)
9038#define TRANS_DDI_BPC_6 (2 << 20)
9039#define TRANS_DDI_BPC_12 (3 << 20)
9040#define TRANS_DDI_PVSYNC (1 << 17)
9041#define TRANS_DDI_PHSYNC (1 << 16)
9042#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
9043#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
9044#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
9045#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
9046#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
9047#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
9048#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
9049#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9050#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9051#define TRANS_DDI_BFI_ENABLE (1 << 4)
9052#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
9053#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
9054#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9055 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9056 | TRANS_DDI_HDMI_SCRAMBLING)
9057
9058
9059#define _DP_TP_CTL_A 0x64040
9060#define _DP_TP_CTL_B 0x64140
9061#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9062#define DP_TP_CTL_ENABLE (1 << 31)
9063#define DP_TP_CTL_MODE_SST (0 << 27)
9064#define DP_TP_CTL_MODE_MST (1 << 27)
9065#define DP_TP_CTL_FORCE_ACT (1 << 25)
9066#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
9067#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
9068#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
9069#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
9070#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
9071#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
9072#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
9073#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
9074#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
9075#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
9076
9077
9078#define _DP_TP_STATUS_A 0x64044
9079#define _DP_TP_STATUS_B 0x64144
9080#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
9081#define DP_TP_STATUS_IDLE_DONE (1 << 25)
9082#define DP_TP_STATUS_ACT_SENT (1 << 24)
9083#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
9084#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
9085#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
9086#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
9087#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
9088
9089
9090#define _DDI_BUF_CTL_A 0x64000
9091#define _DDI_BUF_CTL_B 0x64100
9092#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
9093#define DDI_BUF_CTL_ENABLE (1 << 31)
9094#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
9095#define DDI_BUF_EMP_MASK (0xf << 24)
9096#define DDI_BUF_PORT_REVERSAL (1 << 16)
9097#define DDI_BUF_IS_IDLE (1 << 7)
9098#define DDI_A_4_LANES (1 << 4)
9099#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
9100#define DDI_PORT_WIDTH_MASK (7 << 1)
9101#define DDI_PORT_WIDTH_SHIFT 1
9102#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
9103
9104
9105#define _DDI_BUF_TRANS_A 0x64E00
9106#define _DDI_BUF_TRANS_B 0x64E60
9107#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9108#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
9109#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
9110
9111
9112
9113
9114#define SBI_ADDR _MMIO(0xC6000)
9115#define SBI_DATA _MMIO(0xC6004)
9116#define SBI_CTL_STAT _MMIO(0xC6008)
9117#define SBI_CTL_DEST_ICLK (0x0 << 16)
9118#define SBI_CTL_DEST_MPHY (0x1 << 16)
9119#define SBI_CTL_OP_IORD (0x2 << 8)
9120#define SBI_CTL_OP_IOWR (0x3 << 8)
9121#define SBI_CTL_OP_CRRD (0x6 << 8)
9122#define SBI_CTL_OP_CRWR (0x7 << 8)
9123#define SBI_RESPONSE_FAIL (0x1 << 1)
9124#define SBI_RESPONSE_SUCCESS (0x0 << 1)
9125#define SBI_BUSY (0x1 << 0)
9126#define SBI_READY (0x0 << 0)
9127
9128
9129#define SBI_SSCDIVINTPHASE 0x0200
9130#define SBI_SSCDIVINTPHASE6 0x0600
9131#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
9132#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
9133#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
9134#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
9135#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
9136#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
9137#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
9138#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
9139#define SBI_SSCDITHPHASE 0x0204
9140#define SBI_SSCCTL 0x020c
9141#define SBI_SSCCTL6 0x060C
9142#define SBI_SSCCTL_PATHALT (1 << 3)
9143#define SBI_SSCCTL_DISABLE (1 << 0)
9144#define SBI_SSCAUXDIV6 0x0610
9145#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
9146#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
9147#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
9148#define SBI_DBUFF0 0x2a00
9149#define SBI_GEN0 0x1f00
9150#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
9151
9152
9153#define PIXCLK_GATE _MMIO(0xC6020)
9154#define PIXCLK_GATE_UNGATE (1 << 0)
9155#define PIXCLK_GATE_GATE (0 << 0)
9156
9157
9158#define SPLL_CTL _MMIO(0x46020)
9159#define SPLL_PLL_ENABLE (1 << 31)
9160#define SPLL_PLL_SSC (1 << 28)
9161#define SPLL_PLL_NON_SSC (2 << 28)
9162#define SPLL_PLL_LCPLL (3 << 28)
9163#define SPLL_PLL_REF_MASK (3 << 28)
9164#define SPLL_PLL_FREQ_810MHz (0 << 26)
9165#define SPLL_PLL_FREQ_1350MHz (1 << 26)
9166#define SPLL_PLL_FREQ_2700MHz (2 << 26)
9167#define SPLL_PLL_FREQ_MASK (3 << 26)
9168
9169
9170#define _WRPLL_CTL1 0x46040
9171#define _WRPLL_CTL2 0x46060
9172#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9173#define WRPLL_PLL_ENABLE (1 << 31)
9174#define WRPLL_PLL_SSC (1 << 28)
9175#define WRPLL_PLL_NON_SSC (2 << 28)
9176#define WRPLL_PLL_LCPLL (3 << 28)
9177#define WRPLL_PLL_REF_MASK (3 << 28)
9178
9179#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
9180#define WRPLL_DIVIDER_REF_MASK (0xff)
9181#define WRPLL_DIVIDER_POST(x) ((x) << 8)
9182#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
9183#define WRPLL_DIVIDER_POST_SHIFT 8
9184#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
9185#define WRPLL_DIVIDER_FB_SHIFT 16
9186#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
9187
9188
9189#define _PORT_CLK_SEL_A 0x46100
9190#define _PORT_CLK_SEL_B 0x46104
9191#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9192#define PORT_CLK_SEL_LCPLL_2700 (0 << 29)
9193#define PORT_CLK_SEL_LCPLL_1350 (1 << 29)
9194#define PORT_CLK_SEL_LCPLL_810 (2 << 29)
9195#define PORT_CLK_SEL_SPLL (3 << 29)
9196#define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29)
9197#define PORT_CLK_SEL_WRPLL1 (4 << 29)
9198#define PORT_CLK_SEL_WRPLL2 (5 << 29)
9199#define PORT_CLK_SEL_NONE (7 << 29)
9200#define PORT_CLK_SEL_MASK (7 << 29)
9201
9202
9203#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
9204#define DDI_CLK_SEL_NONE (0x0 << 28)
9205#define DDI_CLK_SEL_MG (0x8 << 28)
9206#define DDI_CLK_SEL_TBT_162 (0xC << 28)
9207#define DDI_CLK_SEL_TBT_270 (0xD << 28)
9208#define DDI_CLK_SEL_TBT_540 (0xE << 28)
9209#define DDI_CLK_SEL_TBT_810 (0xF << 28)
9210#define DDI_CLK_SEL_MASK (0xF << 28)
9211
9212
9213#define _TRANS_CLK_SEL_A 0x46140
9214#define _TRANS_CLK_SEL_B 0x46144
9215#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
9216
9217#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
9218#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
9219
9220#define CDCLK_FREQ _MMIO(0x46200)
9221
9222#define _TRANSA_MSA_MISC 0x60410
9223#define _TRANSB_MSA_MISC 0x61410
9224#define _TRANSC_MSA_MISC 0x62410
9225#define _TRANS_EDP_MSA_MISC 0x6f410
9226#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9227
9228#define TRANS_MSA_SYNC_CLK (1 << 0)
9229#define TRANS_MSA_6_BPC (0 << 5)
9230#define TRANS_MSA_8_BPC (1 << 5)
9231#define TRANS_MSA_10_BPC (2 << 5)
9232#define TRANS_MSA_12_BPC (3 << 5)
9233#define TRANS_MSA_16_BPC (4 << 5)
9234#define TRANS_MSA_CEA_RANGE (1 << 3)
9235
9236
9237#define LCPLL_CTL _MMIO(0x130040)
9238#define LCPLL_PLL_DISABLE (1 << 31)
9239#define LCPLL_PLL_LOCK (1 << 30)
9240#define LCPLL_CLK_FREQ_MASK (3 << 26)
9241#define LCPLL_CLK_FREQ_450 (0 << 26)
9242#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
9243#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
9244#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
9245#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
9246#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
9247#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
9248#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
9249#define LCPLL_CD_SOURCE_FCLK (1 << 21)
9250#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
9251
9252
9253
9254
9255
9256
9257#define CDCLK_CTL _MMIO(0x46000)
9258#define CDCLK_FREQ_SEL_MASK (3 << 26)
9259#define CDCLK_FREQ_450_432 (0 << 26)
9260#define CDCLK_FREQ_540 (1 << 26)
9261#define CDCLK_FREQ_337_308 (2 << 26)
9262#define CDCLK_FREQ_675_617 (3 << 26)
9263#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
9264#define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
9265#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
9266#define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
9267#define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
9268#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
9269#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
9270#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
9271#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
9272#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
9273#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
9274
9275
9276#define LCPLL1_CTL _MMIO(0x46010)
9277#define LCPLL2_CTL _MMIO(0x46014)
9278#define LCPLL_PLL_ENABLE (1 << 31)
9279
9280
9281#define DPLL_CTRL1 _MMIO(0x6C058)
9282#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
9283#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
9284#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
9285#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
9286#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
9287#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
9288#define DPLL_CTRL1_LINK_RATE_2700 0
9289#define DPLL_CTRL1_LINK_RATE_1350 1
9290#define DPLL_CTRL1_LINK_RATE_810 2
9291#define DPLL_CTRL1_LINK_RATE_1620 3
9292#define DPLL_CTRL1_LINK_RATE_1080 4
9293#define DPLL_CTRL1_LINK_RATE_2160 5
9294
9295
9296#define DPLL_CTRL2 _MMIO(0x6C05C)
9297#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
9298#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
9299#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
9300#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
9301#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
9302
9303
9304#define DPLL_STATUS _MMIO(0x6C060)
9305#define DPLL_LOCK(id) (1 << ((id) * 8))
9306
9307
9308#define _DPLL1_CFGCR1 0x6C040
9309#define _DPLL2_CFGCR1 0x6C048
9310#define _DPLL3_CFGCR1 0x6C050
9311#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
9312#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
9313#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
9314#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
9315
9316#define _DPLL1_CFGCR2 0x6C044
9317#define _DPLL2_CFGCR2 0x6C04C
9318#define _DPLL3_CFGCR2 0x6C054
9319#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
9320#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
9321#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
9322#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
9323#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
9324#define DPLL_CFGCR2_KDIV_5 (0 << 5)
9325#define DPLL_CFGCR2_KDIV_2 (1 << 5)
9326#define DPLL_CFGCR2_KDIV_3 (2 << 5)
9327#define DPLL_CFGCR2_KDIV_1 (3 << 5)
9328#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
9329#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
9330#define DPLL_CFGCR2_PDIV_1 (0 << 2)
9331#define DPLL_CFGCR2_PDIV_2 (1 << 2)
9332#define DPLL_CFGCR2_PDIV_3 (2 << 2)
9333#define DPLL_CFGCR2_PDIV_7 (4 << 2)
9334#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
9335
9336#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
9337#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
9338
9339
9340
9341
9342#define DPCLKA_CFGCR0 _MMIO(0x6C200)
9343#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
9344#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
9345 (port) + 10))
9346#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
9347#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
9348 21 : (tc_port) + 12))
9349#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
9350 (port) * 2)
9351#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9352#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9353
9354
9355#define DPLL0_ENABLE 0x46010
9356#define DPLL1_ENABLE 0x46014
9357#define PLL_ENABLE (1 << 31)
9358#define PLL_LOCK (1 << 30)
9359#define PLL_POWER_ENABLE (1 << 27)
9360#define PLL_POWER_STATE (1 << 26)
9361#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
9362
9363#define TBT_PLL_ENABLE _MMIO(0x46020)
9364
9365#define _MG_PLL1_ENABLE 0x46030
9366#define _MG_PLL2_ENABLE 0x46034
9367#define _MG_PLL3_ENABLE 0x46038
9368#define _MG_PLL4_ENABLE 0x4603C
9369
9370#define MG_PLL_ENABLE(port) _MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
9371 _MG_PLL2_ENABLE)
9372
9373#define _MG_REFCLKIN_CTL_PORT1 0x16892C
9374#define _MG_REFCLKIN_CTL_PORT2 0x16992C
9375#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
9376#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
9377#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
9378#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
9379#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
9380 _MG_REFCLKIN_CTL_PORT1, \
9381 _MG_REFCLKIN_CTL_PORT2)
9382
9383#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
9384#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
9385#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
9386#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
9387#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
9388#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
9389#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
9390#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
9391#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
9392 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
9393 _MG_CLKTOP2_CORECLKCTL1_PORT2)
9394
9395#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
9396#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
9397#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
9398#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
9399#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
9400#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
9401#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
9402#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
9403#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
9404#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
9405#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
9406#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
9407#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
9408#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
9409#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
9410#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
9411#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
9412 _MG_CLKTOP2_HSCLKCTL_PORT1, \
9413 _MG_CLKTOP2_HSCLKCTL_PORT2)
9414
9415#define _MG_PLL_DIV0_PORT1 0x168A00
9416#define _MG_PLL_DIV0_PORT2 0x169A00
9417#define _MG_PLL_DIV0_PORT3 0x16AA00
9418#define _MG_PLL_DIV0_PORT4 0x16BA00
9419#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
9420#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
9421#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
9422#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
9423#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
9424#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
9425#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \
9426 _MG_PLL_DIV0_PORT2)
9427
9428#define _MG_PLL_DIV1_PORT1 0x168A04
9429#define _MG_PLL_DIV1_PORT2 0x169A04
9430#define _MG_PLL_DIV1_PORT3 0x16AA04
9431#define _MG_PLL_DIV1_PORT4 0x16BA04
9432#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
9433#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
9434#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
9435#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
9436#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
9437#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
9438#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
9439#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
9440#define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \
9441 _MG_PLL_DIV1_PORT2)
9442
9443#define _MG_PLL_LF_PORT1 0x168A08
9444#define _MG_PLL_LF_PORT2 0x169A08
9445#define _MG_PLL_LF_PORT3 0x16AA08
9446#define _MG_PLL_LF_PORT4 0x16BA08
9447#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
9448#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
9449#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
9450#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
9451#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
9452#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
9453#define MG_PLL_LF(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_LF_PORT1, \
9454 _MG_PLL_LF_PORT2)
9455
9456#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
9457#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
9458#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
9459#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
9460#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
9461#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
9462#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
9463#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
9464#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
9465#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
9466#define MG_PLL_FRAC_LOCK(port) _MMIO_PORT((port) - PORT_C, \
9467 _MG_PLL_FRAC_LOCK_PORT1, \
9468 _MG_PLL_FRAC_LOCK_PORT2)
9469
9470#define _MG_PLL_SSC_PORT1 0x168A10
9471#define _MG_PLL_SSC_PORT2 0x169A10
9472#define _MG_PLL_SSC_PORT3 0x16AA10
9473#define _MG_PLL_SSC_PORT4 0x16BA10
9474#define MG_PLL_SSC_EN (1 << 28)
9475#define MG_PLL_SSC_TYPE(x) ((x) << 26)
9476#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
9477#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
9478#define MG_PLL_SSC_FLLEN (1 << 9)
9479#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
9480#define MG_PLL_SSC(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_SSC_PORT1, \
9481 _MG_PLL_SSC_PORT2)
9482
9483#define _MG_PLL_BIAS_PORT1 0x168A14
9484#define _MG_PLL_BIAS_PORT2 0x169A14
9485#define _MG_PLL_BIAS_PORT3 0x16AA14
9486#define _MG_PLL_BIAS_PORT4 0x16BA14
9487#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
9488#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
9489#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
9490#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
9491#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
9492#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
9493#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
9494#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
9495#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
9496#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
9497#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
9498#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
9499#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
9500#define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_BIAS_PORT1, \
9501 _MG_PLL_BIAS_PORT2)
9502
9503#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
9504#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
9505#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
9506#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
9507#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
9508#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
9509#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
9510#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
9511#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
9512#define MG_PLL_TDC_COLDST_BIAS(port) _MMIO_PORT((port) - PORT_C, \
9513 _MG_PLL_TDC_COLDST_BIAS_PORT1, \
9514 _MG_PLL_TDC_COLDST_BIAS_PORT2)
9515
9516#define _CNL_DPLL0_CFGCR0 0x6C000
9517#define _CNL_DPLL1_CFGCR0 0x6C080
9518#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
9519#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
9520#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
9521#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
9522#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
9523#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
9524#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
9525#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
9526#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
9527#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
9528#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
9529#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
9530#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
9531#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
9532#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
9533#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
9534#define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
9535
9536#define _CNL_DPLL0_CFGCR1 0x6C004
9537#define _CNL_DPLL1_CFGCR1 0x6C084
9538#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
9539#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
9540#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
9541#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
9542#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
9543#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
9544#define DPLL_CFGCR1_KDIV_SHIFT (6)
9545#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
9546#define DPLL_CFGCR1_KDIV_1 (1 << 6)
9547#define DPLL_CFGCR1_KDIV_2 (2 << 6)
9548#define DPLL_CFGCR1_KDIV_4 (4 << 6)
9549#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
9550#define DPLL_CFGCR1_PDIV_SHIFT (2)
9551#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
9552#define DPLL_CFGCR1_PDIV_2 (1 << 2)
9553#define DPLL_CFGCR1_PDIV_3 (2 << 2)
9554#define DPLL_CFGCR1_PDIV_5 (4 << 2)
9555#define DPLL_CFGCR1_PDIV_7 (8 << 2)
9556#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
9557#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
9558#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
9559
9560#define _ICL_DPLL0_CFGCR0 0x164000
9561#define _ICL_DPLL1_CFGCR0 0x164080
9562#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
9563 _ICL_DPLL1_CFGCR0)
9564
9565#define _ICL_DPLL0_CFGCR1 0x164004
9566#define _ICL_DPLL1_CFGCR1 0x164084
9567#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
9568 _ICL_DPLL1_CFGCR1)
9569
9570
9571#define BXT_DE_PLL_CTL _MMIO(0x6d000)
9572#define BXT_DE_PLL_RATIO(x) (x)
9573#define BXT_DE_PLL_RATIO_MASK 0xff
9574
9575#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
9576#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
9577#define BXT_DE_PLL_LOCK (1 << 30)
9578#define CNL_CDCLK_PLL_RATIO(x) (x)
9579#define CNL_CDCLK_PLL_RATIO_MASK 0xff
9580
9581
9582#define DC_STATE_EN _MMIO(0x45504)
9583#define DC_STATE_DISABLE 0
9584#define DC_STATE_EN_UPTO_DC5 (1 << 0)
9585#define DC_STATE_EN_DC9 (1 << 3)
9586#define DC_STATE_EN_UPTO_DC6 (2 << 0)
9587#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
9588
9589#define DC_STATE_DEBUG _MMIO(0x45520)
9590#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
9591#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
9592
9593#define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
9594#define BXT_REQ_DATA_MASK 0x3F
9595#define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12
9596#define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12)
9597#define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333
9598
9599#define BXT_D_CR_DRP0_DUNIT8 0x1000
9600#define BXT_D_CR_DRP0_DUNIT9 0x1200
9601#define BXT_D_CR_DRP0_DUNIT_START 8
9602#define BXT_D_CR_DRP0_DUNIT_END 11
9603#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
9604 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
9605 BXT_D_CR_DRP0_DUNIT9))
9606#define BXT_DRAM_RANK_MASK 0x3
9607#define BXT_DRAM_RANK_SINGLE 0x1
9608#define BXT_DRAM_RANK_DUAL 0x3
9609#define BXT_DRAM_WIDTH_MASK (0x3 << 4)
9610#define BXT_DRAM_WIDTH_SHIFT 4
9611#define BXT_DRAM_WIDTH_X8 (0x0 << 4)
9612#define BXT_DRAM_WIDTH_X16 (0x1 << 4)
9613#define BXT_DRAM_WIDTH_X32 (0x2 << 4)
9614#define BXT_DRAM_WIDTH_X64 (0x3 << 4)
9615#define BXT_DRAM_SIZE_MASK (0x7 << 6)
9616#define BXT_DRAM_SIZE_SHIFT 6
9617#define BXT_DRAM_SIZE_4GB (0x0 << 6)
9618#define BXT_DRAM_SIZE_6GB (0x1 << 6)
9619#define BXT_DRAM_SIZE_8GB (0x2 << 6)
9620#define BXT_DRAM_SIZE_12GB (0x3 << 6)
9621#define BXT_DRAM_SIZE_16GB (0x4 << 6)
9622
9623#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
9624#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
9625#define SKL_REQ_DATA_MASK (0xF << 0)
9626
9627#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
9628#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
9629#define SKL_DRAM_S_SHIFT 16
9630#define SKL_DRAM_SIZE_MASK 0x3F
9631#define SKL_DRAM_WIDTH_MASK (0x3 << 8)
9632#define SKL_DRAM_WIDTH_SHIFT 8
9633#define SKL_DRAM_WIDTH_X8 (0x0 << 8)
9634#define SKL_DRAM_WIDTH_X16 (0x1 << 8)
9635#define SKL_DRAM_WIDTH_X32 (0x2 << 8)
9636#define SKL_DRAM_RANK_MASK (0x1 << 10)
9637#define SKL_DRAM_RANK_SHIFT 10
9638#define SKL_DRAM_RANK_SINGLE (0x0 << 10)
9639#define SKL_DRAM_RANK_DUAL (0x1 << 10)
9640
9641
9642
9643#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
9644#define D_COMP_BDW _MMIO(0x138144)
9645#define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
9646#define D_COMP_COMP_FORCE (1 << 8)
9647#define D_COMP_COMP_DISABLE (1 << 0)
9648
9649
9650#define _PIPE_WM_LINETIME_A 0x45270
9651#define _PIPE_WM_LINETIME_B 0x45274
9652#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
9653#define PIPE_WM_LINETIME_MASK (0x1ff)
9654#define PIPE_WM_LINETIME_TIME(x) ((x))
9655#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16)
9656#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16)
9657
9658
9659#define SFUSE_STRAP _MMIO(0xc2014)
9660#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
9661#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
9662#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
9663#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
9664#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
9665#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
9666#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
9667#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
9668
9669#define WM_MISC _MMIO(0x45260)
9670#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
9671
9672#define WM_DBG _MMIO(0x45280)
9673#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
9674#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
9675#define WM_DBG_DISALLOW_SPRITE (1 << 2)
9676
9677
9678#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
9679#define _PIPE_A_CSC_COEFF_BY 0x49014
9680#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
9681#define _PIPE_A_CSC_COEFF_BU 0x4901c
9682#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
9683#define _PIPE_A_CSC_COEFF_BV 0x49024
9684#define _PIPE_A_CSC_MODE 0x49028
9685#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
9686#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
9687#define CSC_MODE_YUV_TO_RGB (1 << 0)
9688#define _PIPE_A_CSC_PREOFF_HI 0x49030
9689#define _PIPE_A_CSC_PREOFF_ME 0x49034
9690#define _PIPE_A_CSC_PREOFF_LO 0x49038
9691#define _PIPE_A_CSC_POSTOFF_HI 0x49040
9692#define _PIPE_A_CSC_POSTOFF_ME 0x49044
9693#define _PIPE_A_CSC_POSTOFF_LO 0x49048
9694
9695#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
9696#define _PIPE_B_CSC_COEFF_BY 0x49114
9697#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
9698#define _PIPE_B_CSC_COEFF_BU 0x4911c
9699#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
9700#define _PIPE_B_CSC_COEFF_BV 0x49124
9701#define _PIPE_B_CSC_MODE 0x49128
9702#define _PIPE_B_CSC_PREOFF_HI 0x49130
9703#define _PIPE_B_CSC_PREOFF_ME 0x49134
9704#define _PIPE_B_CSC_PREOFF_LO 0x49138
9705#define _PIPE_B_CSC_POSTOFF_HI 0x49140
9706#define _PIPE_B_CSC_POSTOFF_ME 0x49144
9707#define _PIPE_B_CSC_POSTOFF_LO 0x49148
9708
9709#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
9710#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
9711#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
9712#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
9713#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
9714#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
9715#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
9716#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
9717#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
9718#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
9719#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
9720#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
9721#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
9722
9723
9724#define _PAL_PREC_INDEX_A 0x4A400
9725#define _PAL_PREC_INDEX_B 0x4AC00
9726#define _PAL_PREC_INDEX_C 0x4B400
9727#define PAL_PREC_10_12_BIT (0 << 31)
9728#define PAL_PREC_SPLIT_MODE (1 << 31)
9729#define PAL_PREC_AUTO_INCREMENT (1 << 15)
9730#define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
9731#define _PAL_PREC_DATA_A 0x4A404
9732#define _PAL_PREC_DATA_B 0x4AC04
9733#define _PAL_PREC_DATA_C 0x4B404
9734#define _PAL_PREC_GC_MAX_A 0x4A410
9735#define _PAL_PREC_GC_MAX_B 0x4AC10
9736#define _PAL_PREC_GC_MAX_C 0x4B410
9737#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
9738#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
9739#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
9740#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
9741#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
9742#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
9743
9744#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
9745#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
9746#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
9747#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
9748
9749#define _PRE_CSC_GAMC_INDEX_A 0x4A484
9750#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
9751#define _PRE_CSC_GAMC_INDEX_C 0x4B484
9752#define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
9753#define _PRE_CSC_GAMC_DATA_A 0x4A488
9754#define _PRE_CSC_GAMC_DATA_B 0x4AC88
9755#define _PRE_CSC_GAMC_DATA_C 0x4B488
9756
9757#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
9758#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
9759
9760
9761#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
9762#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
9763#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
9764#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
9765#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
9766#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
9767#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
9768#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
9769#define CGM_PIPE_MODE_GAMMA (1 << 2)
9770#define CGM_PIPE_MODE_CSC (1 << 1)
9771#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
9772
9773#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
9774#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
9775#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
9776#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
9777#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
9778#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
9779#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
9780#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
9781
9782#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
9783#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
9784#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
9785#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
9786#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
9787#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
9788#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
9789#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
9790
9791
9792
9793#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c)
9794#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
9795
9796#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
9797#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
9798#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
9799#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
9800
9801#define _ICL_DSI_ESC_CLK_DIV0 0x6b090
9802#define _ICL_DSI_ESC_CLK_DIV1 0x6b890
9803#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \
9804 _ICL_DSI_ESC_CLK_DIV0, \
9805 _ICL_DSI_ESC_CLK_DIV1)
9806#define _ICL_DPHY_ESC_CLK_DIV0 0x162190
9807#define _ICL_DPHY_ESC_CLK_DIV1 0x6C190
9808#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \
9809 _ICL_DPHY_ESC_CLK_DIV0, \
9810 _ICL_DPHY_ESC_CLK_DIV1)
9811#define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16)
9812#define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
9813#define ICL_ESC_CLK_DIV_MASK 0x1ff
9814#define ICL_ESC_CLK_DIV_SHIFT 0
9815#define DSI_MAX_ESC_CLK 20000
9816
9817
9818#define GEN4_TIMESTAMP _MMIO(0x2358)
9819#define ILK_TIMESTAMP_HI _MMIO(0x70070)
9820#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
9821
9822#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
9823#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
9824#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
9825#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
9826#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
9827
9828#define _PIPE_FRMTMSTMP_A 0x70048
9829#define PIPE_FRMTMSTMP(pipe) \
9830 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
9831
9832
9833#define BXT_MAX_VAR_OUTPUT_KHZ 39500
9834
9835#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
9836#define BXT_MIPI1_DIV_SHIFT 26
9837#define BXT_MIPI2_DIV_SHIFT 10
9838#define BXT_MIPI_DIV_SHIFT(port) \
9839 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
9840 BXT_MIPI2_DIV_SHIFT)
9841
9842
9843#define BXT_MIPI1_TX_ESCLK_SHIFT 26
9844#define BXT_MIPI2_TX_ESCLK_SHIFT 10
9845#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
9846 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
9847 BXT_MIPI2_TX_ESCLK_SHIFT)
9848#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
9849#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
9850#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
9851 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
9852 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
9853#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
9854 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
9855
9856#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
9857#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
9858#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
9859 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
9860 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
9861#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
9862#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
9863#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
9864 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
9865 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
9866#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
9867 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
9868
9869#define BXT_MIPI1_8X_BY3_SHIFT 19
9870#define BXT_MIPI2_8X_BY3_SHIFT 3
9871#define BXT_MIPI_8X_BY3_SHIFT(port) \
9872 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
9873 BXT_MIPI2_8X_BY3_SHIFT)
9874#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
9875#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
9876#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
9877 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
9878 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
9879#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
9880 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
9881
9882#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
9883#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
9884#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
9885 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
9886 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
9887#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
9888#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
9889#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
9890 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
9891 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
9892#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
9893 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
9894
9895#define RX_DIVIDER_BIT_1_2 0x3
9896#define RX_DIVIDER_BIT_3_4 0xC
9897
9898
9899#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
9900#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
9901#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
9902 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
9903
9904#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
9905#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
9906#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
9907 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
9908
9909#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
9910#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
9911#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
9912 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
9913
9914#define BXT_DSI_PLL_CTL _MMIO(0x161000)
9915#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
9916#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9917#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9918#define BXT_DSIC_16X_BY1 (0 << 10)
9919#define BXT_DSIC_16X_BY2 (1 << 10)
9920#define BXT_DSIC_16X_BY3 (2 << 10)
9921#define BXT_DSIC_16X_BY4 (3 << 10)
9922#define BXT_DSIC_16X_MASK (3 << 10)
9923#define BXT_DSIA_16X_BY1 (0 << 8)
9924#define BXT_DSIA_16X_BY2 (1 << 8)
9925#define BXT_DSIA_16X_BY3 (2 << 8)
9926#define BXT_DSIA_16X_BY4 (3 << 8)
9927#define BXT_DSIA_16X_MASK (3 << 8)
9928#define BXT_DSI_FREQ_SEL_SHIFT 8
9929#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
9930
9931#define BXT_DSI_PLL_RATIO_MAX 0x7D
9932#define BXT_DSI_PLL_RATIO_MIN 0x22
9933#define GLK_DSI_PLL_RATIO_MAX 0x6F
9934#define GLK_DSI_PLL_RATIO_MIN 0x22
9935#define BXT_DSI_PLL_RATIO_MASK 0xFF
9936#define BXT_REF_CLOCK_KHZ 19200
9937
9938#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
9939#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
9940#define BXT_DSI_PLL_LOCKED (1 << 30)
9941
9942#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
9943#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
9944#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
9945
9946
9947#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
9948#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
9949#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
9950
9951
9952#define _ICL_DSI_IO_MODECTL_0 0x6B094
9953#define _ICL_DSI_IO_MODECTL_1 0x6B894
9954#define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \
9955 _ICL_DSI_IO_MODECTL_0, \
9956 _ICL_DSI_IO_MODECTL_1)
9957#define COMBO_PHY_MODE_DSI (1 << 0)
9958
9959#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
9960#define STAP_SELECT (1 << 0)
9961
9962#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
9963#define HS_IO_CTRL_SELECT (1 << 0)
9964
9965#define DPI_ENABLE (1 << 31)
9966#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
9967#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
9968#define DUAL_LINK_MODE_SHIFT 26
9969#define DUAL_LINK_MODE_MASK (1 << 26)
9970#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
9971#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
9972#define DITHERING_ENABLE (1 << 25)
9973#define FLOPPED_HSTX (1 << 23)
9974#define DE_INVERT (1 << 19)
9975#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
9976#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
9977#define AFE_LATCHOUT (1 << 17)
9978#define LP_OUTPUT_HOLD (1 << 16)
9979#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
9980#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
9981#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
9982#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
9983#define CSB_SHIFT 9
9984#define CSB_MASK (3 << 9)
9985#define CSB_20MHZ (0 << 9)
9986#define CSB_10MHZ (1 << 9)
9987#define CSB_40MHZ (2 << 9)
9988#define BANDGAP_MASK (1 << 8)
9989#define BANDGAP_PNW_CIRCUIT (0 << 8)
9990#define BANDGAP_LNC_CIRCUIT (1 << 8)
9991#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
9992#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
9993#define TEARING_EFFECT_DELAY (1 << 4)
9994#define TEARING_EFFECT_SHIFT 2
9995#define TEARING_EFFECT_MASK (3 << 2)
9996#define TEARING_EFFECT_OFF (0 << 2)
9997#define TEARING_EFFECT_DSI (1 << 2)
9998#define TEARING_EFFECT_GPIO (2 << 2)
9999#define LANE_CONFIGURATION_SHIFT 0
10000#define LANE_CONFIGURATION_MASK (3 << 0)
10001#define LANE_CONFIGURATION_4LANE (0 << 0)
10002#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
10003#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
10004
10005#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
10006#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
10007#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
10008#define TEARING_EFFECT_DELAY_SHIFT 0
10009#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
10010
10011
10012#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
10013
10014
10015
10016#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
10017#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
10018#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
10019#define BUS_POSSESSION (1 << 3)
10020#define ULPS_STATE_MASK (3 << 1)
10021#define ULPS_STATE_ENTER (2 << 1)
10022#define ULPS_STATE_EXIT (1 << 1)
10023#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
10024#define DEVICE_READY (1 << 0)
10025
10026#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
10027#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
10028#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
10029#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
10030#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
10031#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
10032#define TEARING_EFFECT (1 << 31)
10033#define SPL_PKT_SENT_INTERRUPT (1 << 30)
10034#define GEN_READ_DATA_AVAIL (1 << 29)
10035#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
10036#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
10037#define RX_PROT_VIOLATION (1 << 26)
10038#define RX_INVALID_TX_LENGTH (1 << 25)
10039#define ACK_WITH_NO_ERROR (1 << 24)
10040#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
10041#define LP_RX_TIMEOUT (1 << 22)
10042#define HS_TX_TIMEOUT (1 << 21)
10043#define DPI_FIFO_UNDERRUN (1 << 20)
10044#define LOW_CONTENTION (1 << 19)
10045#define HIGH_CONTENTION (1 << 18)
10046#define TXDSI_VC_ID_INVALID (1 << 17)
10047#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
10048#define TXCHECKSUM_ERROR (1 << 15)
10049#define TXECC_MULTIBIT_ERROR (1 << 14)
10050#define TXECC_SINGLE_BIT_ERROR (1 << 13)
10051#define TXFALSE_CONTROL_ERROR (1 << 12)
10052#define RXDSI_VC_ID_INVALID (1 << 11)
10053#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
10054#define RXCHECKSUM_ERROR (1 << 9)
10055#define RXECC_MULTIBIT_ERROR (1 << 8)
10056#define RXECC_SINGLE_BIT_ERROR (1 << 7)
10057#define RXFALSE_CONTROL_ERROR (1 << 6)
10058#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
10059#define RX_LP_TX_SYNC_ERROR (1 << 4)
10060#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
10061#define RXEOT_SYNC_ERROR (1 << 2)
10062#define RXSOT_SYNC_ERROR (1 << 1)
10063#define RXSOT_ERROR (1 << 0)
10064
10065#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
10066#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
10067#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
10068#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
10069#define CMD_MODE_NOT_SUPPORTED (0 << 13)
10070#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
10071#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
10072#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
10073#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
10074#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
10075#define VID_MODE_FORMAT_MASK (0xf << 7)
10076#define VID_MODE_NOT_SUPPORTED (0 << 7)
10077#define VID_MODE_FORMAT_RGB565 (1 << 7)
10078#define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
10079#define VID_MODE_FORMAT_RGB666 (3 << 7)
10080#define VID_MODE_FORMAT_RGB888 (4 << 7)
10081#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
10082#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
10083#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
10084#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
10085#define DATA_LANES_PRG_REG_SHIFT 0
10086#define DATA_LANES_PRG_REG_MASK (7 << 0)
10087
10088#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
10089#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
10090#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
10091#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
10092
10093#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
10094#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
10095#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
10096#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
10097
10098#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
10099#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
10100#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
10101#define TURN_AROUND_TIMEOUT_MASK 0x3f
10102
10103#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
10104#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
10105#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
10106#define DEVICE_RESET_TIMER_MASK 0xffff
10107
10108#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
10109#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
10110#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
10111#define VERTICAL_ADDRESS_SHIFT 16
10112#define VERTICAL_ADDRESS_MASK (0xffff << 16)
10113#define HORIZONTAL_ADDRESS_SHIFT 0
10114#define HORIZONTAL_ADDRESS_MASK 0xffff
10115
10116#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
10117#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
10118#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
10119#define DBI_FIFO_EMPTY_HALF (0 << 0)
10120#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
10121#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
10122
10123
10124#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
10125#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
10126#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
10127
10128#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
10129#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
10130#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
10131
10132#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
10133#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
10134#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
10135
10136#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
10137#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
10138#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
10139
10140#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
10141#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
10142#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
10143
10144#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
10145#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
10146#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
10147
10148#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
10149#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
10150#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
10151
10152#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
10153#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
10154#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
10155
10156
10157
10158#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
10159#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
10160#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
10161#define DPI_LP_MODE (1 << 6)
10162#define BACKLIGHT_OFF (1 << 5)
10163#define BACKLIGHT_ON (1 << 4)
10164#define COLOR_MODE_OFF (1 << 3)
10165#define COLOR_MODE_ON (1 << 2)
10166#define TURN_ON (1 << 1)
10167#define SHUTDOWN (1 << 0)
10168
10169#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
10170#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
10171#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
10172#define COMMAND_BYTE_SHIFT 0
10173#define COMMAND_BYTE_MASK (0x3f << 0)
10174
10175#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
10176#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
10177#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
10178#define MASTER_INIT_TIMER_SHIFT 0
10179#define MASTER_INIT_TIMER_MASK (0xffff << 0)
10180
10181#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
10182#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
10183#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
10184 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
10185#define MAX_RETURN_PKT_SIZE_SHIFT 0
10186#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
10187
10188#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
10189#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
10190#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
10191#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
10192#define DISABLE_VIDEO_BTA (1 << 3)
10193#define IP_TG_CONFIG (1 << 2)
10194#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
10195#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
10196#define VIDEO_MODE_BURST (3 << 0)
10197
10198#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
10199#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
10200#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
10201#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
10202#define BXT_DPHY_DEFEATURE_EN (1 << 8)
10203#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
10204#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
10205#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
10206#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
10207#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
10208#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
10209#define CLOCKSTOP (1 << 1)
10210#define EOT_DISABLE (1 << 0)
10211
10212#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
10213#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
10214#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
10215#define LP_BYTECLK_SHIFT 0
10216#define LP_BYTECLK_MASK (0xffff << 0)
10217
10218#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
10219#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
10220#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
10221
10222#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
10223#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
10224#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
10225
10226
10227#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
10228#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
10229#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
10230
10231
10232#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
10233#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
10234#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
10235
10236#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
10237#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
10238#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
10239#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
10240#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
10241#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
10242#define LONG_PACKET_WORD_COUNT_SHIFT 8
10243#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
10244#define SHORT_PACKET_PARAM_SHIFT 8
10245#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
10246#define VIRTUAL_CHANNEL_SHIFT 6
10247#define VIRTUAL_CHANNEL_MASK (3 << 6)
10248#define DATA_TYPE_SHIFT 0
10249#define DATA_TYPE_MASK (0x3f << 0)
10250
10251
10252#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
10253#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
10254#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
10255#define DPI_FIFO_EMPTY (1 << 28)
10256#define DBI_FIFO_EMPTY (1 << 27)
10257#define LP_CTRL_FIFO_EMPTY (1 << 26)
10258#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
10259#define LP_CTRL_FIFO_FULL (1 << 24)
10260#define HS_CTRL_FIFO_EMPTY (1 << 18)
10261#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
10262#define HS_CTRL_FIFO_FULL (1 << 16)
10263#define LP_DATA_FIFO_EMPTY (1 << 10)
10264#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
10265#define LP_DATA_FIFO_FULL (1 << 8)
10266#define HS_DATA_FIFO_EMPTY (1 << 2)
10267#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
10268#define HS_DATA_FIFO_FULL (1 << 0)
10269
10270#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
10271#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
10272#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
10273#define DBI_HS_LP_MODE_MASK (1 << 0)
10274#define DBI_LP_MODE (1 << 0)
10275#define DBI_HS_MODE (0 << 0)
10276
10277#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
10278#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
10279#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
10280#define EXIT_ZERO_COUNT_SHIFT 24
10281#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
10282#define TRAIL_COUNT_SHIFT 16
10283#define TRAIL_COUNT_MASK (0x1f << 16)
10284#define CLK_ZERO_COUNT_SHIFT 8
10285#define CLK_ZERO_COUNT_MASK (0xff << 8)
10286#define PREPARE_COUNT_SHIFT 0
10287#define PREPARE_COUNT_MASK (0x3f << 0)
10288
10289#define _ICL_DSI_T_INIT_MASTER_0 0x6b088
10290#define _ICL_DSI_T_INIT_MASTER_1 0x6b888
10291#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \
10292 _ICL_DSI_T_INIT_MASTER_0,\
10293 _ICL_DSI_T_INIT_MASTER_1)
10294
10295
10296#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
10297#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
10298#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
10299
10300#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
10301#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
10302#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
10303#define LP_HS_SSW_CNT_SHIFT 16
10304#define LP_HS_SSW_CNT_MASK (0xffff << 16)
10305#define HS_LP_PWR_SW_CNT_SHIFT 0
10306#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
10307
10308#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
10309#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
10310#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
10311#define STOP_STATE_STALL_COUNTER_SHIFT 0
10312#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
10313
10314#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
10315#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
10316#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
10317#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
10318#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
10319#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
10320#define RX_CONTENTION_DETECTED (1 << 0)
10321
10322
10323#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
10324#define DBI_TYPEC_ENABLE (1 << 31)
10325#define DBI_TYPEC_WIP (1 << 30)
10326#define DBI_TYPEC_OPTION_SHIFT 28
10327#define DBI_TYPEC_OPTION_MASK (3 << 28)
10328#define DBI_TYPEC_FREQ_SHIFT 24
10329#define DBI_TYPEC_FREQ_MASK (0xf << 24)
10330#define DBI_TYPEC_OVERRIDE (1 << 8)
10331#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
10332#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
10333
10334
10335
10336
10337#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
10338#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
10339#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
10340#define ESCAPE_CLOCK_DIVIDER_SHIFT 5
10341#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
10342#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
10343#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
10344#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
10345#define READ_REQUEST_PRIORITY_SHIFT 3
10346#define READ_REQUEST_PRIORITY_MASK (3 << 3)
10347#define READ_REQUEST_PRIORITY_LOW (0 << 3)
10348#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
10349#define RGB_FLIP_TO_BGR (1 << 2)
10350
10351#define BXT_PIPE_SELECT_SHIFT 7
10352#define BXT_PIPE_SELECT_MASK (7 << 7)
10353#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
10354#define GLK_PHY_STATUS_PORT_READY (1 << 31)
10355#define GLK_ULPS_NOT_ACTIVE (1 << 30)
10356#define GLK_MIPIIO_RESET_RELEASED (1 << 28)
10357#define GLK_CLOCK_LANE_STOP_STATE (1 << 27)
10358#define GLK_DATA_LANE_STOP_STATE (1 << 26)
10359#define GLK_LP_WAKE (1 << 22)
10360#define GLK_LP11_LOW_PWR_MODE (1 << 21)
10361#define GLK_LP00_LOW_PWR_MODE (1 << 20)
10362#define GLK_FIREWALL_ENABLE (1 << 16)
10363#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
10364#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
10365#define BXT_DSC_ENABLE (1 << 3)
10366#define BXT_RGB_FLIP (1 << 2)
10367#define GLK_MIPIIO_PORT_POWERED (1 << 1)
10368#define GLK_MIPIIO_ENABLE (1 << 0)
10369
10370#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
10371#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
10372#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
10373#define DATA_MEM_ADDRESS_SHIFT 5
10374#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
10375#define DATA_VALID (1 << 0)
10376
10377#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
10378#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
10379#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
10380#define DATA_LENGTH_SHIFT 0
10381#define DATA_LENGTH_MASK (0xfffff << 0)
10382
10383#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
10384#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
10385#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
10386#define COMMAND_MEM_ADDRESS_SHIFT 5
10387#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
10388#define AUTO_PWG_ENABLE (1 << 2)
10389#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
10390#define COMMAND_VALID (1 << 0)
10391
10392#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
10393#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
10394#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
10395#define COMMAND_LENGTH_SHIFT(n) (8 * (n))
10396#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
10397
10398#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
10399#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
10400#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n))
10401
10402#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
10403#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
10404#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
10405#define READ_DATA_VALID(n) (1 << (n))
10406
10407
10408#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
10409#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
10410
10411
10412#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4)
10413
10414#define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4)
10415#define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4)
10416#define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4)
10417#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4)
10418#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4)
10419
10420#define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
10421
10422#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
10423#define PMFLUSHDONE_LNICRSDROP (1 << 20)
10424#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
10425#define PMFLUSHDONE_LNEBLK (1 << 22)
10426
10427
10428#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
10429#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F
10430#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF
10431#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F
10432#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF
10433
10434#define MMCD_MISC_CTRL _MMIO(0x4ddc)
10435#define MMCD_PCLA (1 << 31)
10436#define MMCD_HOTSPOT_EN (1 << 27)
10437
10438#define _ICL_PHY_MISC_A 0x64C00
10439#define _ICL_PHY_MISC_B 0x64C04
10440#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
10441 _ICL_PHY_MISC_B)
10442#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
10443
10444
10445#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
10446#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
10447#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
10448#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
10449#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
10450#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
10451#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10452 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
10453 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
10454#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10455 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
10456 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
10457#define DSC_VBR_ENABLE (1 << 19)
10458#define DSC_422_ENABLE (1 << 18)
10459#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
10460#define DSC_BLOCK_PREDICTION (1 << 16)
10461#define DSC_LINE_BUF_DEPTH_SHIFT 12
10462#define DSC_BPC_SHIFT 8
10463#define DSC_VER_MIN_SHIFT 4
10464#define DSC_VER_MAJ (0x1 << 0)
10465
10466#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
10467#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
10468#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
10469#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
10470#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
10471#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
10472#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10473 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
10474 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
10475#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10476 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
10477 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
10478#define DSC_BPP(bpp) ((bpp) << 0)
10479
10480#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
10481#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
10482#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
10483#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
10484#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
10485#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
10486#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10487 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
10488 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
10489#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10490 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
10491 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
10492#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
10493#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
10494
10495#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
10496#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
10497#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
10498#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
10499#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
10500#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
10501#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10502 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
10503 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
10504#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10505 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
10506 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
10507#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
10508#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
10509
10510#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
10511#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
10512#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
10513#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
10514#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
10515#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
10516#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10517 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
10518 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
10519#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10520 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
10521 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
10522#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
10523#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
10524
10525#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
10526#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
10527#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
10528#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
10529#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
10530#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
10531#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10532 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
10533 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
10534#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10535 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
10536 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
10537#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
10538#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
10539
10540#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
10541#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
10542#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
10543#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
10544#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
10545#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
10546#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10547 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
10548 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
10549#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10550 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
10551 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
10552#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
10553#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
10554#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
10555#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
10556
10557#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
10558#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
10559#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
10560#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
10561#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
10562#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
10563#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10564 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
10565 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
10566#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10567 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
10568 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
10569#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
10570#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
10571
10572#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
10573#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
10574#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
10575#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
10576#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
10577#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
10578#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10579 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
10580 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
10581#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10582 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
10583 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
10584#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
10585#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
10586
10587#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
10588#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
10589#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
10590#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
10591#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
10592#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
10593#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10594 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
10595 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
10596#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10597 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
10598 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
10599#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
10600#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
10601
10602#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
10603#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
10604#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
10605#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
10606#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
10607#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
10608#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10609 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
10610 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
10611#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10612 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
10613 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
10614#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
10615#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
10616#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
10617#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
10618
10619#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
10620#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
10621#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
10622#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
10623#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
10624#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
10625#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10626 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
10627 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
10628#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10629 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
10630 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
10631
10632#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
10633#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
10634#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
10635#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
10636#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
10637#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
10638#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10639 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
10640 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
10641#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10642 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
10643 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
10644
10645#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
10646#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
10647#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
10648#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
10649#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
10650#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
10651#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10652 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
10653 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
10654#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10655 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
10656 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
10657
10658#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
10659#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
10660#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
10661#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
10662#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
10663#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
10664#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10665 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
10666 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
10667#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10668 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
10669 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
10670
10671#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
10672#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
10673#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
10674#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
10675#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
10676#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
10677#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10678 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
10679 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
10680#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10681 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
10682 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
10683
10684#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
10685#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
10686#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
10687#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
10688#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
10689#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
10690#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10691 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
10692 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
10693#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10694 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
10695 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
10696#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
10697#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
10698
10699
10700#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
10701#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
10702#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
10703#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
10704#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
10705#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
10706#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
10707#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
10708#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
10709#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
10710#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
10711#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
10712#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10713 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
10714 _ICL_DSC0_RC_BUF_THRESH_0_PC)
10715#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10716 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
10717 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
10718#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10719 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
10720 _ICL_DSC1_RC_BUF_THRESH_0_PC)
10721#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10722 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
10723 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
10724
10725#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
10726#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
10727#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
10728#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
10729#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
10730#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
10731#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
10732#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
10733#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
10734#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
10735#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
10736#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
10737#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10738 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
10739 _ICL_DSC0_RC_BUF_THRESH_1_PC)
10740#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10741 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
10742 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
10743#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10744 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
10745 _ICL_DSC1_RC_BUF_THRESH_1_PC)
10746#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10747 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
10748 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
10749
10750#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
10751#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
10752#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
10753#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
10754#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
10755#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
10756
10757#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
10758#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
10759
10760#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
10761#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
10762
10763#endif
10764