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28#include <drm/drm_dp_helper.h>
29#include <drm/drmP.h>
30#include <drm/i915_drm.h>
31#include "i915_drv.h"
32
33#define _INTEL_BIOS_PRIVATE
34#include "intel_vbt_defs.h"
35
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57
58#define SLAVE_ADDR1 0x70
59#define SLAVE_ADDR2 0x72
60
61
62static u32 _get_blocksize(const u8 *block_base)
63{
64
65 if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3)
66 return *((const u32 *)(block_base + 4));
67 else
68 return *((const u16 *)(block_base + 1));
69}
70
71
72static u32 get_blocksize(const void *block_data)
73{
74 return _get_blocksize(block_data - 3);
75}
76
77static const void *
78find_section(const void *_bdb, int section_id)
79{
80 const struct bdb_header *bdb = _bdb;
81 const u8 *base = _bdb;
82 int index = 0;
83 u32 total, current_size;
84 u8 current_id;
85
86
87 index += bdb->header_size;
88 total = bdb->bdb_size;
89
90
91 while (index + 3 < total) {
92 current_id = *(base + index);
93 current_size = _get_blocksize(base + index);
94 index += 3;
95
96 if (index + current_size > total)
97 return NULL;
98
99 if (current_id == section_id)
100 return base + index;
101
102 index += current_size;
103 }
104
105 return NULL;
106}
107
108static void
109fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
110 const struct lvds_dvo_timing *dvo_timing)
111{
112 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
113 dvo_timing->hactive_lo;
114 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
115 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
116 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
117 ((dvo_timing->hsync_pulse_width_hi << 8) |
118 dvo_timing->hsync_pulse_width_lo);
119 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
120 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
121
122 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
123 dvo_timing->vactive_lo;
124 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
125 ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
126 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
127 ((dvo_timing->vsync_pulse_width_hi << 4) |
128 dvo_timing->vsync_pulse_width_lo);
129 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
130 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
131 panel_fixed_mode->clock = dvo_timing->clock * 10;
132 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
133
134 if (dvo_timing->hsync_positive)
135 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
136 else
137 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
138
139 if (dvo_timing->vsync_positive)
140 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
141 else
142 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
143
144 panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) |
145 dvo_timing->himage_lo;
146 panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) |
147 dvo_timing->vimage_lo;
148
149
150 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
151 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
152 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
153 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
154
155 drm_mode_set_name(panel_fixed_mode);
156}
157
158static const struct lvds_dvo_timing *
159get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data,
160 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs,
161 int index)
162{
163
164
165
166
167
168
169 int lfp_data_size =
170 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
171 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
172 int dvo_timing_offset =
173 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
174 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
175 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index;
176
177 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset);
178}
179
180
181
182
183static const struct lvds_fp_timing *
184get_lvds_fp_timing(const struct bdb_header *bdb,
185 const struct bdb_lvds_lfp_data *data,
186 const struct bdb_lvds_lfp_data_ptrs *ptrs,
187 int index)
188{
189 size_t data_ofs = (const u8 *)data - (const u8 *)bdb;
190 u16 data_size = ((const u16 *)data)[-1];
191 size_t ofs;
192
193 if (index >= ARRAY_SIZE(ptrs->ptr))
194 return NULL;
195 ofs = ptrs->ptr[index].fp_timing_offset;
196 if (ofs < data_ofs ||
197 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size)
198 return NULL;
199 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
200}
201
202
203static void
204parse_lfp_panel_data(struct drm_i915_private *dev_priv,
205 const struct bdb_header *bdb)
206{
207 const struct bdb_lvds_options *lvds_options;
208 const struct bdb_lvds_lfp_data *lvds_lfp_data;
209 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
210 const struct lvds_dvo_timing *panel_dvo_timing;
211 const struct lvds_fp_timing *fp_timing;
212 struct drm_display_mode *panel_fixed_mode;
213 int panel_type;
214 int drrs_mode;
215 int ret;
216
217 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
218 if (!lvds_options)
219 return;
220
221 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
222
223 ret = intel_opregion_get_panel_type(dev_priv);
224 if (ret >= 0) {
225 WARN_ON(ret > 0xf);
226 panel_type = ret;
227 DRM_DEBUG_KMS("Panel type: %d (OpRegion)\n", panel_type);
228 } else {
229 if (lvds_options->panel_type > 0xf) {
230 DRM_DEBUG_KMS("Invalid VBT panel type 0x%x\n",
231 lvds_options->panel_type);
232 return;
233 }
234 panel_type = lvds_options->panel_type;
235 DRM_DEBUG_KMS("Panel type: %d (VBT)\n", panel_type);
236 }
237
238 dev_priv->vbt.panel_type = panel_type;
239
240 drrs_mode = (lvds_options->dps_panel_type_bits
241 >> (panel_type * 2)) & MODE_MASK;
242
243
244
245
246
247 switch (drrs_mode) {
248 case 0:
249 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
250 DRM_DEBUG_KMS("DRRS supported mode is static\n");
251 break;
252 case 2:
253 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
254 DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
255 break;
256 default:
257 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
258 DRM_DEBUG_KMS("DRRS not supported (VBT input)\n");
259 break;
260 }
261
262 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
263 if (!lvds_lfp_data)
264 return;
265
266 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
267 if (!lvds_lfp_data_ptrs)
268 return;
269
270 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
271 lvds_lfp_data_ptrs,
272 panel_type);
273
274 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
275 if (!panel_fixed_mode)
276 return;
277
278 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
279
280 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
281
282 DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
283 drm_mode_debug_printmodeline(panel_fixed_mode);
284
285 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
286 lvds_lfp_data_ptrs,
287 panel_type);
288 if (fp_timing) {
289
290 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
291 fp_timing->y_res == panel_fixed_mode->vdisplay) {
292 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
293 DRM_DEBUG_KMS("VBT initial LVDS value %x\n",
294 dev_priv->vbt.bios_lvds_val);
295 }
296 }
297}
298
299static void
300parse_lfp_backlight(struct drm_i915_private *dev_priv,
301 const struct bdb_header *bdb)
302{
303 const struct bdb_lfp_backlight_data *backlight_data;
304 const struct bdb_lfp_backlight_data_entry *entry;
305 int panel_type = dev_priv->vbt.panel_type;
306
307 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
308 if (!backlight_data)
309 return;
310
311 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
312 DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n",
313 backlight_data->entry_size);
314 return;
315 }
316
317 entry = &backlight_data->data[panel_type];
318
319 dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
320 if (!dev_priv->vbt.backlight.present) {
321 DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n",
322 entry->type);
323 return;
324 }
325
326 dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
327 if (bdb->version >= 191 &&
328 get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
329 const struct bdb_lfp_backlight_control_method *method;
330
331 method = &backlight_data->backlight_control[panel_type];
332 dev_priv->vbt.backlight.type = method->type;
333 dev_priv->vbt.backlight.controller = method->controller;
334 }
335
336 dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
337 dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
338 dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
339 DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, "
340 "active %s, min brightness %u, level %u, controller %u\n",
341 dev_priv->vbt.backlight.pwm_freq_hz,
342 dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
343 dev_priv->vbt.backlight.min_brightness,
344 backlight_data->level[panel_type],
345 dev_priv->vbt.backlight.controller);
346}
347
348
349static void
350parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
351 const struct bdb_header *bdb)
352{
353 const struct lvds_dvo_timing *dvo_timing;
354 struct drm_display_mode *panel_fixed_mode;
355 int index;
356
357 index = i915_modparams.vbt_sdvo_panel_type;
358 if (index == -2) {
359 DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
360 return;
361 }
362
363 if (index == -1) {
364 const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
365
366 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
367 if (!sdvo_lvds_options)
368 return;
369
370 index = sdvo_lvds_options->panel_type;
371 }
372
373 dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
374 if (!dvo_timing)
375 return;
376
377 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
378 if (!panel_fixed_mode)
379 return;
380
381 fill_detail_timing_data(panel_fixed_mode, dvo_timing + index);
382
383 dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
384
385 DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");
386 drm_mode_debug_printmodeline(panel_fixed_mode);
387}
388
389static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
390 bool alternate)
391{
392 switch (INTEL_GEN(dev_priv)) {
393 case 2:
394 return alternate ? 66667 : 48000;
395 case 3:
396 case 4:
397 return alternate ? 100000 : 96000;
398 default:
399 return alternate ? 100000 : 120000;
400 }
401}
402
403static void
404parse_general_features(struct drm_i915_private *dev_priv,
405 const struct bdb_header *bdb)
406{
407 const struct bdb_general_features *general;
408
409 general = find_section(bdb, BDB_GENERAL_FEATURES);
410 if (!general)
411 return;
412
413 dev_priv->vbt.int_tv_support = general->int_tv_support;
414
415 if (bdb->version >= 155 &&
416 (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv)))
417 dev_priv->vbt.int_crt_support = general->int_crt_support;
418 dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
419 dev_priv->vbt.lvds_ssc_freq =
420 intel_bios_ssc_frequency(dev_priv, general->ssc_freq);
421 dev_priv->vbt.display_clock_mode = general->display_clock_mode;
422 dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
423 DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
424 dev_priv->vbt.int_tv_support,
425 dev_priv->vbt.int_crt_support,
426 dev_priv->vbt.lvds_use_ssc,
427 dev_priv->vbt.lvds_ssc_freq,
428 dev_priv->vbt.display_clock_mode,
429 dev_priv->vbt.fdi_rx_polarity_inverted);
430}
431
432static const struct child_device_config *
433child_device_ptr(const struct bdb_general_definitions *defs, int i)
434{
435 return (const void *) &defs->devices[i * defs->child_dev_size];
436}
437
438static void
439parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
440{
441 struct sdvo_device_mapping *mapping;
442 const struct child_device_config *child;
443 int i, count = 0;
444
445
446
447
448
449 if (!IS_GEN(dev_priv, 3, 7)) {
450 DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
451 return;
452 }
453
454 for (i = 0, count = 0; i < dev_priv->vbt.child_dev_num; i++) {
455 child = dev_priv->vbt.child_dev + i;
456
457 if (child->slave_addr != SLAVE_ADDR1 &&
458 child->slave_addr != SLAVE_ADDR2) {
459
460
461
462
463 continue;
464 }
465 if (child->dvo_port != DEVICE_PORT_DVOB &&
466 child->dvo_port != DEVICE_PORT_DVOC) {
467
468 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n");
469 continue;
470 }
471 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
472 " %s port\n",
473 child->slave_addr,
474 (child->dvo_port == DEVICE_PORT_DVOB) ?
475 "SDVOB" : "SDVOC");
476 mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1];
477 if (!mapping->initialized) {
478 mapping->dvo_port = child->dvo_port;
479 mapping->slave_addr = child->slave_addr;
480 mapping->dvo_wiring = child->dvo_wiring;
481 mapping->ddc_pin = child->ddc_pin;
482 mapping->i2c_pin = child->i2c_pin;
483 mapping->initialized = 1;
484 DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
485 mapping->dvo_port,
486 mapping->slave_addr,
487 mapping->dvo_wiring,
488 mapping->ddc_pin,
489 mapping->i2c_pin);
490 } else {
491 DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
492 "two SDVO device.\n");
493 }
494 if (child->slave2_addr) {
495
496
497 DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
498 " is a SDVO device with multiple inputs.\n");
499 }
500 count++;
501 }
502
503 if (!count) {
504
505 DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
506 }
507}
508
509static void
510parse_driver_features(struct drm_i915_private *dev_priv,
511 const struct bdb_header *bdb)
512{
513 const struct bdb_driver_features *driver;
514
515 driver = find_section(bdb, BDB_DRIVER_FEATURES);
516 if (!driver)
517 return;
518
519 if (INTEL_GEN(dev_priv) >= 5) {
520
521
522
523
524
525 if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS)
526 dev_priv->vbt.int_lvds_support = 0;
527 } else {
528
529
530
531
532
533
534
535
536
537
538
539 if (bdb->version >= 134 &&
540 driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS &&
541 driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
542 dev_priv->vbt.int_lvds_support = 0;
543 }
544
545 DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
546
547
548
549
550
551
552 if (!driver->drrs_enabled)
553 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
554 dev_priv->vbt.psr.enable = driver->psr_enabled;
555}
556
557static void
558parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
559{
560 const struct bdb_edp *edp;
561 const struct edp_power_seq *edp_pps;
562 const struct edp_fast_link_params *edp_link_params;
563 int panel_type = dev_priv->vbt.panel_type;
564
565 edp = find_section(bdb, BDB_EDP);
566 if (!edp)
567 return;
568
569 switch ((edp->color_depth >> (panel_type * 2)) & 3) {
570 case EDP_18BPP:
571 dev_priv->vbt.edp.bpp = 18;
572 break;
573 case EDP_24BPP:
574 dev_priv->vbt.edp.bpp = 24;
575 break;
576 case EDP_30BPP:
577 dev_priv->vbt.edp.bpp = 30;
578 break;
579 }
580
581
582 edp_pps = &edp->power_seqs[panel_type];
583 edp_link_params = &edp->fast_link_params[panel_type];
584
585 dev_priv->vbt.edp.pps = *edp_pps;
586
587 switch (edp_link_params->rate) {
588 case EDP_RATE_1_62:
589 dev_priv->vbt.edp.rate = DP_LINK_BW_1_62;
590 break;
591 case EDP_RATE_2_7:
592 dev_priv->vbt.edp.rate = DP_LINK_BW_2_7;
593 break;
594 default:
595 DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
596 edp_link_params->rate);
597 break;
598 }
599
600 switch (edp_link_params->lanes) {
601 case EDP_LANE_1:
602 dev_priv->vbt.edp.lanes = 1;
603 break;
604 case EDP_LANE_2:
605 dev_priv->vbt.edp.lanes = 2;
606 break;
607 case EDP_LANE_4:
608 dev_priv->vbt.edp.lanes = 4;
609 break;
610 default:
611 DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
612 edp_link_params->lanes);
613 break;
614 }
615
616 switch (edp_link_params->preemphasis) {
617 case EDP_PREEMPHASIS_NONE:
618 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
619 break;
620 case EDP_PREEMPHASIS_3_5dB:
621 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
622 break;
623 case EDP_PREEMPHASIS_6dB:
624 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
625 break;
626 case EDP_PREEMPHASIS_9_5dB:
627 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
628 break;
629 default:
630 DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
631 edp_link_params->preemphasis);
632 break;
633 }
634
635 switch (edp_link_params->vswing) {
636 case EDP_VSWING_0_4V:
637 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
638 break;
639 case EDP_VSWING_0_6V:
640 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
641 break;
642 case EDP_VSWING_0_8V:
643 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
644 break;
645 case EDP_VSWING_1_2V:
646 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
647 break;
648 default:
649 DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
650 edp_link_params->vswing);
651 break;
652 }
653
654 if (bdb->version >= 173) {
655 u8 vswing;
656
657
658 if (i915_modparams.edp_vswing) {
659 dev_priv->vbt.edp.low_vswing =
660 i915_modparams.edp_vswing == 1;
661 } else {
662 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
663 dev_priv->vbt.edp.low_vswing = vswing == 0;
664 }
665 }
666}
667
668static void
669parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
670{
671 const struct bdb_psr *psr;
672 const struct psr_table *psr_table;
673 int panel_type = dev_priv->vbt.panel_type;
674
675 psr = find_section(bdb, BDB_PSR);
676 if (!psr) {
677 DRM_DEBUG_KMS("No PSR BDB found.\n");
678 return;
679 }
680
681 psr_table = &psr->psr_table[panel_type];
682
683 dev_priv->vbt.psr.full_link = psr_table->full_link;
684 dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
685
686
687 dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
688 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
689
690 switch (psr_table->lines_to_wait) {
691 case 0:
692 dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
693 break;
694 case 1:
695 dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
696 break;
697 case 2:
698 dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
699 break;
700 case 3:
701 dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
702 break;
703 default:
704 DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n",
705 psr_table->lines_to_wait);
706 break;
707 }
708
709
710
711
712
713 if (bdb->version >= 205 &&
714 (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) ||
715 INTEL_GEN(dev_priv) >= 10)) {
716 switch (psr_table->tp1_wakeup_time) {
717 case 0:
718 dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
719 break;
720 case 1:
721 dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
722 break;
723 case 3:
724 dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
725 break;
726 default:
727 DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
728 psr_table->tp1_wakeup_time);
729
730 case 2:
731 dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
732 break;
733 }
734
735 switch (psr_table->tp2_tp3_wakeup_time) {
736 case 0:
737 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
738 break;
739 case 1:
740 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
741 break;
742 case 3:
743 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 0;
744 break;
745 default:
746 DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
747 psr_table->tp2_tp3_wakeup_time);
748
749 case 2:
750 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
751 break;
752 }
753 } else {
754 dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
755 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
756 }
757}
758
759static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
760 u16 version, enum port port)
761{
762 if (!dev_priv->vbt.dsi.config->dual_link || version < 197) {
763 dev_priv->vbt.dsi.bl_ports = BIT(port);
764 if (dev_priv->vbt.dsi.config->cabc_supported)
765 dev_priv->vbt.dsi.cabc_ports = BIT(port);
766
767 return;
768 }
769
770 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
771 case DL_DCS_PORT_A:
772 dev_priv->vbt.dsi.bl_ports = BIT(PORT_A);
773 break;
774 case DL_DCS_PORT_C:
775 dev_priv->vbt.dsi.bl_ports = BIT(PORT_C);
776 break;
777 default:
778 case DL_DCS_PORT_A_AND_C:
779 dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
780 break;
781 }
782
783 if (!dev_priv->vbt.dsi.config->cabc_supported)
784 return;
785
786 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
787 case DL_DCS_PORT_A:
788 dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A);
789 break;
790 case DL_DCS_PORT_C:
791 dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C);
792 break;
793 default:
794 case DL_DCS_PORT_A_AND_C:
795 dev_priv->vbt.dsi.cabc_ports =
796 BIT(PORT_A) | BIT(PORT_C);
797 break;
798 }
799}
800
801static void
802parse_mipi_config(struct drm_i915_private *dev_priv,
803 const struct bdb_header *bdb)
804{
805 const struct bdb_mipi_config *start;
806 const struct mipi_config *config;
807 const struct mipi_pps_data *pps;
808 int panel_type = dev_priv->vbt.panel_type;
809 enum port port;
810
811
812 if (!intel_bios_is_dsi_present(dev_priv, &port))
813 return;
814
815
816 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
817
818
819
820
821
822
823
824
825
826 start = find_section(bdb, BDB_MIPI_CONFIG);
827 if (!start) {
828 DRM_DEBUG_KMS("No MIPI config BDB found");
829 return;
830 }
831
832 DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n",
833 panel_type);
834
835
836
837
838
839 config = &start->config[panel_type];
840 pps = &start->pps[panel_type];
841
842
843 dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
844 if (!dev_priv->vbt.dsi.config)
845 return;
846
847 dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
848 if (!dev_priv->vbt.dsi.pps) {
849 kfree(dev_priv->vbt.dsi.config);
850 return;
851 }
852
853 parse_dsi_backlight_ports(dev_priv, bdb->version, port);
854
855
856 dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
857}
858
859
860static const u8 *
861find_panel_sequence_block(const struct bdb_mipi_sequence *sequence,
862 u16 panel_id, u32 *seq_size)
863{
864 u32 total = get_blocksize(sequence);
865 const u8 *data = &sequence->data[0];
866 u8 current_id;
867 u32 current_size;
868 int header_size = sequence->version >= 3 ? 5 : 3;
869 int index = 0;
870 int i;
871
872
873 if (sequence->version >= 3)
874 data += 4;
875
876 for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) {
877 if (index + header_size > total) {
878 DRM_ERROR("Invalid sequence block (header)\n");
879 return NULL;
880 }
881
882 current_id = *(data + index);
883 if (sequence->version >= 3)
884 current_size = *((const u32 *)(data + index + 1));
885 else
886 current_size = *((const u16 *)(data + index + 1));
887
888 index += header_size;
889
890 if (index + current_size > total) {
891 DRM_ERROR("Invalid sequence block\n");
892 return NULL;
893 }
894
895 if (current_id == panel_id) {
896 *seq_size = current_size;
897 return data + index;
898 }
899
900 index += current_size;
901 }
902
903 DRM_ERROR("Sequence block detected but no valid configuration\n");
904
905 return NULL;
906}
907
908static int goto_next_sequence(const u8 *data, int index, int total)
909{
910 u16 len;
911
912
913 for (index = index + 1; index < total; index += len) {
914 u8 operation_byte = *(data + index);
915 index++;
916
917 switch (operation_byte) {
918 case MIPI_SEQ_ELEM_END:
919 return index;
920 case MIPI_SEQ_ELEM_SEND_PKT:
921 if (index + 4 > total)
922 return 0;
923
924 len = *((const u16 *)(data + index + 2)) + 4;
925 break;
926 case MIPI_SEQ_ELEM_DELAY:
927 len = 4;
928 break;
929 case MIPI_SEQ_ELEM_GPIO:
930 len = 2;
931 break;
932 case MIPI_SEQ_ELEM_I2C:
933 if (index + 7 > total)
934 return 0;
935 len = *(data + index + 6) + 7;
936 break;
937 default:
938 DRM_ERROR("Unknown operation byte\n");
939 return 0;
940 }
941 }
942
943 return 0;
944}
945
946static int goto_next_sequence_v3(const u8 *data, int index, int total)
947{
948 int seq_end;
949 u16 len;
950 u32 size_of_sequence;
951
952
953
954
955
956 if (total < 5) {
957 DRM_ERROR("Too small sequence size\n");
958 return 0;
959 }
960
961
962 index++;
963
964
965
966
967
968
969 size_of_sequence = *((const u32 *)(data + index));
970 index += 4;
971
972 seq_end = index + size_of_sequence;
973 if (seq_end > total) {
974 DRM_ERROR("Invalid sequence size\n");
975 return 0;
976 }
977
978 for (; index < total; index += len) {
979 u8 operation_byte = *(data + index);
980 index++;
981
982 if (operation_byte == MIPI_SEQ_ELEM_END) {
983 if (index != seq_end) {
984 DRM_ERROR("Invalid element structure\n");
985 return 0;
986 }
987 return index;
988 }
989
990 len = *(data + index);
991 index++;
992
993
994
995
996
997 switch (operation_byte) {
998 case MIPI_SEQ_ELEM_SEND_PKT:
999 case MIPI_SEQ_ELEM_DELAY:
1000 case MIPI_SEQ_ELEM_GPIO:
1001 case MIPI_SEQ_ELEM_I2C:
1002 case MIPI_SEQ_ELEM_SPI:
1003 case MIPI_SEQ_ELEM_PMIC:
1004 break;
1005 default:
1006 DRM_ERROR("Unknown operation byte %u\n",
1007 operation_byte);
1008 break;
1009 }
1010 }
1011
1012 return 0;
1013}
1014
1015
1016
1017
1018
1019static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv)
1020{
1021 const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1022 int index, len;
1023
1024 if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1))
1025 return 0;
1026
1027
1028 for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) {
1029 switch (data[index]) {
1030 case MIPI_SEQ_ELEM_SEND_PKT:
1031 return index == 1 ? 0 : index;
1032 case MIPI_SEQ_ELEM_DELAY:
1033 len = 5;
1034 break;
1035 case MIPI_SEQ_ELEM_GPIO:
1036 len = 3;
1037 break;
1038 default:
1039 return 0;
1040 }
1041 }
1042
1043 return 0;
1044}
1045
1046
1047
1048
1049
1050
1051
1052static void fixup_mipi_sequences(struct drm_i915_private *dev_priv)
1053{
1054 u8 *init_otp;
1055 int len;
1056
1057
1058 if (!IS_VALLEYVIEW(dev_priv))
1059 return;
1060
1061
1062 if (dev_priv->vbt.dsi.config->is_cmd_mode ||
1063 dev_priv->vbt.dsi.seq_version != 1)
1064 return;
1065
1066
1067 if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
1068 !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
1069 dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
1070 return;
1071
1072
1073 len = get_init_otp_deassert_fragment_len(dev_priv);
1074 if (!len)
1075 return;
1076
1077 DRM_DEBUG_KMS("Using init OTP fragment to deassert reset\n");
1078
1079
1080 init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1081 dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
1082 if (!dev_priv->vbt.dsi.deassert_seq)
1083 return;
1084 dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
1085 dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
1086
1087 dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
1088 dev_priv->vbt.dsi.deassert_seq;
1089
1090 init_otp[len - 1] = MIPI_SEQ_INIT_OTP;
1091
1092 dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
1093}
1094
1095static void
1096parse_mipi_sequence(struct drm_i915_private *dev_priv,
1097 const struct bdb_header *bdb)
1098{
1099 int panel_type = dev_priv->vbt.panel_type;
1100 const struct bdb_mipi_sequence *sequence;
1101 const u8 *seq_data;
1102 u32 seq_size;
1103 u8 *data;
1104 int index = 0;
1105
1106
1107 if (dev_priv->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)
1108 return;
1109
1110 sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
1111 if (!sequence) {
1112 DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n");
1113 return;
1114 }
1115
1116
1117 if (sequence->version >= 4) {
1118 DRM_ERROR("Unable to parse MIPI Sequence Block v%u\n",
1119 sequence->version);
1120 return;
1121 }
1122
1123 DRM_DEBUG_DRIVER("Found MIPI sequence block v%u\n", sequence->version);
1124
1125 seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size);
1126 if (!seq_data)
1127 return;
1128
1129 data = kmemdup(seq_data, seq_size, GFP_KERNEL);
1130 if (!data)
1131 return;
1132
1133
1134 for (;;) {
1135 u8 seq_id = *(data + index);
1136 if (seq_id == MIPI_SEQ_END)
1137 break;
1138
1139 if (seq_id >= MIPI_SEQ_MAX) {
1140 DRM_ERROR("Unknown sequence %u\n", seq_id);
1141 goto err;
1142 }
1143
1144
1145 if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF)
1146 DRM_DEBUG_KMS("Unsupported sequence %u\n", seq_id);
1147
1148 dev_priv->vbt.dsi.sequence[seq_id] = data + index;
1149
1150 if (sequence->version >= 3)
1151 index = goto_next_sequence_v3(data, index, seq_size);
1152 else
1153 index = goto_next_sequence(data, index, seq_size);
1154 if (!index) {
1155 DRM_ERROR("Invalid sequence %u\n", seq_id);
1156 goto err;
1157 }
1158 }
1159
1160 dev_priv->vbt.dsi.data = data;
1161 dev_priv->vbt.dsi.size = seq_size;
1162 dev_priv->vbt.dsi.seq_version = sequence->version;
1163
1164 fixup_mipi_sequences(dev_priv);
1165
1166 DRM_DEBUG_DRIVER("MIPI related VBT parsing complete\n");
1167 return;
1168
1169err:
1170 kfree(data);
1171 memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
1172}
1173
1174static u8 translate_iboost(u8 val)
1175{
1176 static const u8 mapping[] = { 1, 3, 7 };
1177
1178 if (val >= ARRAY_SIZE(mapping)) {
1179 DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);
1180 return 0;
1181 }
1182 return mapping[val];
1183}
1184
1185static void sanitize_ddc_pin(struct drm_i915_private *dev_priv,
1186 enum port port)
1187{
1188 const struct ddi_vbt_port_info *info =
1189 &dev_priv->vbt.ddi_port_info[port];
1190 enum port p;
1191
1192 if (!info->alternate_ddc_pin)
1193 return;
1194
1195 for_each_port_masked(p, (1 << port) - 1) {
1196 struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p];
1197
1198 if (info->alternate_ddc_pin != i->alternate_ddc_pin)
1199 continue;
1200
1201 DRM_DEBUG_KMS("port %c trying to use the same DDC pin (0x%x) as port %c, "
1202 "disabling port %c DVI/HDMI support\n",
1203 port_name(p), i->alternate_ddc_pin,
1204 port_name(port), port_name(p));
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215 i->supports_dvi = false;
1216 i->supports_hdmi = false;
1217 i->alternate_ddc_pin = 0;
1218 }
1219}
1220
1221static void sanitize_aux_ch(struct drm_i915_private *dev_priv,
1222 enum port port)
1223{
1224 const struct ddi_vbt_port_info *info =
1225 &dev_priv->vbt.ddi_port_info[port];
1226 enum port p;
1227
1228 if (!info->alternate_aux_channel)
1229 return;
1230
1231 for_each_port_masked(p, (1 << port) - 1) {
1232 struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p];
1233
1234 if (info->alternate_aux_channel != i->alternate_aux_channel)
1235 continue;
1236
1237 DRM_DEBUG_KMS("port %c trying to use the same AUX CH (0x%x) as port %c, "
1238 "disabling port %c DP support\n",
1239 port_name(p), i->alternate_aux_channel,
1240 port_name(port), port_name(p));
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251 i->supports_dp = false;
1252 i->alternate_aux_channel = 0;
1253 }
1254}
1255
1256static const u8 cnp_ddc_pin_map[] = {
1257 [0] = 0,
1258 [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT,
1259 [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT,
1260 [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP,
1261 [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT,
1262};
1263
1264static const u8 icp_ddc_pin_map[] = {
1265 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
1266 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
1267 [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
1268 [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
1269 [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
1270 [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
1271};
1272
1273static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
1274{
1275 const u8 *ddc_pin_map;
1276 int n_entries;
1277
1278 if (HAS_PCH_ICP(dev_priv)) {
1279 ddc_pin_map = icp_ddc_pin_map;
1280 n_entries = ARRAY_SIZE(icp_ddc_pin_map);
1281 } else if (HAS_PCH_CNP(dev_priv)) {
1282 ddc_pin_map = cnp_ddc_pin_map;
1283 n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
1284 } else {
1285
1286 return vbt_pin;
1287 }
1288
1289 if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0)
1290 return ddc_pin_map[vbt_pin];
1291
1292 DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n",
1293 vbt_pin);
1294 return 0;
1295}
1296
1297static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
1298 u8 bdb_version)
1299{
1300 struct child_device_config *it, *child = NULL;
1301 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1302 int i, j;
1303 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
1304
1305
1306
1307 int dvo_ports[][3] = {
1308 {DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
1309 {DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
1310 {DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
1311 {DVO_PORT_HDMID, DVO_PORT_DPD, -1},
1312 {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
1313 {DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
1314 };
1315
1316
1317
1318
1319
1320 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1321 it = dev_priv->vbt.child_dev + i;
1322
1323 for (j = 0; j < 3; j++) {
1324 if (dvo_ports[port][j] == -1)
1325 break;
1326
1327 if (it->dvo_port == dvo_ports[port][j]) {
1328 if (child) {
1329 DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n",
1330 port_name(port));
1331 } else {
1332 child = it;
1333 }
1334 }
1335 }
1336 }
1337 if (!child)
1338 return;
1339
1340 is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
1341 is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
1342 is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT;
1343 is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
1344 is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
1345
1346 if (port == PORT_A && is_dvi) {
1347 DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n",
1348 is_hdmi ? "/HDMI" : "");
1349 is_dvi = false;
1350 is_hdmi = false;
1351 }
1352
1353 info->supports_dvi = is_dvi;
1354 info->supports_hdmi = is_hdmi;
1355 info->supports_dp = is_dp;
1356 info->supports_edp = is_edp;
1357
1358 DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n",
1359 port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt);
1360
1361 if (is_edp && is_dvi)
1362 DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
1363 port_name(port));
1364 if (is_crt && port != PORT_E)
1365 DRM_DEBUG_KMS("Port %c is analog\n", port_name(port));
1366 if (is_crt && (is_dvi || is_dp))
1367 DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n",
1368 port_name(port));
1369 if (is_dvi && (port == PORT_A || port == PORT_E))
1370 DRM_DEBUG_KMS("Port %c is TMDS compatible\n", port_name(port));
1371 if (!is_dvi && !is_dp && !is_crt)
1372 DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n",
1373 port_name(port));
1374 if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E))
1375 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
1376
1377 if (is_dvi) {
1378 u8 ddc_pin;
1379
1380 ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin);
1381 if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) {
1382 info->alternate_ddc_pin = ddc_pin;
1383 sanitize_ddc_pin(dev_priv, port);
1384 } else {
1385 DRM_DEBUG_KMS("Port %c has invalid DDC pin %d, "
1386 "sticking to defaults\n",
1387 port_name(port), ddc_pin);
1388 }
1389 }
1390
1391 if (is_dp) {
1392 info->alternate_aux_channel = child->aux_channel;
1393
1394 sanitize_aux_ch(dev_priv, port);
1395 }
1396
1397 if (bdb_version >= 158) {
1398
1399 u8 hdmi_level_shift = child->hdmi_level_shifter_value;
1400 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
1401 port_name(port),
1402 hdmi_level_shift);
1403 info->hdmi_level_shift = hdmi_level_shift;
1404 }
1405
1406 if (bdb_version >= 204) {
1407 int max_tmds_clock;
1408
1409 switch (child->hdmi_max_data_rate) {
1410 default:
1411 MISSING_CASE(child->hdmi_max_data_rate);
1412
1413 case HDMI_MAX_DATA_RATE_PLATFORM:
1414 max_tmds_clock = 0;
1415 break;
1416 case HDMI_MAX_DATA_RATE_297:
1417 max_tmds_clock = 297000;
1418 break;
1419 case HDMI_MAX_DATA_RATE_165:
1420 max_tmds_clock = 165000;
1421 break;
1422 }
1423
1424 if (max_tmds_clock)
1425 DRM_DEBUG_KMS("VBT HDMI max TMDS clock for port %c: %d kHz\n",
1426 port_name(port), max_tmds_clock);
1427 info->max_tmds_clock = max_tmds_clock;
1428 }
1429
1430
1431 if (bdb_version >= 196 && child->iboost) {
1432 info->dp_boost_level = translate_iboost(child->dp_iboost_level);
1433 DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n",
1434 port_name(port), info->dp_boost_level);
1435 info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level);
1436 DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
1437 port_name(port), info->hdmi_boost_level);
1438 }
1439
1440
1441 if (bdb_version >= 216) {
1442 switch (child->dp_max_link_rate) {
1443 default:
1444 case VBT_DP_MAX_LINK_RATE_HBR3:
1445 info->dp_max_link_rate = 810000;
1446 break;
1447 case VBT_DP_MAX_LINK_RATE_HBR2:
1448 info->dp_max_link_rate = 540000;
1449 break;
1450 case VBT_DP_MAX_LINK_RATE_HBR:
1451 info->dp_max_link_rate = 270000;
1452 break;
1453 case VBT_DP_MAX_LINK_RATE_LBR:
1454 info->dp_max_link_rate = 162000;
1455 break;
1456 }
1457 DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n",
1458 port_name(port), info->dp_max_link_rate);
1459 }
1460}
1461
1462static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
1463{
1464 enum port port;
1465
1466 if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1467 return;
1468
1469 if (!dev_priv->vbt.child_dev_num)
1470 return;
1471
1472 if (bdb_version < 155)
1473 return;
1474
1475 for (port = PORT_A; port < I915_MAX_PORTS; port++)
1476 parse_ddi_port(dev_priv, port, bdb_version);
1477}
1478
1479static void
1480parse_general_definitions(struct drm_i915_private *dev_priv,
1481 const struct bdb_header *bdb)
1482{
1483 const struct bdb_general_definitions *defs;
1484 const struct child_device_config *child;
1485 int i, child_device_num, count;
1486 u8 expected_size;
1487 u16 block_size;
1488 int bus_pin;
1489
1490 defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
1491 if (!defs) {
1492 DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
1493 return;
1494 }
1495
1496 block_size = get_blocksize(defs);
1497 if (block_size < sizeof(*defs)) {
1498 DRM_DEBUG_KMS("General definitions block too small (%u)\n",
1499 block_size);
1500 return;
1501 }
1502
1503 bus_pin = defs->crt_ddc_gmbus_pin;
1504 DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
1505 if (intel_gmbus_is_valid_pin(dev_priv, bus_pin))
1506 dev_priv->vbt.crt_ddc_pin = bus_pin;
1507
1508 if (bdb->version < 106) {
1509 expected_size = 22;
1510 } else if (bdb->version < 111) {
1511 expected_size = 27;
1512 } else if (bdb->version < 195) {
1513 expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
1514 } else if (bdb->version == 195) {
1515 expected_size = 37;
1516 } else if (bdb->version <= 215) {
1517 expected_size = 38;
1518 } else if (bdb->version <= 216) {
1519 expected_size = 39;
1520 } else {
1521 expected_size = sizeof(*child);
1522 BUILD_BUG_ON(sizeof(*child) < 39);
1523 DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n",
1524 bdb->version, expected_size);
1525 }
1526
1527
1528 if (defs->child_dev_size != expected_size)
1529 DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n",
1530 defs->child_dev_size, expected_size, bdb->version);
1531
1532
1533 if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
1534 DRM_DEBUG_KMS("Child device config size %u is too small.\n",
1535 defs->child_dev_size);
1536 return;
1537 }
1538
1539
1540 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
1541 count = 0;
1542
1543 for (i = 0; i < child_device_num; i++) {
1544 child = child_device_ptr(defs, i);
1545 if (!child->device_type)
1546 continue;
1547 count++;
1548 }
1549 if (!count) {
1550 DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
1551 return;
1552 }
1553 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL);
1554 if (!dev_priv->vbt.child_dev) {
1555 DRM_DEBUG_KMS("No memory space for child device\n");
1556 return;
1557 }
1558
1559 dev_priv->vbt.child_dev_num = count;
1560 count = 0;
1561 for (i = 0; i < child_device_num; i++) {
1562 child = child_device_ptr(defs, i);
1563 if (!child->device_type)
1564 continue;
1565
1566
1567
1568
1569
1570
1571 memcpy(dev_priv->vbt.child_dev + count, child,
1572 min_t(size_t, defs->child_dev_size, sizeof(*child)));
1573 count++;
1574 }
1575}
1576
1577
1578static void
1579init_vbt_defaults(struct drm_i915_private *dev_priv)
1580{
1581 enum port port;
1582
1583 dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
1584
1585
1586 dev_priv->vbt.backlight.present = true;
1587
1588
1589 dev_priv->vbt.lvds_dither = 1;
1590
1591
1592 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1593
1594
1595 dev_priv->vbt.int_tv_support = 1;
1596 dev_priv->vbt.int_crt_support = 1;
1597
1598
1599 dev_priv->vbt.int_lvds_support = 1;
1600
1601
1602 dev_priv->vbt.lvds_use_ssc = 1;
1603
1604
1605
1606
1607 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv,
1608 !HAS_PCH_SPLIT(dev_priv));
1609 DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq);
1610
1611 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
1612 struct ddi_vbt_port_info *info =
1613 &dev_priv->vbt.ddi_port_info[port];
1614
1615 info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN;
1616 }
1617}
1618
1619
1620static void
1621init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
1622{
1623 enum port port;
1624
1625 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
1626 struct ddi_vbt_port_info *info =
1627 &dev_priv->vbt.ddi_port_info[port];
1628
1629 info->supports_dvi = (port != PORT_A && port != PORT_E);
1630 info->supports_hdmi = info->supports_dvi;
1631 info->supports_dp = (port != PORT_E);
1632 }
1633}
1634
1635static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
1636{
1637 const void *_vbt = vbt;
1638
1639 return _vbt + vbt->bdb_offset;
1640}
1641
1642
1643
1644
1645
1646
1647
1648
1649bool intel_bios_is_valid_vbt(const void *buf, size_t size)
1650{
1651 const struct vbt_header *vbt = buf;
1652 const struct bdb_header *bdb;
1653
1654 if (!vbt)
1655 return false;
1656
1657 if (sizeof(struct vbt_header) > size) {
1658 DRM_DEBUG_DRIVER("VBT header incomplete\n");
1659 return false;
1660 }
1661
1662 if (memcmp(vbt->signature, "$VBT", 4)) {
1663 DRM_DEBUG_DRIVER("VBT invalid signature\n");
1664 return false;
1665 }
1666
1667 if (range_overflows_t(size_t,
1668 vbt->bdb_offset,
1669 sizeof(struct bdb_header),
1670 size)) {
1671 DRM_DEBUG_DRIVER("BDB header incomplete\n");
1672 return false;
1673 }
1674
1675 bdb = get_bdb_header(vbt);
1676 if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {
1677 DRM_DEBUG_DRIVER("BDB incomplete\n");
1678 return false;
1679 }
1680
1681 return vbt;
1682}
1683
1684static const struct vbt_header *find_vbt(void __iomem *bios, size_t size)
1685{
1686 size_t i;
1687
1688
1689 for (i = 0; i + 4 < size; i++) {
1690 void *vbt;
1691
1692 if (ioread32(bios + i) != *((const u32 *) "$VBT"))
1693 continue;
1694
1695
1696
1697
1698
1699 vbt = (void __force *) bios + i;
1700 if (intel_bios_is_valid_vbt(vbt, size - i))
1701 return vbt;
1702
1703 break;
1704 }
1705
1706 return NULL;
1707}
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717void intel_bios_init(struct drm_i915_private *dev_priv)
1718{
1719 struct pci_dev *pdev = dev_priv->drm.pdev;
1720 const struct vbt_header *vbt = dev_priv->opregion.vbt;
1721 const struct bdb_header *bdb;
1722 u8 __iomem *bios = NULL;
1723
1724 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
1725 DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
1726 return;
1727 }
1728
1729 init_vbt_defaults(dev_priv);
1730
1731
1732 if (!vbt) {
1733 size_t size;
1734
1735 bios = pci_map_rom(pdev, &size);
1736 if (!bios)
1737 goto out;
1738
1739 vbt = find_vbt(bios, size);
1740 if (!vbt)
1741 goto out;
1742
1743 DRM_DEBUG_KMS("Found valid VBT in PCI ROM\n");
1744 }
1745
1746 bdb = get_bdb_header(vbt);
1747
1748 DRM_DEBUG_KMS("VBT signature \"%.*s\", BDB version %d\n",
1749 (int)sizeof(vbt->signature), vbt->signature, bdb->version);
1750
1751
1752 parse_general_features(dev_priv, bdb);
1753 parse_general_definitions(dev_priv, bdb);
1754 parse_lfp_panel_data(dev_priv, bdb);
1755 parse_lfp_backlight(dev_priv, bdb);
1756 parse_sdvo_panel_data(dev_priv, bdb);
1757 parse_driver_features(dev_priv, bdb);
1758 parse_edp(dev_priv, bdb);
1759 parse_psr(dev_priv, bdb);
1760 parse_mipi_config(dev_priv, bdb);
1761 parse_mipi_sequence(dev_priv, bdb);
1762
1763
1764 parse_sdvo_device_mapping(dev_priv, bdb->version);
1765 parse_ddi_ports(dev_priv, bdb->version);
1766
1767out:
1768 if (!vbt) {
1769 DRM_INFO("Failed to find VBIOS tables (VBT)\n");
1770 init_vbt_missing_defaults(dev_priv);
1771 }
1772
1773 if (bios)
1774 pci_unmap_rom(pdev, bios);
1775}
1776
1777
1778
1779
1780
1781void intel_bios_cleanup(struct drm_i915_private *dev_priv)
1782{
1783 kfree(dev_priv->vbt.child_dev);
1784 dev_priv->vbt.child_dev = NULL;
1785 dev_priv->vbt.child_dev_num = 0;
1786 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1787 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1788 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1789 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1790 kfree(dev_priv->vbt.dsi.data);
1791 dev_priv->vbt.dsi.data = NULL;
1792 kfree(dev_priv->vbt.dsi.pps);
1793 dev_priv->vbt.dsi.pps = NULL;
1794 kfree(dev_priv->vbt.dsi.config);
1795 dev_priv->vbt.dsi.config = NULL;
1796 kfree(dev_priv->vbt.dsi.deassert_seq);
1797 dev_priv->vbt.dsi.deassert_seq = NULL;
1798}
1799
1800
1801
1802
1803
1804
1805
1806
1807bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
1808{
1809 const struct child_device_config *child;
1810 int i;
1811
1812 if (!dev_priv->vbt.int_tv_support)
1813 return false;
1814
1815 if (!dev_priv->vbt.child_dev_num)
1816 return true;
1817
1818 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1819 child = dev_priv->vbt.child_dev + i;
1820
1821
1822
1823 switch (child->device_type) {
1824 case DEVICE_TYPE_INT_TV:
1825 case DEVICE_TYPE_TV:
1826 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
1827 break;
1828 default:
1829 continue;
1830 }
1831
1832
1833
1834 if (child->addin_offset)
1835 return true;
1836 }
1837
1838 return false;
1839}
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)
1850{
1851 const struct child_device_config *child;
1852 int i;
1853
1854 if (!dev_priv->vbt.child_dev_num)
1855 return true;
1856
1857 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1858 child = dev_priv->vbt.child_dev + i;
1859
1860
1861
1862
1863
1864 if (child->device_type != DEVICE_TYPE_INT_LFP &&
1865 child->device_type != DEVICE_TYPE_LFP)
1866 continue;
1867
1868 if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
1869 *i2c_pin = child->i2c_pin;
1870
1871
1872
1873
1874
1875
1876 if (child->addin_offset)
1877 return true;
1878
1879
1880
1881
1882
1883
1884 if (dev_priv->opregion.vbt)
1885 return true;
1886 }
1887
1888 return false;
1889}
1890
1891
1892
1893
1894
1895
1896
1897
1898bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port)
1899{
1900 const struct child_device_config *child;
1901 static const struct {
1902 u16 dp, hdmi;
1903 } port_mapping[] = {
1904 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
1905 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
1906 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
1907 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
1908 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
1909 };
1910 int i;
1911
1912
1913 if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping))
1914 return false;
1915
1916 if (!dev_priv->vbt.child_dev_num)
1917 return false;
1918
1919 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1920 child = dev_priv->vbt.child_dev + i;
1921
1922 if ((child->dvo_port == port_mapping[port].dp ||
1923 child->dvo_port == port_mapping[port].hdmi) &&
1924 (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
1925 DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
1926 return true;
1927 }
1928
1929 return false;
1930}
1931
1932
1933
1934
1935
1936
1937
1938
1939bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
1940{
1941 const struct child_device_config *child;
1942 static const short port_mapping[] = {
1943 [PORT_B] = DVO_PORT_DPB,
1944 [PORT_C] = DVO_PORT_DPC,
1945 [PORT_D] = DVO_PORT_DPD,
1946 [PORT_E] = DVO_PORT_DPE,
1947 [PORT_F] = DVO_PORT_DPF,
1948 };
1949 int i;
1950
1951 if (HAS_DDI(dev_priv))
1952 return dev_priv->vbt.ddi_port_info[port].supports_edp;
1953
1954 if (!dev_priv->vbt.child_dev_num)
1955 return false;
1956
1957 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1958 child = dev_priv->vbt.child_dev + i;
1959
1960 if (child->dvo_port == port_mapping[port] &&
1961 (child->device_type & DEVICE_TYPE_eDP_BITS) ==
1962 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
1963 return true;
1964 }
1965
1966 return false;
1967}
1968
1969static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
1970 enum port port)
1971{
1972 static const struct {
1973 u16 dp, hdmi;
1974 } port_mapping[] = {
1975
1976
1977
1978
1979 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
1980 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
1981 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
1982 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
1983 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
1984 };
1985
1986 if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
1987 return false;
1988
1989 if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
1990 (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
1991 return false;
1992
1993 if (child->dvo_port == port_mapping[port].dp)
1994 return true;
1995
1996
1997 if (child->dvo_port == port_mapping[port].hdmi &&
1998 child->aux_channel != 0)
1999 return true;
2000
2001 return false;
2002}
2003
2004bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv,
2005 enum port port)
2006{
2007 const struct child_device_config *child;
2008 int i;
2009
2010 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2011 child = dev_priv->vbt.child_dev + i;
2012
2013 if (child_dev_is_dp_dual_mode(child, port))
2014 return true;
2015 }
2016
2017 return false;
2018}
2019
2020
2021
2022
2023
2024
2025
2026
2027bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
2028 enum port *port)
2029{
2030 const struct child_device_config *child;
2031 u8 dvo_port;
2032 int i;
2033
2034 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2035 child = dev_priv->vbt.child_dev + i;
2036
2037 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
2038 continue;
2039
2040 dvo_port = child->dvo_port;
2041
2042 switch (dvo_port) {
2043 case DVO_PORT_MIPIA:
2044 case DVO_PORT_MIPIC:
2045 if (port)
2046 *port = dvo_port - DVO_PORT_MIPIA;
2047 return true;
2048 case DVO_PORT_MIPIB:
2049 case DVO_PORT_MIPID:
2050 DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
2051 port_name(dvo_port - DVO_PORT_MIPIA));
2052 break;
2053 }
2054 }
2055
2056 return false;
2057}
2058
2059
2060
2061
2062
2063
2064
2065
2066bool
2067intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
2068 enum port port)
2069{
2070 const struct child_device_config *child;
2071 int i;
2072
2073 if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
2074 return false;
2075
2076 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2077 child = dev_priv->vbt.child_dev + i;
2078
2079 if (!child->hpd_invert)
2080 continue;
2081
2082 switch (child->dvo_port) {
2083 case DVO_PORT_DPA:
2084 case DVO_PORT_HDMIA:
2085 if (port == PORT_A)
2086 return true;
2087 break;
2088 case DVO_PORT_DPB:
2089 case DVO_PORT_HDMIB:
2090 if (port == PORT_B)
2091 return true;
2092 break;
2093 case DVO_PORT_DPC:
2094 case DVO_PORT_HDMIC:
2095 if (port == PORT_C)
2096 return true;
2097 break;
2098 default:
2099 break;
2100 }
2101 }
2102
2103 return false;
2104}
2105
2106
2107
2108
2109
2110
2111
2112
2113bool
2114intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
2115 enum port port)
2116{
2117 const struct child_device_config *child;
2118 int i;
2119
2120 if (!HAS_LSPCON(dev_priv))
2121 return false;
2122
2123 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2124 child = dev_priv->vbt.child_dev + i;
2125
2126 if (!child->lspcon)
2127 continue;
2128
2129 switch (child->dvo_port) {
2130 case DVO_PORT_DPA:
2131 case DVO_PORT_HDMIA:
2132 if (port == PORT_A)
2133 return true;
2134 break;
2135 case DVO_PORT_DPB:
2136 case DVO_PORT_HDMIB:
2137 if (port == PORT_B)
2138 return true;
2139 break;
2140 case DVO_PORT_DPC:
2141 case DVO_PORT_HDMIC:
2142 if (port == PORT_C)
2143 return true;
2144 break;
2145 case DVO_PORT_DPD:
2146 case DVO_PORT_HDMID:
2147 if (port == PORT_D)
2148 return true;
2149 break;
2150 case DVO_PORT_DPF:
2151 case DVO_PORT_HDMIF:
2152 if (port == PORT_F)
2153 return true;
2154 break;
2155 default:
2156 break;
2157 }
2158 }
2159
2160 return false;
2161}
2162