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21#ifndef __OMAP2_DSS_H
22#define __OMAP2_DSS_H
23
24#include <linux/interrupt.h>
25
26#include "omapdss.h"
27
28struct dispc_device;
29struct dss_debugfs_entry;
30struct platform_device;
31struct seq_file;
32
33#define MAX_DSS_LCD_MANAGERS 3
34#define MAX_NUM_DSI 2
35
36#ifdef pr_fmt
37#undef pr_fmt
38#endif
39
40#ifdef DSS_SUBSYS_NAME
41#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
42#else
43#define pr_fmt(fmt) fmt
44#endif
45
46#define DSSDBG(format, ...) \
47 pr_debug(format, ## __VA_ARGS__)
48
49#ifdef DSS_SUBSYS_NAME
50#define DSSERR(format, ...) \
51 pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
52#else
53#define DSSERR(format, ...) \
54 pr_err("omapdss error: " format, ##__VA_ARGS__)
55#endif
56
57#ifdef DSS_SUBSYS_NAME
58#define DSSINFO(format, ...) \
59 pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
60#else
61#define DSSINFO(format, ...) \
62 pr_info("omapdss: " format, ## __VA_ARGS__)
63#endif
64
65#ifdef DSS_SUBSYS_NAME
66#define DSSWARN(format, ...) \
67 pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
68#else
69#define DSSWARN(format, ...) \
70 pr_warn("omapdss: " format, ##__VA_ARGS__)
71#endif
72
73
74
75#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
76#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
77#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
78#define FLD_MOD(orig, val, start, end) \
79 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
80
81enum dss_model {
82 DSS_MODEL_OMAP2,
83 DSS_MODEL_OMAP3,
84 DSS_MODEL_OMAP4,
85 DSS_MODEL_OMAP5,
86 DSS_MODEL_DRA7,
87};
88
89enum dss_io_pad_mode {
90 DSS_IO_PAD_MODE_RESET,
91 DSS_IO_PAD_MODE_RFBI,
92 DSS_IO_PAD_MODE_BYPASS,
93};
94
95enum dss_hdmi_venc_clk_source_select {
96 DSS_VENC_TV_CLK = 0,
97 DSS_HDMI_M_PCLK = 1,
98};
99
100enum dss_dsi_content_type {
101 DSS_DSI_CONTENT_DCS,
102 DSS_DSI_CONTENT_GENERIC,
103};
104
105enum dss_clk_source {
106 DSS_CLK_SRC_FCK = 0,
107
108 DSS_CLK_SRC_PLL1_1,
109 DSS_CLK_SRC_PLL1_2,
110 DSS_CLK_SRC_PLL1_3,
111
112 DSS_CLK_SRC_PLL2_1,
113 DSS_CLK_SRC_PLL2_2,
114 DSS_CLK_SRC_PLL2_3,
115
116 DSS_CLK_SRC_HDMI_PLL,
117};
118
119enum dss_pll_id {
120 DSS_PLL_DSI1,
121 DSS_PLL_DSI2,
122 DSS_PLL_HDMI,
123 DSS_PLL_VIDEO1,
124 DSS_PLL_VIDEO2,
125};
126
127struct dss_pll;
128
129#define DSS_PLL_MAX_HSDIVS 4
130
131enum dss_pll_type {
132 DSS_PLL_TYPE_A,
133 DSS_PLL_TYPE_B,
134};
135
136
137
138
139
140struct dss_pll_clock_info {
141
142 unsigned long fint;
143 unsigned long clkdco;
144 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
145
146
147 u16 n;
148 u16 m;
149 u32 mf;
150 u16 mX[DSS_PLL_MAX_HSDIVS];
151 u16 sd;
152};
153
154struct dss_pll_ops {
155 int (*enable)(struct dss_pll *pll);
156 void (*disable)(struct dss_pll *pll);
157 int (*set_config)(struct dss_pll *pll,
158 const struct dss_pll_clock_info *cinfo);
159};
160
161struct dss_pll_hw {
162 enum dss_pll_type type;
163
164 unsigned int n_max;
165 unsigned int m_min;
166 unsigned int m_max;
167 unsigned int mX_max;
168
169 unsigned long fint_min, fint_max;
170 unsigned long clkdco_min, clkdco_low, clkdco_max;
171
172 u8 n_msb, n_lsb;
173 u8 m_msb, m_lsb;
174 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
175
176 bool has_stopmode;
177 bool has_freqsel;
178 bool has_selfreqdco;
179 bool has_refsel;
180
181
182 bool errata_i886;
183
184
185 bool errata_i932;
186};
187
188struct dss_pll {
189 const char *name;
190 enum dss_pll_id id;
191 struct dss_device *dss;
192
193 struct clk *clkin;
194 struct regulator *regulator;
195
196 void __iomem *base;
197
198 const struct dss_pll_hw *hw;
199
200 const struct dss_pll_ops *ops;
201
202 struct dss_pll_clock_info cinfo;
203};
204
205
206struct dss_reg_field {
207 u8 start, end;
208};
209
210struct dispc_clock_info {
211
212 unsigned long lck;
213 unsigned long pck;
214
215
216 u16 lck_div;
217 u16 pck_div;
218};
219
220struct dss_lcd_mgr_config {
221 enum dss_io_pad_mode io_pad_mode;
222
223 bool stallmode;
224 bool fifohandcheck;
225
226 struct dispc_clock_info clock_info;
227
228 int video_port_width;
229
230 int lcden_sig_polarity;
231};
232
233#define DSS_SZ_REGS SZ_512
234
235struct dss_device {
236 struct platform_device *pdev;
237 void __iomem *base;
238 struct regmap *syscon_pll_ctrl;
239 u32 syscon_pll_ctrl_offset;
240
241 struct platform_device *drm_pdev;
242
243 struct clk *parent_clk;
244 struct clk *dss_clk;
245 unsigned long dss_clk_rate;
246
247 unsigned long cache_req_pck;
248 unsigned long cache_prate;
249 struct dispc_clock_info cache_dispc_cinfo;
250
251 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
252 enum dss_clk_source dispc_clk_source;
253 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
254
255 bool ctx_valid;
256 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
257
258 const struct dss_features *feat;
259
260 struct {
261 struct dentry *root;
262 struct dss_debugfs_entry *clk;
263 struct dss_debugfs_entry *dss;
264 } debugfs;
265
266 struct dss_pll *plls[4];
267 struct dss_pll *video1_pll;
268 struct dss_pll *video2_pll;
269
270 struct dispc_device *dispc;
271 const struct dispc_ops *dispc_ops;
272 const struct dss_mgr_ops *mgr_ops;
273 struct omap_drm_private *mgr_ops_priv;
274};
275
276
277static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
278{
279
280 return 0;
281}
282
283static inline bool dss_mgr_is_lcd(enum omap_channel id)
284{
285 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
286 id == OMAP_DSS_CHANNEL_LCD3)
287 return true;
288 else
289 return false;
290}
291
292
293#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
294struct dss_debugfs_entry *
295dss_debugfs_create_file(struct dss_device *dss, const char *name,
296 int (*show_fn)(struct seq_file *s, void *data),
297 void *data);
298void dss_debugfs_remove_file(struct dss_debugfs_entry *entry);
299#else
300static inline struct dss_debugfs_entry *
301dss_debugfs_create_file(struct dss_device *dss, const char *name,
302 int (*show_fn)(struct seq_file *s, void *data),
303 void *data)
304{
305 return NULL;
306}
307
308static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
309{
310}
311#endif
312
313struct dss_device *dss_get_device(struct device *dev);
314
315int dss_runtime_get(struct dss_device *dss);
316void dss_runtime_put(struct dss_device *dss);
317
318unsigned long dss_get_dispc_clk_rate(struct dss_device *dss);
319unsigned long dss_get_max_fck_rate(struct dss_device *dss);
320int dss_dpi_select_source(struct dss_device *dss, int port,
321 enum omap_channel channel);
322void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
323 enum dss_hdmi_venc_clk_source_select src);
324const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
325
326
327struct dss_pll *dss_video_pll_init(struct dss_device *dss,
328 struct platform_device *pdev, int id,
329 struct regulator *regulator);
330void dss_video_pll_uninit(struct dss_pll *pll);
331
332void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
333
334void dss_sdi_init(struct dss_device *dss, int datapairs);
335int dss_sdi_enable(struct dss_device *dss);
336void dss_sdi_disable(struct dss_device *dss);
337
338void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
339 enum dss_clk_source clk_src);
340void dss_select_lcd_clk_source(struct dss_device *dss,
341 enum omap_channel channel,
342 enum dss_clk_source clk_src);
343enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss);
344enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
345 int dsi_module);
346enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
347 enum omap_channel channel);
348
349void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type);
350void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable);
351
352int dss_set_fck_rate(struct dss_device *dss, unsigned long rate);
353
354typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
355bool dss_div_calc(struct dss_device *dss, unsigned long pck,
356 unsigned long fck_min, dss_div_calc_func func, void *data);
357
358
359#ifdef CONFIG_OMAP2_DSS_SDI
360int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
361 struct device_node *port);
362void sdi_uninit_port(struct device_node *port);
363#else
364static inline int sdi_init_port(struct dss_device *dss,
365 struct platform_device *pdev,
366 struct device_node *port)
367{
368 return 0;
369}
370static inline void sdi_uninit_port(struct device_node *port)
371{
372}
373#endif
374
375
376
377#ifdef CONFIG_OMAP2_DSS_DSI
378
379void dsi_irq_handler(void);
380
381#endif
382
383
384#ifdef CONFIG_OMAP2_DSS_DPI
385int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
386 struct device_node *port, enum dss_model dss_model);
387void dpi_uninit_port(struct device_node *port);
388#else
389static inline int dpi_init_port(struct dss_device *dss,
390 struct platform_device *pdev,
391 struct device_node *port,
392 enum dss_model dss_model)
393{
394 return 0;
395}
396static inline void dpi_uninit_port(struct device_node *port)
397{
398}
399#endif
400
401
402void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
403
404int dispc_runtime_get(struct dispc_device *dispc);
405void dispc_runtime_put(struct dispc_device *dispc);
406
407void dispc_enable_sidle(struct dispc_device *dispc);
408void dispc_disable_sidle(struct dispc_device *dispc);
409
410void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
411void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
412void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
413
414typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
415 unsigned long pck, void *data);
416bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
417 unsigned long pck_min, unsigned long pck_max,
418 dispc_div_calc_func func, void *data);
419
420int dispc_calc_clock_rates(struct dispc_device *dispc,
421 unsigned long dispc_fclk_rate,
422 struct dispc_clock_info *cinfo);
423
424
425void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
426 enum omap_plane_id plane, u32 low, u32 high);
427void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
428 enum omap_plane_id plane,
429 u32 *fifo_low, u32 *fifo_high,
430 bool use_fifomerge, bool manual_update);
431
432void dispc_mgr_set_clock_div(struct dispc_device *dispc,
433 enum omap_channel channel,
434 const struct dispc_clock_info *cinfo);
435int dispc_mgr_get_clock_div(struct dispc_device *dispc,
436 enum omap_channel channel,
437 struct dispc_clock_info *cinfo);
438void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk);
439
440#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
441static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
442{
443 int b;
444 for (b = 0; b < 32; ++b) {
445 if (irqstatus & (1 << b))
446 irq_arr[b]++;
447 }
448}
449#endif
450
451
452typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
453 unsigned long clkdco, void *data);
454typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
455 void *data);
456
457int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
458void dss_pll_unregister(struct dss_pll *pll);
459struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name);
460struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
461 enum dss_clk_source src);
462unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
463int dss_pll_enable(struct dss_pll *pll);
464void dss_pll_disable(struct dss_pll *pll);
465int dss_pll_set_config(struct dss_pll *pll,
466 const struct dss_pll_clock_info *cinfo);
467
468bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
469 unsigned long out_min, unsigned long out_max,
470 dss_hsdiv_calc_func func, void *data);
471bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
472 unsigned long pll_min, unsigned long pll_max,
473 dss_pll_calc_func func, void *data);
474
475bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
476 unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
477
478int dss_pll_write_config_type_a(struct dss_pll *pll,
479 const struct dss_pll_clock_info *cinfo);
480int dss_pll_write_config_type_b(struct dss_pll *pll,
481 const struct dss_pll_clock_info *cinfo);
482int dss_pll_wait_reset_done(struct dss_pll *pll);
483
484extern struct platform_driver omap_dsshw_driver;
485extern struct platform_driver omap_dispchw_driver;
486#ifdef CONFIG_OMAP2_DSS_DSI
487extern struct platform_driver omap_dsihw_driver;
488#endif
489#ifdef CONFIG_OMAP2_DSS_VENC
490extern struct platform_driver omap_venchw_driver;
491#endif
492#ifdef CONFIG_OMAP4_DSS_HDMI
493extern struct platform_driver omapdss_hdmi4hw_driver;
494#endif
495#ifdef CONFIG_OMAP5_DSS_HDMI
496extern struct platform_driver omapdss_hdmi5hw_driver;
497#endif
498
499#endif
500