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15#ifndef _ROCKCHIP_DRM_VOP_H
16#define _ROCKCHIP_DRM_VOP_H
17
18
19
20
21
22#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
23#define VOP_MAJOR(version) ((version) >> 8)
24#define VOP_MINOR(version) ((version) & 0xff)
25
26enum vop_data_format {
27 VOP_FMT_ARGB8888 = 0,
28 VOP_FMT_RGB888,
29 VOP_FMT_RGB565,
30 VOP_FMT_YUV420SP = 4,
31 VOP_FMT_YUV422SP,
32 VOP_FMT_YUV444SP,
33};
34
35struct vop_reg {
36 uint32_t mask;
37 uint16_t offset;
38 uint8_t shift;
39 bool write_mask;
40 bool relaxed;
41};
42
43struct vop_modeset {
44 struct vop_reg htotal_pw;
45 struct vop_reg hact_st_end;
46 struct vop_reg hpost_st_end;
47 struct vop_reg vtotal_pw;
48 struct vop_reg vact_st_end;
49 struct vop_reg vpost_st_end;
50};
51
52struct vop_output {
53 struct vop_reg pin_pol;
54 struct vop_reg dp_pin_pol;
55 struct vop_reg edp_pin_pol;
56 struct vop_reg hdmi_pin_pol;
57 struct vop_reg mipi_pin_pol;
58 struct vop_reg rgb_pin_pol;
59 struct vop_reg dp_en;
60 struct vop_reg edp_en;
61 struct vop_reg hdmi_en;
62 struct vop_reg mipi_en;
63 struct vop_reg rgb_en;
64};
65
66struct vop_common {
67 struct vop_reg cfg_done;
68 struct vop_reg dsp_blank;
69 struct vop_reg data_blank;
70 struct vop_reg pre_dither_down;
71 struct vop_reg dither_down;
72 struct vop_reg dither_up;
73 struct vop_reg gate_en;
74 struct vop_reg mmu_en;
75 struct vop_reg out_mode;
76 struct vop_reg standby;
77};
78
79struct vop_misc {
80 struct vop_reg global_regdone_en;
81};
82
83struct vop_intr {
84 const int *intrs;
85 uint32_t nintrs;
86
87 struct vop_reg line_flag_num[2];
88 struct vop_reg enable;
89 struct vop_reg clear;
90 struct vop_reg status;
91};
92
93struct vop_scl_extension {
94 struct vop_reg cbcr_vsd_mode;
95 struct vop_reg cbcr_vsu_mode;
96 struct vop_reg cbcr_hsd_mode;
97 struct vop_reg cbcr_ver_scl_mode;
98 struct vop_reg cbcr_hor_scl_mode;
99 struct vop_reg yrgb_vsd_mode;
100 struct vop_reg yrgb_vsu_mode;
101 struct vop_reg yrgb_hsd_mode;
102 struct vop_reg yrgb_ver_scl_mode;
103 struct vop_reg yrgb_hor_scl_mode;
104 struct vop_reg line_load_mode;
105 struct vop_reg cbcr_axi_gather_num;
106 struct vop_reg yrgb_axi_gather_num;
107 struct vop_reg vsd_cbcr_gt2;
108 struct vop_reg vsd_cbcr_gt4;
109 struct vop_reg vsd_yrgb_gt2;
110 struct vop_reg vsd_yrgb_gt4;
111 struct vop_reg bic_coe_sel;
112 struct vop_reg cbcr_axi_gather_en;
113 struct vop_reg yrgb_axi_gather_en;
114 struct vop_reg lb_mode;
115};
116
117struct vop_scl_regs {
118 const struct vop_scl_extension *ext;
119
120 struct vop_reg scale_yrgb_x;
121 struct vop_reg scale_yrgb_y;
122 struct vop_reg scale_cbcr_x;
123 struct vop_reg scale_cbcr_y;
124};
125
126struct vop_win_phy {
127 const struct vop_scl_regs *scl;
128 const uint32_t *data_formats;
129 uint32_t nformats;
130
131 struct vop_reg enable;
132 struct vop_reg gate;
133 struct vop_reg format;
134 struct vop_reg rb_swap;
135 struct vop_reg act_info;
136 struct vop_reg dsp_info;
137 struct vop_reg dsp_st;
138 struct vop_reg yrgb_mst;
139 struct vop_reg uv_mst;
140 struct vop_reg yrgb_vir;
141 struct vop_reg uv_vir;
142
143 struct vop_reg dst_alpha_ctl;
144 struct vop_reg src_alpha_ctl;
145 struct vop_reg channel;
146};
147
148struct vop_win_data {
149 uint32_t base;
150 const struct vop_win_phy *phy;
151 enum drm_plane_type type;
152};
153
154struct vop_data {
155 uint32_t version;
156 const struct vop_intr *intr;
157 const struct vop_common *common;
158 const struct vop_misc *misc;
159 const struct vop_modeset *modeset;
160 const struct vop_output *output;
161 const struct vop_win_data *win;
162 unsigned int win_size;
163
164#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
165#define VOP_FEATURE_INTERNAL_RGB BIT(1)
166 u64 feature;
167};
168
169
170#define DSP_HOLD_VALID_INTR (1 << 0)
171#define FS_INTR (1 << 1)
172#define LINE_FLAG_INTR (1 << 2)
173#define BUS_ERROR_INTR (1 << 3)
174
175#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
176 LINE_FLAG_INTR | BUS_ERROR_INTR)
177
178#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
179#define FS_INTR_EN(x) ((x) << 5)
180#define LINE_FLAG_INTR_EN(x) ((x) << 6)
181#define BUS_ERROR_INTR_EN(x) ((x) << 7)
182#define DSP_HOLD_VALID_INTR_MASK (1 << 4)
183#define FS_INTR_MASK (1 << 5)
184#define LINE_FLAG_INTR_MASK (1 << 6)
185#define BUS_ERROR_INTR_MASK (1 << 7)
186
187#define INTR_CLR_SHIFT 8
188#define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
189#define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
190#define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
191#define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
192
193#define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
194#define DSP_LINE_NUM_MASK (0x1fff << 12)
195
196
197#define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
198#define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
199#define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
200#define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
201#define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
202#define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
203#define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
204#define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
205
206#define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
207
208
209
210
211#define ROCKCHIP_OUT_MODE_P888 0
212#define ROCKCHIP_OUT_MODE_P666 1
213#define ROCKCHIP_OUT_MODE_P565 2
214
215#define ROCKCHIP_OUT_MODE_AAAA 15
216
217enum alpha_mode {
218 ALPHA_STRAIGHT,
219 ALPHA_INVERSE,
220};
221
222enum global_blend_mode {
223 ALPHA_GLOBAL,
224 ALPHA_PER_PIX,
225 ALPHA_PER_PIX_GLOBAL,
226};
227
228enum alpha_cal_mode {
229 ALPHA_SATURATION,
230 ALPHA_NO_SATURATION,
231};
232
233enum color_mode {
234 ALPHA_SRC_PRE_MUL,
235 ALPHA_SRC_NO_PRE_MUL,
236};
237
238enum factor_mode {
239 ALPHA_ZERO,
240 ALPHA_ONE,
241 ALPHA_SRC,
242 ALPHA_SRC_INVERSE,
243 ALPHA_SRC_GLOBAL,
244};
245
246enum scale_mode {
247 SCALE_NONE = 0x0,
248 SCALE_UP = 0x1,
249 SCALE_DOWN = 0x2
250};
251
252enum lb_mode {
253 LB_YUV_3840X5 = 0x0,
254 LB_YUV_2560X8 = 0x1,
255 LB_RGB_3840X2 = 0x2,
256 LB_RGB_2560X4 = 0x3,
257 LB_RGB_1920X5 = 0x4,
258 LB_RGB_1280X8 = 0x5
259};
260
261enum sacle_up_mode {
262 SCALE_UP_BIL = 0x0,
263 SCALE_UP_BIC = 0x1
264};
265
266enum scale_down_mode {
267 SCALE_DOWN_BIL = 0x0,
268 SCALE_DOWN_AVG = 0x1
269};
270
271enum vop_pol {
272 HSYNC_POSITIVE = 0,
273 VSYNC_POSITIVE = 1,
274 DEN_NEGATIVE = 2,
275 DCLK_INVERT = 3
276};
277
278#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
279#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
280#define SCL_MAX_VSKIPLINES 4
281#define MIN_SCL_FT_AFTER_VSKIP 1
282
283static inline uint16_t scl_cal_scale(int src, int dst, int shift)
284{
285 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
286}
287
288static inline uint16_t scl_cal_scale2(int src, int dst)
289{
290 return ((src - 1) << 12) / (dst - 1);
291}
292
293#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
294#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
295#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
296
297static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
298 int vskiplines)
299{
300 int act_height;
301
302 act_height = (src_h + vskiplines - 1) / vskiplines;
303
304 if (act_height == dst_h)
305 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
306
307 return GET_SCL_FT_BILI_DN(act_height, dst_h);
308}
309
310static inline enum scale_mode scl_get_scl_mode(int src, int dst)
311{
312 if (src < dst)
313 return SCALE_UP;
314 else if (src > dst)
315 return SCALE_DOWN;
316
317 return SCALE_NONE;
318}
319
320static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
321{
322 uint32_t vskiplines;
323
324 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
325 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
326 break;
327
328 return vskiplines;
329}
330
331static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
332{
333 int lb_mode;
334
335 if (is_yuv) {
336 if (width > 1280)
337 lb_mode = LB_YUV_3840X5;
338 else
339 lb_mode = LB_YUV_2560X8;
340 } else {
341 if (width > 2560)
342 lb_mode = LB_RGB_3840X2;
343 else if (width > 1920)
344 lb_mode = LB_RGB_2560X4;
345 else
346 lb_mode = LB_RGB_1920X5;
347 }
348
349 return lb_mode;
350}
351
352extern const struct component_ops vop_component_ops;
353#endif
354
