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33#include <linux/kref.h>
34#include <rdma/ib_umem.h>
35#include <rdma/ib_user_verbs.h>
36#include <rdma/ib_cache.h>
37#include "mlx5_ib.h"
38
39static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
40{
41 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
42
43 ibcq->comp_handler(ibcq, ibcq->cq_context);
44}
45
46static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
47{
48 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
49 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
50 struct ib_cq *ibcq = &cq->ibcq;
51 struct ib_event event;
52
53 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
54 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
55 type, mcq->cqn);
56 return;
57 }
58
59 if (ibcq->event_handler) {
60 event.device = &dev->ib_dev;
61 event.event = IB_EVENT_CQ_ERR;
62 event.element.cq = ibcq;
63 ibcq->event_handler(&event, ibcq->cq_context);
64 }
65}
66
67static void *get_cqe(struct mlx5_ib_cq *cq, int n)
68{
69 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n);
70}
71
72static u8 sw_ownership_bit(int n, int nent)
73{
74 return (n & nent) ? 1 : 0;
75}
76
77static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
78{
79 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
80 struct mlx5_cqe64 *cqe64;
81
82 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
83
84 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
85 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
86 return cqe;
87 } else {
88 return NULL;
89 }
90}
91
92static void *next_cqe_sw(struct mlx5_ib_cq *cq)
93{
94 return get_sw_cqe(cq, cq->mcq.cons_index);
95}
96
97static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
98{
99 switch (wq->wr_data[idx]) {
100 case MLX5_IB_WR_UMR:
101 return 0;
102
103 case IB_WR_LOCAL_INV:
104 return IB_WC_LOCAL_INV;
105
106 case IB_WR_REG_MR:
107 return IB_WC_REG_MR;
108
109 default:
110 pr_warn("unknown completion status\n");
111 return 0;
112 }
113}
114
115static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
116 struct mlx5_ib_wq *wq, int idx)
117{
118 wc->wc_flags = 0;
119 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
120 case MLX5_OPCODE_RDMA_WRITE_IMM:
121 wc->wc_flags |= IB_WC_WITH_IMM;
122
123 case MLX5_OPCODE_RDMA_WRITE:
124 wc->opcode = IB_WC_RDMA_WRITE;
125 break;
126 case MLX5_OPCODE_SEND_IMM:
127 wc->wc_flags |= IB_WC_WITH_IMM;
128
129 case MLX5_OPCODE_SEND:
130 case MLX5_OPCODE_SEND_INVAL:
131 wc->opcode = IB_WC_SEND;
132 break;
133 case MLX5_OPCODE_RDMA_READ:
134 wc->opcode = IB_WC_RDMA_READ;
135 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
136 break;
137 case MLX5_OPCODE_ATOMIC_CS:
138 wc->opcode = IB_WC_COMP_SWAP;
139 wc->byte_len = 8;
140 break;
141 case MLX5_OPCODE_ATOMIC_FA:
142 wc->opcode = IB_WC_FETCH_ADD;
143 wc->byte_len = 8;
144 break;
145 case MLX5_OPCODE_ATOMIC_MASKED_CS:
146 wc->opcode = IB_WC_MASKED_COMP_SWAP;
147 wc->byte_len = 8;
148 break;
149 case MLX5_OPCODE_ATOMIC_MASKED_FA:
150 wc->opcode = IB_WC_MASKED_FETCH_ADD;
151 wc->byte_len = 8;
152 break;
153 case MLX5_OPCODE_UMR:
154 wc->opcode = get_umr_comp(wq, idx);
155 break;
156 }
157}
158
159enum {
160 MLX5_GRH_IN_BUFFER = 1,
161 MLX5_GRH_IN_CQE = 2,
162};
163
164static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
165 struct mlx5_ib_qp *qp)
166{
167 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
168 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
169 struct mlx5_ib_srq *srq;
170 struct mlx5_ib_wq *wq;
171 u16 wqe_ctr;
172 u8 roce_packet_type;
173 bool vlan_present;
174 u8 g;
175
176 if (qp->ibqp.srq || qp->ibqp.xrcd) {
177 struct mlx5_core_srq *msrq = NULL;
178
179 if (qp->ibqp.xrcd) {
180 msrq = mlx5_core_get_srq(dev->mdev,
181 be32_to_cpu(cqe->srqn));
182 srq = to_mibsrq(msrq);
183 } else {
184 srq = to_msrq(qp->ibqp.srq);
185 }
186 if (srq) {
187 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
188 wc->wr_id = srq->wrid[wqe_ctr];
189 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
190 if (msrq && atomic_dec_and_test(&msrq->refcount))
191 complete(&msrq->free);
192 }
193 } else {
194 wq = &qp->rq;
195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
196 ++wq->tail;
197 }
198 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
199
200 switch (cqe->op_own >> 4) {
201 case MLX5_CQE_RESP_WR_IMM:
202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
203 wc->wc_flags = IB_WC_WITH_IMM;
204 wc->ex.imm_data = cqe->imm_inval_pkey;
205 break;
206 case MLX5_CQE_RESP_SEND:
207 wc->opcode = IB_WC_RECV;
208 wc->wc_flags = IB_WC_IP_CSUM_OK;
209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
210 (cqe->hds_ip_ext & CQE_L4_OK))))
211 wc->wc_flags = 0;
212 break;
213 case MLX5_CQE_RESP_SEND_IMM:
214 wc->opcode = IB_WC_RECV;
215 wc->wc_flags = IB_WC_WITH_IMM;
216 wc->ex.imm_data = cqe->imm_inval_pkey;
217 break;
218 case MLX5_CQE_RESP_SEND_INV:
219 wc->opcode = IB_WC_RECV;
220 wc->wc_flags = IB_WC_WITH_INVALIDATE;
221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
222 break;
223 }
224 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
225 wc->dlid_path_bits = cqe->ml_path;
226 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
227 wc->wc_flags |= g ? IB_WC_GRH : 0;
228 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
229 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
230
231 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
232 &wc->pkey_index);
233 } else {
234 wc->pkey_index = 0;
235 }
236
237 if (ll != IB_LINK_LAYER_ETHERNET) {
238 wc->slid = be16_to_cpu(cqe->slid);
239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
240 return;
241 }
242
243 wc->slid = 0;
244 vlan_present = cqe->l4_l3_hdr_type & 0x1;
245 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
246 if (vlan_present) {
247 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
248 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
249 wc->wc_flags |= IB_WC_WITH_VLAN;
250 } else {
251 wc->sl = 0;
252 }
253
254 switch (roce_packet_type) {
255 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
256 wc->network_hdr_type = RDMA_NETWORK_IB;
257 break;
258 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
259 wc->network_hdr_type = RDMA_NETWORK_IPV6;
260 break;
261 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
262 wc->network_hdr_type = RDMA_NETWORK_IPV4;
263 break;
264 }
265 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
266}
267
268static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
269{
270 mlx5_ib_warn(dev, "dump error cqe\n");
271 mlx5_dump_err_cqe(dev->mdev, cqe);
272}
273
274static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
275 struct mlx5_err_cqe *cqe,
276 struct ib_wc *wc)
277{
278 int dump = 1;
279
280 switch (cqe->syndrome) {
281 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
282 wc->status = IB_WC_LOC_LEN_ERR;
283 break;
284 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
285 wc->status = IB_WC_LOC_QP_OP_ERR;
286 break;
287 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
288 wc->status = IB_WC_LOC_PROT_ERR;
289 break;
290 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
291 dump = 0;
292 wc->status = IB_WC_WR_FLUSH_ERR;
293 break;
294 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
295 wc->status = IB_WC_MW_BIND_ERR;
296 break;
297 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
298 wc->status = IB_WC_BAD_RESP_ERR;
299 break;
300 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
301 wc->status = IB_WC_LOC_ACCESS_ERR;
302 break;
303 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
304 wc->status = IB_WC_REM_INV_REQ_ERR;
305 break;
306 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
307 wc->status = IB_WC_REM_ACCESS_ERR;
308 break;
309 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
310 wc->status = IB_WC_REM_OP_ERR;
311 break;
312 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
313 wc->status = IB_WC_RETRY_EXC_ERR;
314 dump = 0;
315 break;
316 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
317 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
318 dump = 0;
319 break;
320 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
321 wc->status = IB_WC_REM_ABORT_ERR;
322 break;
323 default:
324 wc->status = IB_WC_GENERAL_ERR;
325 break;
326 }
327
328 wc->vendor_err = cqe->vendor_err_synd;
329 if (dump)
330 dump_cqe(dev, cqe);
331}
332
333static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
334{
335
336
337 return 0;
338}
339
340static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
341{
342 struct mlx5_wqe_data_seg *dpseg;
343 void *addr;
344
345 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
346 sizeof(struct mlx5_wqe_raddr_seg) +
347 sizeof(struct mlx5_wqe_atomic_seg);
348 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
349 return addr;
350}
351
352static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
353 uint16_t idx)
354{
355 void *addr;
356 int byte_count;
357 int i;
358
359 if (!is_atomic_response(qp, idx))
360 return;
361
362 byte_count = be32_to_cpu(cqe64->byte_cnt);
363 addr = mlx5_get_atomic_laddr(qp, idx);
364
365 if (byte_count == 4) {
366 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
367 } else {
368 for (i = 0; i < byte_count; i += 8) {
369 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
370 addr += 8;
371 }
372 }
373
374 return;
375}
376
377static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
378 u16 tail, u16 head)
379{
380 u16 idx;
381
382 do {
383 idx = tail & (qp->sq.wqe_cnt - 1);
384 handle_atomic(qp, cqe64, idx);
385 if (idx == head)
386 break;
387
388 tail = qp->sq.w_list[idx].next;
389 } while (1);
390 tail = qp->sq.w_list[idx].next;
391 qp->sq.last_poll = tail;
392}
393
394static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
395{
396 mlx5_frag_buf_free(dev->mdev, &buf->frag_buf);
397}
398
399static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
400 struct ib_sig_err *item)
401{
402 u16 syndrome = be16_to_cpu(cqe->syndrome);
403
404#define GUARD_ERR (1 << 13)
405#define APPTAG_ERR (1 << 12)
406#define REFTAG_ERR (1 << 11)
407
408 if (syndrome & GUARD_ERR) {
409 item->err_type = IB_SIG_BAD_GUARD;
410 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
411 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
412 } else
413 if (syndrome & REFTAG_ERR) {
414 item->err_type = IB_SIG_BAD_REFTAG;
415 item->expected = be32_to_cpu(cqe->expected_reftag);
416 item->actual = be32_to_cpu(cqe->actual_reftag);
417 } else
418 if (syndrome & APPTAG_ERR) {
419 item->err_type = IB_SIG_BAD_APPTAG;
420 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
421 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
422 } else {
423 pr_err("Got signature completion error with bad syndrome %04x\n",
424 syndrome);
425 }
426
427 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
428 item->key = be32_to_cpu(cqe->mkey);
429}
430
431static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
432 struct ib_wc *wc, int *npolled)
433{
434 struct mlx5_ib_wq *wq;
435 unsigned int cur;
436 unsigned int idx;
437 int np;
438 int i;
439
440 wq = &qp->sq;
441 cur = wq->head - wq->tail;
442 np = *npolled;
443
444 if (cur == 0)
445 return;
446
447 for (i = 0; i < cur && np < num_entries; i++) {
448 idx = wq->last_poll & (wq->wqe_cnt - 1);
449 wc->wr_id = wq->wrid[idx];
450 wc->status = IB_WC_WR_FLUSH_ERR;
451 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
452 wq->tail++;
453 np++;
454 wc->qp = &qp->ibqp;
455 wc++;
456 wq->last_poll = wq->w_list[idx].next;
457 }
458 *npolled = np;
459}
460
461static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
462 struct ib_wc *wc, int *npolled)
463{
464 struct mlx5_ib_wq *wq;
465 unsigned int cur;
466 int np;
467 int i;
468
469 wq = &qp->rq;
470 cur = wq->head - wq->tail;
471 np = *npolled;
472
473 if (cur == 0)
474 return;
475
476 for (i = 0; i < cur && np < num_entries; i++) {
477 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
478 wc->status = IB_WC_WR_FLUSH_ERR;
479 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
480 wq->tail++;
481 np++;
482 wc->qp = &qp->ibqp;
483 wc++;
484 }
485 *npolled = np;
486}
487
488static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
489 struct ib_wc *wc, int *npolled)
490{
491 struct mlx5_ib_qp *qp;
492
493 *npolled = 0;
494
495 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
496 sw_send_comp(qp, num_entries, wc + *npolled, npolled);
497 if (*npolled >= num_entries)
498 return;
499 }
500
501 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
502 sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
503 if (*npolled >= num_entries)
504 return;
505 }
506}
507
508static int mlx5_poll_one(struct mlx5_ib_cq *cq,
509 struct mlx5_ib_qp **cur_qp,
510 struct ib_wc *wc)
511{
512 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
513 struct mlx5_err_cqe *err_cqe;
514 struct mlx5_cqe64 *cqe64;
515 struct mlx5_core_qp *mqp;
516 struct mlx5_ib_wq *wq;
517 struct mlx5_sig_err_cqe *sig_err_cqe;
518 struct mlx5_core_mkey *mmkey;
519 struct mlx5_ib_mr *mr;
520 uint8_t opcode;
521 uint32_t qpn;
522 u16 wqe_ctr;
523 void *cqe;
524 int idx;
525
526repoll:
527 cqe = next_cqe_sw(cq);
528 if (!cqe)
529 return -EAGAIN;
530
531 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
532
533 ++cq->mcq.cons_index;
534
535
536
537
538 rmb();
539
540 opcode = cqe64->op_own >> 4;
541 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
542 if (likely(cq->resize_buf)) {
543 free_cq_buf(dev, &cq->buf);
544 cq->buf = *cq->resize_buf;
545 kfree(cq->resize_buf);
546 cq->resize_buf = NULL;
547 goto repoll;
548 } else {
549 mlx5_ib_warn(dev, "unexpected resize cqe\n");
550 }
551 }
552
553 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
554 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
555
556
557
558
559 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
560 *cur_qp = to_mibqp(mqp);
561 }
562
563 wc->qp = &(*cur_qp)->ibqp;
564 switch (opcode) {
565 case MLX5_CQE_REQ:
566 wq = &(*cur_qp)->sq;
567 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
568 idx = wqe_ctr & (wq->wqe_cnt - 1);
569 handle_good_req(wc, cqe64, wq, idx);
570 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
571 wc->wr_id = wq->wrid[idx];
572 wq->tail = wq->wqe_head[idx] + 1;
573 wc->status = IB_WC_SUCCESS;
574 break;
575 case MLX5_CQE_RESP_WR_IMM:
576 case MLX5_CQE_RESP_SEND:
577 case MLX5_CQE_RESP_SEND_IMM:
578 case MLX5_CQE_RESP_SEND_INV:
579 handle_responder(wc, cqe64, *cur_qp);
580 wc->status = IB_WC_SUCCESS;
581 break;
582 case MLX5_CQE_RESIZE_CQ:
583 break;
584 case MLX5_CQE_REQ_ERR:
585 case MLX5_CQE_RESP_ERR:
586 err_cqe = (struct mlx5_err_cqe *)cqe64;
587 mlx5_handle_error_cqe(dev, err_cqe, wc);
588 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
589 opcode == MLX5_CQE_REQ_ERR ?
590 "Requestor" : "Responder", cq->mcq.cqn);
591 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
592 err_cqe->syndrome, err_cqe->vendor_err_synd);
593 if (opcode == MLX5_CQE_REQ_ERR) {
594 wq = &(*cur_qp)->sq;
595 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
596 idx = wqe_ctr & (wq->wqe_cnt - 1);
597 wc->wr_id = wq->wrid[idx];
598 wq->tail = wq->wqe_head[idx] + 1;
599 } else {
600 struct mlx5_ib_srq *srq;
601
602 if ((*cur_qp)->ibqp.srq) {
603 srq = to_msrq((*cur_qp)->ibqp.srq);
604 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
605 wc->wr_id = srq->wrid[wqe_ctr];
606 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
607 } else {
608 wq = &(*cur_qp)->rq;
609 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
610 ++wq->tail;
611 }
612 }
613 break;
614 case MLX5_CQE_SIG_ERR:
615 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
616
617 read_lock(&dev->mdev->priv.mkey_table.lock);
618 mmkey = __mlx5_mr_lookup(dev->mdev,
619 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
620 mr = to_mibmr(mmkey);
621 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
622 mr->sig->sig_err_exists = true;
623 mr->sig->sigerr_count++;
624
625 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
626 cq->mcq.cqn, mr->sig->err_item.key,
627 mr->sig->err_item.err_type,
628 mr->sig->err_item.sig_err_offset,
629 mr->sig->err_item.expected,
630 mr->sig->err_item.actual);
631
632 read_unlock(&dev->mdev->priv.mkey_table.lock);
633 goto repoll;
634 }
635
636 return 0;
637}
638
639static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
640 struct ib_wc *wc, bool is_fatal_err)
641{
642 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
643 struct mlx5_ib_wc *soft_wc, *next;
644 int npolled = 0;
645
646 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
647 if (npolled >= num_entries)
648 break;
649
650 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
651 cq->mcq.cqn);
652
653 if (unlikely(is_fatal_err)) {
654 soft_wc->wc.status = IB_WC_WR_FLUSH_ERR;
655 soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
656 }
657 wc[npolled++] = soft_wc->wc;
658 list_del(&soft_wc->list);
659 kfree(soft_wc);
660 }
661
662 return npolled;
663}
664
665int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
666{
667 struct mlx5_ib_cq *cq = to_mcq(ibcq);
668 struct mlx5_ib_qp *cur_qp = NULL;
669 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
670 struct mlx5_core_dev *mdev = dev->mdev;
671 unsigned long flags;
672 int soft_polled = 0;
673 int npolled;
674
675 spin_lock_irqsave(&cq->lock, flags);
676 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
677
678 if (unlikely(!list_empty(&cq->wc_list)))
679 soft_polled = poll_soft_wc(cq, num_entries, wc, true);
680
681 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled,
682 wc + soft_polled, &npolled);
683 goto out;
684 }
685
686 if (unlikely(!list_empty(&cq->wc_list)))
687 soft_polled = poll_soft_wc(cq, num_entries, wc, false);
688
689 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
690 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
691 break;
692 }
693
694 if (npolled)
695 mlx5_cq_set_ci(&cq->mcq);
696out:
697 spin_unlock_irqrestore(&cq->lock, flags);
698
699 return soft_polled + npolled;
700}
701
702int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
703{
704 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
705 struct mlx5_ib_cq *cq = to_mcq(ibcq);
706 void __iomem *uar_page = mdev->priv.uar->map;
707 unsigned long irq_flags;
708 int ret = 0;
709
710 spin_lock_irqsave(&cq->lock, irq_flags);
711 if (cq->notify_flags != IB_CQ_NEXT_COMP)
712 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
713
714 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
715 ret = 1;
716 spin_unlock_irqrestore(&cq->lock, irq_flags);
717
718 mlx5_cq_arm(&cq->mcq,
719 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
720 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
721 uar_page, to_mcq(ibcq)->mcq.cons_index);
722
723 return ret;
724}
725
726static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev,
727 struct mlx5_ib_cq_buf *buf,
728 int nent,
729 int cqe_size)
730{
731 struct mlx5_frag_buf *frag_buf = &buf->frag_buf;
732 u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0);
733 u8 log_wq_sz = ilog2(cqe_size);
734 int err;
735
736 err = mlx5_frag_buf_alloc_node(dev->mdev,
737 nent * cqe_size,
738 frag_buf,
739 dev->mdev->priv.numa_node);
740 if (err)
741 return err;
742
743 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc);
744
745 buf->cqe_size = cqe_size;
746 buf->nent = nent;
747
748 return 0;
749}
750
751enum {
752 MLX5_CQE_RES_FORMAT_HASH = 0,
753 MLX5_CQE_RES_FORMAT_CSUM = 1,
754 MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3,
755};
756
757static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format)
758{
759 switch (format) {
760 case MLX5_IB_CQE_RES_FORMAT_HASH:
761 return MLX5_CQE_RES_FORMAT_HASH;
762 case MLX5_IB_CQE_RES_FORMAT_CSUM:
763 return MLX5_CQE_RES_FORMAT_CSUM;
764 case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX:
765 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
766 return MLX5_CQE_RES_FORMAT_CSUM_STRIDX;
767 return -EOPNOTSUPP;
768 default:
769 return -EINVAL;
770 }
771}
772
773static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
774 struct ib_ucontext *context, struct mlx5_ib_cq *cq,
775 int entries, u32 **cqb,
776 int *cqe_size, int *index, int *inlen)
777{
778 struct mlx5_ib_create_cq ucmd = {};
779 size_t ucmdlen;
780 int page_shift;
781 __be64 *pas;
782 int npages;
783 int ncont;
784 void *cqc;
785 int err;
786
787 ucmdlen = udata->inlen < sizeof(ucmd) ?
788 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd);
789
790 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
791 return -EFAULT;
792
793 if (ucmdlen == sizeof(ucmd) &&
794 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD)))
795 return -EINVAL;
796
797 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
798 return -EINVAL;
799
800 *cqe_size = ucmd.cqe_size;
801
802 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
803 entries * ucmd.cqe_size,
804 IB_ACCESS_LOCAL_WRITE, 1);
805 if (IS_ERR(cq->buf.umem)) {
806 err = PTR_ERR(cq->buf.umem);
807 return err;
808 }
809
810 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
811 &cq->db);
812 if (err)
813 goto err_umem;
814
815 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
816 &ncont, NULL);
817 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
818 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
819
820 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
821 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
822 *cqb = kvzalloc(*inlen, GFP_KERNEL);
823 if (!*cqb) {
824 err = -ENOMEM;
825 goto err_db;
826 }
827
828 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
829 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
830
831 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
832 MLX5_SET(cqc, cqc, log_page_size,
833 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
834
835 *index = to_mucontext(context)->bfregi.sys_pages[0];
836
837 if (ucmd.cqe_comp_en == 1) {
838 int mini_cqe_format;
839
840 if (!((*cqe_size == 128 &&
841 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
842 (*cqe_size == 64 &&
843 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
844 err = -EOPNOTSUPP;
845 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
846 *cqe_size);
847 goto err_cqb;
848 }
849
850 mini_cqe_format =
851 mini_cqe_res_format_to_hw(dev,
852 ucmd.cqe_comp_res_format);
853 if (mini_cqe_format < 0) {
854 err = mini_cqe_format;
855 mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n",
856 ucmd.cqe_comp_res_format, err);
857 goto err_cqb;
858 }
859
860 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
861 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format);
862 }
863
864 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
865 if (*cqe_size != 128 ||
866 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
867 err = -EOPNOTSUPP;
868 mlx5_ib_warn(dev,
869 "CQE padding is not supported for CQE size of %dB!\n",
870 *cqe_size);
871 goto err_cqb;
872 }
873
874 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
875 }
876
877 MLX5_SET(create_cq_in, *cqb, uid, to_mucontext(context)->devx_uid);
878 return 0;
879
880err_cqb:
881 kvfree(*cqb);
882
883err_db:
884 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
885
886err_umem:
887 ib_umem_release(cq->buf.umem);
888 return err;
889}
890
891static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
892{
893 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
894 ib_umem_release(cq->buf.umem);
895}
896
897static void init_cq_frag_buf(struct mlx5_ib_cq *cq,
898 struct mlx5_ib_cq_buf *buf)
899{
900 int i;
901 void *cqe;
902 struct mlx5_cqe64 *cqe64;
903
904 for (i = 0; i < buf->nent; i++) {
905 cqe = get_cqe(cq, i);
906 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
907 cqe64->op_own = MLX5_CQE_INVALID << 4;
908 }
909}
910
911static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
912 int entries, int cqe_size,
913 u32 **cqb, int *index, int *inlen)
914{
915 __be64 *pas;
916 void *cqc;
917 int err;
918
919 err = mlx5_db_alloc(dev->mdev, &cq->db);
920 if (err)
921 return err;
922
923 cq->mcq.set_ci_db = cq->db.db;
924 cq->mcq.arm_db = cq->db.db + 1;
925 cq->mcq.cqe_sz = cqe_size;
926
927 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size);
928 if (err)
929 goto err_db;
930
931 init_cq_frag_buf(cq, &cq->buf);
932
933 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
934 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) *
935 cq->buf.frag_buf.npages;
936 *cqb = kvzalloc(*inlen, GFP_KERNEL);
937 if (!*cqb) {
938 err = -ENOMEM;
939 goto err_buf;
940 }
941
942 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
943 mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas);
944
945 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
946 MLX5_SET(cqc, cqc, log_page_size,
947 cq->buf.frag_buf.page_shift -
948 MLX5_ADAPTER_PAGE_SHIFT);
949
950 *index = dev->mdev->priv.uar->index;
951
952 return 0;
953
954err_buf:
955 free_cq_buf(dev, &cq->buf);
956
957err_db:
958 mlx5_db_free(dev->mdev, &cq->db);
959 return err;
960}
961
962static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
963{
964 free_cq_buf(dev, &cq->buf);
965 mlx5_db_free(dev->mdev, &cq->db);
966}
967
968static void notify_soft_wc_handler(struct work_struct *work)
969{
970 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
971 notify_work);
972
973 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
974}
975
976struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
977 const struct ib_cq_init_attr *attr,
978 struct ib_ucontext *context,
979 struct ib_udata *udata)
980{
981 int entries = attr->cqe;
982 int vector = attr->comp_vector;
983 struct mlx5_ib_dev *dev = to_mdev(ibdev);
984 struct mlx5_ib_cq *cq;
985 int uninitialized_var(index);
986 int uninitialized_var(inlen);
987 u32 *cqb = NULL;
988 void *cqc;
989 int cqe_size;
990 unsigned int irqn;
991 int eqn;
992 int err;
993
994 if (entries < 0 ||
995 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
996 return ERR_PTR(-EINVAL);
997
998 if (check_cq_create_flags(attr->flags))
999 return ERR_PTR(-EOPNOTSUPP);
1000
1001 entries = roundup_pow_of_two(entries + 1);
1002 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
1003 return ERR_PTR(-EINVAL);
1004
1005 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
1006 if (!cq)
1007 return ERR_PTR(-ENOMEM);
1008
1009 cq->ibcq.cqe = entries - 1;
1010 mutex_init(&cq->resize_mutex);
1011 spin_lock_init(&cq->lock);
1012 cq->resize_buf = NULL;
1013 cq->resize_umem = NULL;
1014 cq->create_flags = attr->flags;
1015 INIT_LIST_HEAD(&cq->list_send_qp);
1016 INIT_LIST_HEAD(&cq->list_recv_qp);
1017
1018 if (context) {
1019 err = create_cq_user(dev, udata, context, cq, entries,
1020 &cqb, &cqe_size, &index, &inlen);
1021 if (err)
1022 goto err_create;
1023 } else {
1024 cqe_size = cache_line_size() == 128 ? 128 : 64;
1025 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
1026 &index, &inlen);
1027 if (err)
1028 goto err_create;
1029
1030 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
1031 }
1032
1033 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
1034 if (err)
1035 goto err_cqb;
1036
1037 cq->cqe_size = cqe_size;
1038
1039 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
1040 MLX5_SET(cqc, cqc, cqe_sz,
1041 cqe_sz_to_mlx_sz(cqe_size,
1042 cq->private_flags &
1043 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1044 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1045 MLX5_SET(cqc, cqc, uar_page, index);
1046 MLX5_SET(cqc, cqc, c_eqn, eqn);
1047 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
1048 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
1049 MLX5_SET(cqc, cqc, oi, 1);
1050
1051 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
1052 if (err)
1053 goto err_cqb;
1054
1055 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
1056 cq->mcq.irqn = irqn;
1057 if (context)
1058 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
1059 else
1060 cq->mcq.comp = mlx5_ib_cq_comp;
1061 cq->mcq.event = mlx5_ib_cq_event;
1062
1063 INIT_LIST_HEAD(&cq->wc_list);
1064
1065 if (context)
1066 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
1067 err = -EFAULT;
1068 goto err_cmd;
1069 }
1070
1071
1072 kvfree(cqb);
1073 return &cq->ibcq;
1074
1075err_cmd:
1076 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
1077
1078err_cqb:
1079 kvfree(cqb);
1080 if (context)
1081 destroy_cq_user(cq, context);
1082 else
1083 destroy_cq_kernel(dev, cq);
1084
1085err_create:
1086 kfree(cq);
1087
1088 return ERR_PTR(err);
1089}
1090
1091
1092int mlx5_ib_destroy_cq(struct ib_cq *cq)
1093{
1094 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1095 struct mlx5_ib_cq *mcq = to_mcq(cq);
1096 struct ib_ucontext *context = NULL;
1097
1098 if (cq->uobject)
1099 context = cq->uobject->context;
1100
1101 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1102 if (context)
1103 destroy_cq_user(mcq, context);
1104 else
1105 destroy_cq_kernel(dev, mcq);
1106
1107 kfree(mcq);
1108
1109 return 0;
1110}
1111
1112static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1113{
1114 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1115}
1116
1117void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1118{
1119 struct mlx5_cqe64 *cqe64, *dest64;
1120 void *cqe, *dest;
1121 u32 prod_index;
1122 int nfreed = 0;
1123 u8 owner_bit;
1124
1125 if (!cq)
1126 return;
1127
1128
1129
1130
1131
1132
1133
1134 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1135 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1136 break;
1137
1138
1139
1140
1141 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1142 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1143 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1144 if (is_equal_rsn(cqe64, rsn)) {
1145 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1146 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1147 ++nfreed;
1148 } else if (nfreed) {
1149 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1150 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1151 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1152 memcpy(dest, cqe, cq->mcq.cqe_sz);
1153 dest64->op_own = owner_bit |
1154 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1155 }
1156 }
1157
1158 if (nfreed) {
1159 cq->mcq.cons_index += nfreed;
1160
1161
1162
1163 wmb();
1164 mlx5_cq_set_ci(&cq->mcq);
1165 }
1166}
1167
1168void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1169{
1170 if (!cq)
1171 return;
1172
1173 spin_lock_irq(&cq->lock);
1174 __mlx5_ib_cq_clean(cq, qpn, srq);
1175 spin_unlock_irq(&cq->lock);
1176}
1177
1178int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1179{
1180 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1181 struct mlx5_ib_cq *mcq = to_mcq(cq);
1182 int err;
1183
1184 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1185 return -EOPNOTSUPP;
1186
1187 if (cq_period > MLX5_MAX_CQ_PERIOD)
1188 return -EINVAL;
1189
1190 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1191 cq_period, cq_count);
1192 if (err)
1193 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1194
1195 return err;
1196}
1197
1198static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1199 int entries, struct ib_udata *udata, int *npas,
1200 int *page_shift, int *cqe_size)
1201{
1202 struct mlx5_ib_resize_cq ucmd;
1203 struct ib_umem *umem;
1204 int err;
1205 int npages;
1206 struct ib_ucontext *context = cq->buf.umem->context;
1207
1208 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1209 if (err)
1210 return err;
1211
1212 if (ucmd.reserved0 || ucmd.reserved1)
1213 return -EINVAL;
1214
1215
1216 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1)
1217 return -EINVAL;
1218
1219 umem = ib_umem_get(context, ucmd.buf_addr,
1220 (size_t)ucmd.cqe_size * entries,
1221 IB_ACCESS_LOCAL_WRITE, 1);
1222 if (IS_ERR(umem)) {
1223 err = PTR_ERR(umem);
1224 return err;
1225 }
1226
1227 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1228 npas, NULL);
1229
1230 cq->resize_umem = umem;
1231 *cqe_size = ucmd.cqe_size;
1232
1233 return 0;
1234}
1235
1236static void un_resize_user(struct mlx5_ib_cq *cq)
1237{
1238 ib_umem_release(cq->resize_umem);
1239}
1240
1241static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1242 int entries, int cqe_size)
1243{
1244 int err;
1245
1246 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1247 if (!cq->resize_buf)
1248 return -ENOMEM;
1249
1250 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size);
1251 if (err)
1252 goto ex;
1253
1254 init_cq_frag_buf(cq, cq->resize_buf);
1255
1256 return 0;
1257
1258ex:
1259 kfree(cq->resize_buf);
1260 return err;
1261}
1262
1263static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1264{
1265 free_cq_buf(dev, cq->resize_buf);
1266 cq->resize_buf = NULL;
1267}
1268
1269static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1270{
1271 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1272 struct mlx5_cqe64 *scqe64;
1273 struct mlx5_cqe64 *dcqe64;
1274 void *start_cqe;
1275 void *scqe;
1276 void *dcqe;
1277 int ssize;
1278 int dsize;
1279 int i;
1280 u8 sw_own;
1281
1282 ssize = cq->buf.cqe_size;
1283 dsize = cq->resize_buf->cqe_size;
1284 if (ssize != dsize) {
1285 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1286 return -EINVAL;
1287 }
1288
1289 i = cq->mcq.cons_index;
1290 scqe = get_sw_cqe(cq, i);
1291 scqe64 = ssize == 64 ? scqe : scqe + 64;
1292 start_cqe = scqe;
1293 if (!scqe) {
1294 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1295 return -EINVAL;
1296 }
1297
1298 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1299 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc,
1300 (i + 1) & cq->resize_buf->nent);
1301 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1302 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1303 memcpy(dcqe, scqe, dsize);
1304 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1305
1306 ++i;
1307 scqe = get_sw_cqe(cq, i);
1308 scqe64 = ssize == 64 ? scqe : scqe + 64;
1309 if (!scqe) {
1310 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1311 return -EINVAL;
1312 }
1313
1314 if (scqe == start_cqe) {
1315 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1316 cq->mcq.cqn);
1317 return -ENOMEM;
1318 }
1319 }
1320 ++cq->mcq.cons_index;
1321 return 0;
1322}
1323
1324int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1325{
1326 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1327 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1328 void *cqc;
1329 u32 *in;
1330 int err;
1331 int npas;
1332 __be64 *pas;
1333 int page_shift;
1334 int inlen;
1335 int uninitialized_var(cqe_size);
1336 unsigned long flags;
1337
1338 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1339 pr_info("Firmware does not support resize CQ\n");
1340 return -ENOSYS;
1341 }
1342
1343 if (entries < 1 ||
1344 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1345 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1346 entries,
1347 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1348 return -EINVAL;
1349 }
1350
1351 entries = roundup_pow_of_two(entries + 1);
1352 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1353 return -EINVAL;
1354
1355 if (entries == ibcq->cqe + 1)
1356 return 0;
1357
1358 mutex_lock(&cq->resize_mutex);
1359 if (udata) {
1360 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1361 &cqe_size);
1362 } else {
1363 cqe_size = 64;
1364 err = resize_kernel(dev, cq, entries, cqe_size);
1365 if (!err) {
1366 struct mlx5_frag_buf *frag_buf = &cq->resize_buf->frag_buf;
1367
1368 npas = frag_buf->npages;
1369 page_shift = frag_buf->page_shift;
1370 }
1371 }
1372
1373 if (err)
1374 goto ex;
1375
1376 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1377 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1378
1379 in = kvzalloc(inlen, GFP_KERNEL);
1380 if (!in) {
1381 err = -ENOMEM;
1382 goto ex_resize;
1383 }
1384
1385 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1386 if (udata)
1387 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1388 pas, 0);
1389 else
1390 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas);
1391
1392 MLX5_SET(modify_cq_in, in,
1393 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1394 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1395 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1396 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1397
1398 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1399
1400 MLX5_SET(cqc, cqc, log_page_size,
1401 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1402 MLX5_SET(cqc, cqc, cqe_sz,
1403 cqe_sz_to_mlx_sz(cqe_size,
1404 cq->private_flags &
1405 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1406 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1407
1408 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1409 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1410
1411 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1412 if (err)
1413 goto ex_alloc;
1414
1415 if (udata) {
1416 cq->ibcq.cqe = entries - 1;
1417 ib_umem_release(cq->buf.umem);
1418 cq->buf.umem = cq->resize_umem;
1419 cq->resize_umem = NULL;
1420 } else {
1421 struct mlx5_ib_cq_buf tbuf;
1422 int resized = 0;
1423
1424 spin_lock_irqsave(&cq->lock, flags);
1425 if (cq->resize_buf) {
1426 err = copy_resize_cqes(cq);
1427 if (!err) {
1428 tbuf = cq->buf;
1429 cq->buf = *cq->resize_buf;
1430 kfree(cq->resize_buf);
1431 cq->resize_buf = NULL;
1432 resized = 1;
1433 }
1434 }
1435 cq->ibcq.cqe = entries - 1;
1436 spin_unlock_irqrestore(&cq->lock, flags);
1437 if (resized)
1438 free_cq_buf(dev, &tbuf);
1439 }
1440 mutex_unlock(&cq->resize_mutex);
1441
1442 kvfree(in);
1443 return 0;
1444
1445ex_alloc:
1446 kvfree(in);
1447
1448ex_resize:
1449 if (udata)
1450 un_resize_user(cq);
1451 else
1452 un_resize_kernel(dev, cq);
1453ex:
1454 mutex_unlock(&cq->resize_mutex);
1455 return err;
1456}
1457
1458int mlx5_ib_get_cqe_size(struct ib_cq *ibcq)
1459{
1460 struct mlx5_ib_cq *cq;
1461
1462 if (!ibcq)
1463 return 128;
1464
1465 cq = to_mcq(ibcq);
1466 return cq->cqe_size;
1467}
1468
1469
1470int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1471{
1472 struct mlx5_ib_wc *soft_wc;
1473 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1474 unsigned long flags;
1475
1476 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1477 if (!soft_wc)
1478 return -ENOMEM;
1479
1480 soft_wc->wc = *wc;
1481 spin_lock_irqsave(&cq->lock, flags);
1482 list_add_tail(&soft_wc->list, &cq->wc_list);
1483 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1484 wc->status != IB_WC_SUCCESS) {
1485 cq->notify_flags = 0;
1486 schedule_work(&cq->notify_work);
1487 }
1488 spin_unlock_irqrestore(&cq->lock, flags);
1489
1490 return 0;
1491}
1492
