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17#ifndef _SMI_PCIE_H_
18#define _SMI_PCIE_H_
19
20#include <linux/i2c.h>
21#include <linux/i2c-algo-bit.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/proc_fs.h>
27#include <linux/pci.h>
28#include <linux/dma-mapping.h>
29#include <linux/slab.h>
30#include <media/rc-core.h>
31
32#include <media/demux.h>
33#include <media/dmxdev.h>
34#include <media/dvb_demux.h>
35#include <media/dvb_frontend.h>
36#include <media/dvb_net.h>
37#include <media/dvbdev.h>
38
39
40#define MSI_CONTROL_REG_BASE 0x0800
41#define SYSTEM_CONTROL_REG_BASE 0x0880
42#define PCIE_EP_DEBUG_REG_BASE 0x08C0
43#define IR_CONTROL_REG_BASE 0x0900
44#define I2C_A_CONTROL_REG_BASE 0x0940
45#define I2C_B_CONTROL_REG_BASE 0x0980
46#define ATV_PORTA_CONTROL_REG_BASE 0x09C0
47#define DTV_PORTA_CONTROL_REG_BASE 0x0A00
48#define AES_PORTA_CONTROL_REG_BASE 0x0A80
49#define DMA_PORTA_CONTROL_REG_BASE 0x0AC0
50#define ATV_PORTB_CONTROL_REG_BASE 0x0B00
51#define DTV_PORTB_CONTROL_REG_BASE 0x0B40
52#define AES_PORTB_CONTROL_REG_BASE 0x0BC0
53#define DMA_PORTB_CONTROL_REG_BASE 0x0C00
54#define UART_A_REGISTER_BASE 0x0C40
55#define UART_B_REGISTER_BASE 0x0C80
56#define GPS_CONTROL_REG_BASE 0x0CC0
57#define DMA_PORTC_CONTROL_REG_BASE 0x0D00
58#define DMA_PORTD_CONTROL_REG_BASE 0x0D00
59#define AES_RANDOM_DATA_BASE 0x0D80
60#define AES_KEY_IN_BASE 0x0D90
61#define RANDOM_DATA_LIB_BASE 0x0E00
62#define IR_DATA_BUFFER_BASE 0x0F00
63#define PORTA_TS_BUFFER_BASE 0x1000
64#define PORTA_I2S_BUFFER_BASE 0x1400
65#define PORTB_TS_BUFFER_BASE 0x1800
66#define PORTB_I2S_BUFFER_BASE 0x1C00
67
68
69#define MSI_DELAY_TIMER (MSI_CONTROL_REG_BASE + 0x00)
70#define MSI_INT_STATUS (MSI_CONTROL_REG_BASE + 0x08)
71#define MSI_INT_STATUS_CLR (MSI_CONTROL_REG_BASE + 0x0C)
72#define MSI_INT_STATUS_SET (MSI_CONTROL_REG_BASE + 0x10)
73#define MSI_INT_ENA (MSI_CONTROL_REG_BASE + 0x14)
74#define MSI_INT_ENA_CLR (MSI_CONTROL_REG_BASE + 0x18)
75#define MSI_INT_ENA_SET (MSI_CONTROL_REG_BASE + 0x1C)
76#define MSI_SOFT_RESET (MSI_CONTROL_REG_BASE + 0x20)
77#define MSI_CFG_SRC0 (MSI_CONTROL_REG_BASE + 0x24)
78
79
80#define MUX_MODE_CTRL (SYSTEM_CONTROL_REG_BASE + 0x00)
81 #define rbPaMSMask 0x07
82 #define rbPaMSDtvNoGpio 0x00
83 #define rbPaMSDtv4bitGpio 0x01
84 #define rbPaMSDtv7bitGpio 0x02
85 #define rbPaMS8bitGpio 0x03
86 #define rbPaMSAtv 0x04
87 #define rbPbMSMask 0x38
88 #define rbPbMSDtvNoGpio 0x00
89 #define rbPbMSDtv4bitGpio 0x08
90 #define rbPbMSDtv7bitGpio 0x10
91 #define rbPbMS8bitGpio 0x18
92 #define rbPbMSAtv 0x20
93 #define rbPaAESEN 0x40
94 #define rbPbAESEN 0x80
95
96#define INTERNAL_RST (SYSTEM_CONTROL_REG_BASE + 0x04)
97#define PERIPHERAL_CTRL (SYSTEM_CONTROL_REG_BASE + 0x08)
98#define GPIO_0to7_CTRL (SYSTEM_CONTROL_REG_BASE + 0x0C)
99#define GPIO_8to15_CTRL (SYSTEM_CONTROL_REG_BASE + 0x10)
100#define GPIO_16to24_CTRL (SYSTEM_CONTROL_REG_BASE + 0x14)
101#define GPIO_INT_SRC_CFG (SYSTEM_CONTROL_REG_BASE + 0x18)
102#define SYS_BUF_STATUS (SYSTEM_CONTROL_REG_BASE + 0x1C)
103#define PCIE_IP_REG_ACS (SYSTEM_CONTROL_REG_BASE + 0x20)
104#define PCIE_IP_REG_ACS_ADDR (SYSTEM_CONTROL_REG_BASE + 0x24)
105#define PCIE_IP_REG_ACS_DATA (SYSTEM_CONTROL_REG_BASE + 0x28)
106
107
108#define IR_Init_Reg (IR_CONTROL_REG_BASE + 0x00)
109#define IR_Idle_Cnt_Low (IR_CONTROL_REG_BASE + 0x04)
110#define IR_Idle_Cnt_High (IR_CONTROL_REG_BASE + 0x05)
111#define IR_Unit_Cnt_Low (IR_CONTROL_REG_BASE + 0x06)
112#define IR_Unit_Cnt_High (IR_CONTROL_REG_BASE + 0x07)
113#define IR_Data_Cnt (IR_CONTROL_REG_BASE + 0x08)
114#define rbIRen 0x80
115#define rbIRhighidle 0x10
116#define rbIRlowidle 0x00
117#define rbIRVld 0x04
118
119
120#define I2C_A_CTL_STATUS (I2C_A_CONTROL_REG_BASE + 0x00)
121#define I2C_A_ADDR (I2C_A_CONTROL_REG_BASE + 0x04)
122#define I2C_A_SW_CTL (I2C_A_CONTROL_REG_BASE + 0x08)
123#define I2C_A_TIME_OUT_CNT (I2C_A_CONTROL_REG_BASE + 0x0C)
124#define I2C_A_FIFO_STATUS (I2C_A_CONTROL_REG_BASE + 0x10)
125#define I2C_A_FS_EN (I2C_A_CONTROL_REG_BASE + 0x14)
126#define I2C_A_FIFO_DATA (I2C_A_CONTROL_REG_BASE + 0x20)
127
128
129#define I2C_B_CTL_STATUS (I2C_B_CONTROL_REG_BASE + 0x00)
130#define I2C_B_ADDR (I2C_B_CONTROL_REG_BASE + 0x04)
131#define I2C_B_SW_CTL (I2C_B_CONTROL_REG_BASE + 0x08)
132#define I2C_B_TIME_OUT_CNT (I2C_B_CONTROL_REG_BASE + 0x0C)
133#define I2C_B_FIFO_STATUS (I2C_B_CONTROL_REG_BASE + 0x10)
134#define I2C_B_FS_EN (I2C_B_CONTROL_REG_BASE + 0x14)
135#define I2C_B_FIFO_DATA (I2C_B_CONTROL_REG_BASE + 0x20)
136
137#define VIDEO_CTRL_STATUS_A (ATV_PORTA_CONTROL_REG_BASE + 0x04)
138
139
140#define MPEG2_CTRL_A (DTV_PORTA_CONTROL_REG_BASE + 0x00)
141#define SERIAL_IN_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x4C)
142#define VLD_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x60)
143#define ERR_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x64)
144#define BRD_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x68)
145
146
147#define DMA_PORTA_CHAN0_ADDR_LOW (DMA_PORTA_CONTROL_REG_BASE + 0x00)
148#define DMA_PORTA_CHAN0_ADDR_HI (DMA_PORTA_CONTROL_REG_BASE + 0x04)
149#define DMA_PORTA_CHAN0_TRANS_STATE (DMA_PORTA_CONTROL_REG_BASE + 0x08)
150#define DMA_PORTA_CHAN0_CONTROL (DMA_PORTA_CONTROL_REG_BASE + 0x0C)
151#define DMA_PORTA_CHAN1_ADDR_LOW (DMA_PORTA_CONTROL_REG_BASE + 0x10)
152#define DMA_PORTA_CHAN1_ADDR_HI (DMA_PORTA_CONTROL_REG_BASE + 0x14)
153#define DMA_PORTA_CHAN1_TRANS_STATE (DMA_PORTA_CONTROL_REG_BASE + 0x18)
154#define DMA_PORTA_CHAN1_CONTROL (DMA_PORTA_CONTROL_REG_BASE + 0x1C)
155#define DMA_PORTA_MANAGEMENT (DMA_PORTA_CONTROL_REG_BASE + 0x20)
156#define VIDEO_CTRL_STATUS_B (ATV_PORTB_CONTROL_REG_BASE + 0x04)
157
158
159#define MPEG2_CTRL_B (DTV_PORTB_CONTROL_REG_BASE + 0x00)
160#define SERIAL_IN_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x4C)
161#define VLD_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x60)
162#define ERR_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x64)
163#define BRD_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x68)
164
165
166#define AES_CTRL_B (AES_PORTB_CONTROL_REG_BASE + 0x00)
167#define AES_KEY_BASE_B (AES_PORTB_CONTROL_REG_BASE + 0x04)
168
169
170#define DMA_PORTB_CHAN0_ADDR_LOW (DMA_PORTB_CONTROL_REG_BASE + 0x00)
171#define DMA_PORTB_CHAN0_ADDR_HI (DMA_PORTB_CONTROL_REG_BASE + 0x04)
172#define DMA_PORTB_CHAN0_TRANS_STATE (DMA_PORTB_CONTROL_REG_BASE + 0x08)
173#define DMA_PORTB_CHAN0_CONTROL (DMA_PORTB_CONTROL_REG_BASE + 0x0C)
174#define DMA_PORTB_CHAN1_ADDR_LOW (DMA_PORTB_CONTROL_REG_BASE + 0x10)
175#define DMA_PORTB_CHAN1_ADDR_HI (DMA_PORTB_CONTROL_REG_BASE + 0x14)
176#define DMA_PORTB_CHAN1_TRANS_STATE (DMA_PORTB_CONTROL_REG_BASE + 0x18)
177#define DMA_PORTB_CHAN1_CONTROL (DMA_PORTB_CONTROL_REG_BASE + 0x1C)
178#define DMA_PORTB_MANAGEMENT (DMA_PORTB_CONTROL_REG_BASE + 0x20)
179
180#define DMA_TRANS_UNIT_188 (0x00000007)
181
182
183#define DMA_A_CHAN0_DONE_INT (0x00000001)
184#define DMA_A_CHAN1_DONE_INT (0x00000002)
185#define DMA_B_CHAN0_DONE_INT (0x00000004)
186#define DMA_B_CHAN1_DONE_INT (0x00000008)
187#define DMA_C_CHAN0_DONE_INT (0x00000010)
188#define DMA_C_CHAN1_DONE_INT (0x00000020)
189#define DMA_D_CHAN0_DONE_INT (0x00000040)
190#define DMA_D_CHAN1_DONE_INT (0x00000080)
191#define DATA_BUF_OVERFLOW_INT (0x00000100)
192#define UART_0_X_INT (0x00000200)
193#define UART_1_X_INT (0x00000400)
194#define IR_X_INT (0x00000800)
195#define GPIO_0_INT (0x00001000)
196#define GPIO_1_INT (0x00002000)
197#define GPIO_2_INT (0x00004000)
198#define GPIO_3_INT (0x00008000)
199#define ALL_INT (0x0000FFFF)
200
201
202#define SW_I2C_MSK_MODE 0x01
203#define SW_I2C_MSK_CLK_OUT 0x02
204#define SW_I2C_MSK_DAT_OUT 0x04
205#define SW_I2C_MSK_CLK_EN 0x08
206#define SW_I2C_MSK_DAT_EN 0x10
207#define SW_I2C_MSK_DAT_IN 0x40
208#define SW_I2C_MSK_CLK_IN 0x80
209
210#define SMI_VID 0x1ADE
211#define SMI_PID 0x3038
212#define SMI_TS_DMA_BUF_SIZE (1024 * 188)
213
214struct smi_cfg_info {
215#define SMI_DVBSKY_S952 0
216#define SMI_DVBSKY_S950 1
217#define SMI_DVBSKY_T9580 2
218#define SMI_DVBSKY_T982 3
219#define SMI_TECHNOTREND_S2_4200 4
220 int type;
221 char *name;
222#define SMI_TS_NULL 0
223#define SMI_TS_DMA_SINGLE 1
224#define SMI_TS_DMA_BOTH 3
225
226
227
228 int ts_0;
229 int ts_1;
230#define DVBSKY_FE_NULL 0
231#define DVBSKY_FE_M88RS6000 1
232#define DVBSKY_FE_M88DS3103 2
233#define DVBSKY_FE_SIT2 3
234 int fe_0;
235 int fe_1;
236 char *rc_map;
237};
238
239struct smi_rc {
240 struct smi_dev *dev;
241 struct rc_dev *rc_dev;
242 char input_phys[64];
243 char device_name[64];
244 struct work_struct work;
245 u8 irData[256];
246
247 int users;
248};
249
250struct smi_port {
251 struct smi_dev *dev;
252 int idx;
253 int enable;
254 int fe_type;
255
256 u32 DMA_CHAN0_ADDR_LOW;
257 u32 DMA_CHAN0_ADDR_HI;
258 u32 DMA_CHAN0_TRANS_STATE;
259 u32 DMA_CHAN0_CONTROL;
260 u32 DMA_CHAN1_ADDR_LOW;
261 u32 DMA_CHAN1_ADDR_HI;
262 u32 DMA_CHAN1_TRANS_STATE;
263 u32 DMA_CHAN1_CONTROL;
264 u32 DMA_MANAGEMENT;
265
266 dma_addr_t dma_addr[2];
267 u8 *cpu_addr[2];
268 u32 _dmaInterruptCH0;
269 u32 _dmaInterruptCH1;
270 u32 _int_status;
271 struct tasklet_struct tasklet;
272
273 struct dmx_frontend hw_frontend;
274 struct dmx_frontend mem_frontend;
275 struct dmxdev dmxdev;
276 struct dvb_adapter dvb_adapter;
277 struct dvb_demux demux;
278 struct dvb_net dvbnet;
279 int users;
280 struct dvb_frontend *fe;
281
282 struct i2c_client *i2c_client_demod;
283 struct i2c_client *i2c_client_tuner;
284};
285
286struct smi_dev {
287 int nr;
288 struct smi_cfg_info *info;
289
290
291 struct pci_dev *pci_dev;
292 u32 __iomem *lmmio;
293
294
295 struct smi_port ts_port[2];
296
297
298 struct i2c_adapter i2c_bus[2];
299 struct i2c_algo_bit_data i2c_bit[2];
300
301
302 struct smi_rc ir;
303};
304
305#define smi_read(reg) readl(dev->lmmio + ((reg)>>2))
306#define smi_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
307
308#define smi_andor(reg, mask, value) \
309 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
310 ((value) & (mask)), dev->lmmio+((reg)>>2))
311
312#define smi_set(reg, bit) smi_andor((reg), (bit), (bit))
313#define smi_clear(reg, bit) smi_andor((reg), (bit), 0)
314
315int smi_ir_irq(struct smi_rc *ir, u32 int_status);
316void smi_ir_start(struct smi_rc *ir);
317void smi_ir_exit(struct smi_dev *dev);
318int smi_ir_init(struct smi_dev *dev);
319
320#endif
321