1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/types.h>
73#include <linux/compiler.h>
74#include <linux/delay.h>
75#include <linux/interrupt.h>
76#include <linux/ioport.h>
77#include <linux/pci.h>
78#include <linux/netdevice.h>
79#include <linux/etherdevice.h>
80#include <linux/skbuff.h>
81#include <linux/ethtool.h>
82#include <linux/mii.h>
83#include <linux/if_vlan.h>
84#include <linux/ctype.h>
85#include <linux/crc32.h>
86#include <linux/dma-mapping.h>
87
88#include <asm/io.h>
89#include <asm/byteorder.h>
90#include <linux/uaccess.h>
91
92#if IS_ENABLED(CONFIG_VLAN_8021Q)
93#define AMD8111E_VLAN_TAG_USED 1
94#else
95#define AMD8111E_VLAN_TAG_USED 0
96#endif
97
98#include "amd8111e.h"
99#define MODULE_NAME "amd8111e"
100#define MODULE_VERS "3.0.7"
101MODULE_AUTHOR("Advanced Micro Devices, Inc.");
102MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS);
103MODULE_LICENSE("GPL");
104module_param_array(speed_duplex, int, NULL, 0);
105MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotiate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
106module_param_array(coalesce, bool, NULL, 0);
107MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
108module_param_array(dynamic_ipg, bool, NULL, 0);
109MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
110
111
112static int amd8111e_read_phy(struct amd8111e_priv *lp,
113 int phy_id, int reg, u32 *val)
114{
115 void __iomem *mmio = lp->mmio;
116 unsigned int reg_val;
117 unsigned int repeat= REPEAT_CNT;
118
119 reg_val = readl(mmio + PHY_ACCESS);
120 while (reg_val & PHY_CMD_ACTIVE)
121 reg_val = readl( mmio + PHY_ACCESS );
122
123 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
124 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
125 do{
126 reg_val = readl(mmio + PHY_ACCESS);
127 udelay(30);
128 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
129 if(reg_val & PHY_RD_ERR)
130 goto err_phy_read;
131
132 *val = reg_val & 0xffff;
133 return 0;
134err_phy_read:
135 *val = 0;
136 return -EINVAL;
137
138}
139
140
141static int amd8111e_write_phy(struct amd8111e_priv *lp,
142 int phy_id, int reg, u32 val)
143{
144 unsigned int repeat = REPEAT_CNT;
145 void __iomem *mmio = lp->mmio;
146 unsigned int reg_val;
147
148 reg_val = readl(mmio + PHY_ACCESS);
149 while (reg_val & PHY_CMD_ACTIVE)
150 reg_val = readl( mmio + PHY_ACCESS );
151
152 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
153 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
154
155 do{
156 reg_val = readl(mmio + PHY_ACCESS);
157 udelay(30);
158 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
159
160 if(reg_val & PHY_RD_ERR)
161 goto err_phy_write;
162
163 return 0;
164
165err_phy_write:
166 return -EINVAL;
167
168}
169
170
171static int amd8111e_mdio_read(struct net_device *dev, int phy_id, int reg_num)
172{
173 struct amd8111e_priv *lp = netdev_priv(dev);
174 unsigned int reg_val;
175
176 amd8111e_read_phy(lp,phy_id,reg_num,®_val);
177 return reg_val;
178
179}
180
181
182static void amd8111e_mdio_write(struct net_device *dev,
183 int phy_id, int reg_num, int val)
184{
185 struct amd8111e_priv *lp = netdev_priv(dev);
186
187 amd8111e_write_phy(lp, phy_id, reg_num, val);
188}
189
190
191
192
193static void amd8111e_set_ext_phy(struct net_device *dev)
194{
195 struct amd8111e_priv *lp = netdev_priv(dev);
196 u32 bmcr,advert,tmp;
197
198
199 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
200 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
201 switch (lp->ext_phy_option){
202
203 default:
204 case SPEED_AUTONEG:
205 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
206 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
207 break;
208 case SPEED10_HALF:
209 tmp |= ADVERTISE_10HALF;
210 break;
211 case SPEED10_FULL:
212 tmp |= ADVERTISE_10FULL;
213 break;
214 case SPEED100_HALF:
215 tmp |= ADVERTISE_100HALF;
216 break;
217 case SPEED100_FULL:
218 tmp |= ADVERTISE_100FULL;
219 break;
220 }
221
222 if(advert != tmp)
223 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
224
225 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
226 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
227 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
228
229}
230
231
232
233
234static int amd8111e_free_skbs(struct net_device *dev)
235{
236 struct amd8111e_priv *lp = netdev_priv(dev);
237 struct sk_buff *rx_skbuff;
238 int i;
239
240
241 for(i = 0; i < NUM_TX_BUFFERS; i++){
242 if(lp->tx_skbuff[i]){
243 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
244 dev_kfree_skb (lp->tx_skbuff[i]);
245 lp->tx_skbuff[i] = NULL;
246 lp->tx_dma_addr[i] = 0;
247 }
248 }
249
250 for (i = 0; i < NUM_RX_BUFFERS; i++){
251 rx_skbuff = lp->rx_skbuff[i];
252 if(rx_skbuff != NULL){
253 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
254 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
255 dev_kfree_skb(lp->rx_skbuff[i]);
256 lp->rx_skbuff[i] = NULL;
257 lp->rx_dma_addr[i] = 0;
258 }
259 }
260
261 return 0;
262}
263
264
265
266
267static inline void amd8111e_set_rx_buff_len(struct net_device *dev)
268{
269 struct amd8111e_priv *lp = netdev_priv(dev);
270 unsigned int mtu = dev->mtu;
271
272 if (mtu > ETH_DATA_LEN){
273
274
275
276 lp->rx_buff_len = mtu + ETH_HLEN + 10;
277 lp->options |= OPTION_JUMBO_ENABLE;
278 } else{
279 lp->rx_buff_len = PKT_BUFF_SZ;
280 lp->options &= ~OPTION_JUMBO_ENABLE;
281 }
282}
283
284
285
286
287
288
289static int amd8111e_init_ring(struct net_device *dev)
290{
291 struct amd8111e_priv *lp = netdev_priv(dev);
292 int i;
293
294 lp->rx_idx = lp->tx_idx = 0;
295 lp->tx_complete_idx = 0;
296 lp->tx_ring_idx = 0;
297
298
299 if(lp->opened)
300
301 amd8111e_free_skbs(dev);
302
303 else{
304
305 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
306 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
307 &lp->tx_ring_dma_addr)) == NULL)
308
309 goto err_no_mem;
310
311 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
312 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
313 &lp->rx_ring_dma_addr)) == NULL)
314
315 goto err_free_tx_ring;
316
317 }
318
319 amd8111e_set_rx_buff_len(dev);
320
321
322 for (i = 0; i < NUM_RX_BUFFERS; i++) {
323
324 lp->rx_skbuff[i] = netdev_alloc_skb(dev, lp->rx_buff_len);
325 if (!lp->rx_skbuff[i]) {
326
327 for(--i; i >= 0 ;i--)
328 dev_kfree_skb(lp->rx_skbuff[i]);
329 goto err_free_rx_ring;
330 }
331 skb_reserve(lp->rx_skbuff[i],2);
332 }
333
334 for (i = 0; i < NUM_RX_BUFFERS; i++) {
335 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
336 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
337
338 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
339 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
340 wmb();
341 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
342 }
343
344
345 for (i = 0; i < NUM_TX_RING_DR; i++) {
346 lp->tx_ring[i].buff_phy_addr = 0;
347 lp->tx_ring[i].tx_flags = 0;
348 lp->tx_ring[i].buff_count = 0;
349 }
350
351 return 0;
352
353err_free_rx_ring:
354
355 pci_free_consistent(lp->pci_dev,
356 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
357 lp->rx_ring_dma_addr);
358
359err_free_tx_ring:
360
361 pci_free_consistent(lp->pci_dev,
362 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
363 lp->tx_ring_dma_addr);
364
365err_no_mem:
366 return -ENOMEM;
367}
368
369
370
371
372static int amd8111e_set_coalesce(struct net_device *dev, enum coal_mode cmod)
373{
374 unsigned int timeout;
375 unsigned int event_count;
376
377 struct amd8111e_priv *lp = netdev_priv(dev);
378 void __iomem *mmio = lp->mmio;
379 struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
380
381
382 switch(cmod)
383 {
384 case RX_INTR_COAL :
385 timeout = coal_conf->rx_timeout;
386 event_count = coal_conf->rx_event_count;
387 if( timeout > MAX_TIMEOUT ||
388 event_count > MAX_EVENT_COUNT )
389 return -EINVAL;
390
391 timeout = timeout * DELAY_TIMER_CONV;
392 writel(VAL0|STINTEN, mmio+INTEN0);
393 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
394 mmio+DLY_INT_A);
395 break;
396
397 case TX_INTR_COAL :
398 timeout = coal_conf->tx_timeout;
399 event_count = coal_conf->tx_event_count;
400 if( timeout > MAX_TIMEOUT ||
401 event_count > MAX_EVENT_COUNT )
402 return -EINVAL;
403
404
405 timeout = timeout * DELAY_TIMER_CONV;
406 writel(VAL0|STINTEN,mmio+INTEN0);
407 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
408 mmio+DLY_INT_B);
409 break;
410
411 case DISABLE_COAL:
412 writel(0,mmio+STVAL);
413 writel(STINTEN, mmio+INTEN0);
414 writel(0, mmio +DLY_INT_B);
415 writel(0, mmio+DLY_INT_A);
416 break;
417 case ENABLE_COAL:
418
419 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL);
420 writel(VAL0|STINTEN, mmio+INTEN0);
421 break;
422 default:
423 break;
424
425 }
426 return 0;
427
428}
429
430
431static int amd8111e_restart(struct net_device *dev)
432{
433 struct amd8111e_priv *lp = netdev_priv(dev);
434 void __iomem *mmio = lp->mmio;
435 int i,reg_val;
436
437
438 writel(RUN, mmio + CMD0);
439
440 if(amd8111e_init_ring(dev))
441 return -ENOMEM;
442
443
444 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
445 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
446
447 amd8111e_set_ext_phy(dev);
448
449
450 reg_val = readl(mmio + CTRL1);
451 reg_val &= ~XMTSP_MASK;
452 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
453
454
455 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
456 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
457 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
458
459 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
460
461
462 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
463 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
464
465 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
466 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
467
468
469 writew((u32)DEFAULT_IPG,mmio+IPG);
470 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
471
472 if(lp->options & OPTION_JUMBO_ENABLE){
473 writel((u32)VAL2|JUMBO, mmio + CMD3);
474
475 writel( REX_UFLO, mmio + CMD2);
476
477 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
478 }else{
479 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
480 writel((u32)JUMBO, mmio + CMD3);
481 }
482
483#if AMD8111E_VLAN_TAG_USED
484 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
485#endif
486 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
487
488
489 for (i = 0; i < ETH_ALEN; i++)
490 writeb( dev->dev_addr[i], mmio + PADR + i );
491
492
493 if(lp->options & OPTION_INTR_COAL_ENABLE){
494 netdev_info(dev, "Interrupt Coalescing Enabled.\n");
495 amd8111e_set_coalesce(dev,ENABLE_COAL);
496 }
497
498
499 writel(VAL2 | RDMD0, mmio + CMD0);
500 writel(VAL0 | INTREN | RUN, mmio + CMD0);
501
502
503 readl(mmio+CMD0);
504 return 0;
505}
506
507
508static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
509{
510 unsigned int reg_val;
511 unsigned int logic_filter[2] ={0,};
512 void __iomem *mmio = lp->mmio;
513
514
515
516 writel(RUN, mmio + CMD0);
517
518
519 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
520
521
522 writel(0, mmio + RCV_RING_BASE_ADDR0);
523
524
525 writel(0, mmio + XMT_RING_BASE_ADDR0);
526 writel(0, mmio + XMT_RING_BASE_ADDR1);
527 writel(0, mmio + XMT_RING_BASE_ADDR2);
528 writel(0, mmio + XMT_RING_BASE_ADDR3);
529
530
531 writel(CMD0_CLEAR,mmio + CMD0);
532
533
534 writel(CMD2_CLEAR, mmio +CMD2);
535
536
537 writel(CMD7_CLEAR , mmio + CMD7);
538
539
540 writel(0x0, mmio + DLY_INT_A);
541 writel(0x0, mmio + DLY_INT_B);
542
543
544 writel(0x0, mmio + FLOW_CONTROL);
545
546
547 reg_val = readl(mmio + INT0);
548 writel(reg_val, mmio + INT0);
549
550
551 writel(0x0, mmio + STVAL);
552
553
554 writel( INTEN0_CLEAR, mmio + INTEN0);
555
556
557 writel(0x0 , mmio + LADRF);
558
559
560 writel( 0x80010,mmio + SRAM_SIZE);
561
562
563 writel(0x0, mmio + RCV_RING_LEN0);
564
565
566 writel(0x0, mmio + XMT_RING_LEN0);
567 writel(0x0, mmio + XMT_RING_LEN1);
568 writel(0x0, mmio + XMT_RING_LEN2);
569 writel(0x0, mmio + XMT_RING_LEN3);
570
571
572 writel(0x0, mmio + XMT_RING_LIMIT);
573
574
575 writew(MIB_CLEAR, mmio + MIB_ADDR);
576
577
578 amd8111e_writeq(*(u64 *)logic_filter, mmio + LADRF);
579
580
581 reg_val = readl(mmio + SRAM_SIZE);
582
583 if(lp->options & OPTION_JUMBO_ENABLE)
584 writel( VAL2|JUMBO, mmio + CMD3);
585#if AMD8111E_VLAN_TAG_USED
586 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
587#endif
588
589 writel(CTRL1_DEFAULT, mmio + CTRL1);
590
591
592 readl(mmio + CMD2);
593
594}
595
596
597
598
599static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
600{
601 u32 intr0;
602
603
604 writel(INTREN, lp->mmio + CMD0);
605
606
607 intr0 = readl(lp->mmio + INT0);
608 writel(intr0, lp->mmio + INT0);
609
610
611 readl(lp->mmio + INT0);
612
613}
614
615
616static void amd8111e_stop_chip(struct amd8111e_priv *lp)
617{
618 writel(RUN, lp->mmio + CMD0);
619
620
621 readl(lp->mmio + CMD0);
622}
623
624
625static void amd8111e_free_ring(struct amd8111e_priv *lp)
626{
627
628 if(lp->rx_ring){
629 pci_free_consistent(lp->pci_dev,
630 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
631 lp->rx_ring, lp->rx_ring_dma_addr);
632 lp->rx_ring = NULL;
633 }
634
635 if(lp->tx_ring){
636 pci_free_consistent(lp->pci_dev,
637 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
638 lp->tx_ring, lp->tx_ring_dma_addr);
639
640 lp->tx_ring = NULL;
641 }
642
643}
644
645
646
647
648
649static int amd8111e_tx(struct net_device *dev)
650{
651 struct amd8111e_priv *lp = netdev_priv(dev);
652 int tx_index;
653 int status;
654
655 while (lp->tx_complete_idx != lp->tx_idx){
656 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
657 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
658
659 if(status & OWN_BIT)
660 break;
661
662 lp->tx_ring[tx_index].buff_phy_addr = 0;
663
664
665 if (lp->tx_skbuff[tx_index]) {
666 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
667 lp->tx_skbuff[tx_index]->len,
668 PCI_DMA_TODEVICE);
669 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
670 lp->tx_skbuff[tx_index] = NULL;
671 lp->tx_dma_addr[tx_index] = 0;
672 }
673 lp->tx_complete_idx++;
674
675 lp->coal_conf.tx_packets++;
676 lp->coal_conf.tx_bytes +=
677 le16_to_cpu(lp->tx_ring[tx_index].buff_count);
678
679 if (netif_queue_stopped(dev) &&
680 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
681
682
683 netif_wake_queue (dev);
684 }
685 }
686 return 0;
687}
688
689
690static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
691{
692 struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
693 struct net_device *dev = lp->amd8111e_net_dev;
694 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
695 void __iomem *mmio = lp->mmio;
696 struct sk_buff *skb,*new_skb;
697 int min_pkt_len, status;
698 int num_rx_pkt = 0;
699 short pkt_len;
700#if AMD8111E_VLAN_TAG_USED
701 short vtag;
702#endif
703
704 while (num_rx_pkt < budget) {
705 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
706 if (status & OWN_BIT)
707 break;
708
709
710
711
712
713
714
715 if (status & ERR_BIT) {
716
717 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
718 goto err_next_pkt;
719 }
720
721 if (!((status & STP_BIT) && (status & ENP_BIT))){
722
723 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
724 goto err_next_pkt;
725 }
726 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
727
728#if AMD8111E_VLAN_TAG_USED
729 vtag = status & TT_MASK;
730
731 if (vtag != 0)
732 min_pkt_len = MIN_PKT_LEN - 4;
733 else
734#endif
735 min_pkt_len = MIN_PKT_LEN;
736
737 if (pkt_len < min_pkt_len) {
738 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
739 lp->drv_rx_errors++;
740 goto err_next_pkt;
741 }
742 new_skb = netdev_alloc_skb(dev, lp->rx_buff_len);
743 if (!new_skb) {
744
745
746
747 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
748 lp->drv_rx_errors++;
749 goto err_next_pkt;
750 }
751
752 skb_reserve(new_skb, 2);
753 skb = lp->rx_skbuff[rx_index];
754 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
755 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
756 skb_put(skb, pkt_len);
757 lp->rx_skbuff[rx_index] = new_skb;
758 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
759 new_skb->data,
760 lp->rx_buff_len-2,
761 PCI_DMA_FROMDEVICE);
762
763 skb->protocol = eth_type_trans(skb, dev);
764
765#if AMD8111E_VLAN_TAG_USED
766 if (vtag == TT_VLAN_TAGGED){
767 u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info);
768 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
769 }
770#endif
771 napi_gro_receive(napi, skb);
772
773 lp->coal_conf.rx_packets++;
774 lp->coal_conf.rx_bytes += pkt_len;
775 num_rx_pkt++;
776
777err_next_pkt:
778 lp->rx_ring[rx_index].buff_phy_addr
779 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
780 lp->rx_ring[rx_index].buff_count =
781 cpu_to_le16(lp->rx_buff_len-2);
782 wmb();
783 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
784 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
785 }
786
787 if (num_rx_pkt < budget && napi_complete_done(napi, num_rx_pkt)) {
788 unsigned long flags;
789
790
791 spin_lock_irqsave(&lp->lock, flags);
792 writel(VAL0|RINTEN0, mmio + INTEN0);
793 writel(VAL2 | RDMD0, mmio + CMD0);
794 spin_unlock_irqrestore(&lp->lock, flags);
795 }
796
797 return num_rx_pkt;
798}
799
800
801static int amd8111e_link_change(struct net_device *dev)
802{
803 struct amd8111e_priv *lp = netdev_priv(dev);
804 int status0,speed;
805
806
807 status0 = readl(lp->mmio + STAT0);
808
809 if(status0 & LINK_STATS){
810 if(status0 & AUTONEG_COMPLETE)
811 lp->link_config.autoneg = AUTONEG_ENABLE;
812 else
813 lp->link_config.autoneg = AUTONEG_DISABLE;
814
815 if(status0 & FULL_DPLX)
816 lp->link_config.duplex = DUPLEX_FULL;
817 else
818 lp->link_config.duplex = DUPLEX_HALF;
819 speed = (status0 & SPEED_MASK) >> 7;
820 if(speed == PHY_SPEED_10)
821 lp->link_config.speed = SPEED_10;
822 else if(speed == PHY_SPEED_100)
823 lp->link_config.speed = SPEED_100;
824
825 netdev_info(dev, "Link is Up. Speed is %s Mbps %s Duplex\n",
826 (lp->link_config.speed == SPEED_100) ?
827 "100" : "10",
828 (lp->link_config.duplex == DUPLEX_FULL) ?
829 "Full" : "Half");
830
831 netif_carrier_on(dev);
832 }
833 else{
834 lp->link_config.speed = SPEED_INVALID;
835 lp->link_config.duplex = DUPLEX_INVALID;
836 lp->link_config.autoneg = AUTONEG_INVALID;
837 netdev_info(dev, "Link is Down.\n");
838 netif_carrier_off(dev);
839 }
840
841 return 0;
842}
843
844
845static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
846{
847 unsigned int status;
848 unsigned int data;
849 unsigned int repeat = REPEAT_CNT;
850
851 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
852 do {
853 status = readw(mmio + MIB_ADDR);
854 udelay(2);
855 }
856 while (--repeat && (status & MIB_CMD_ACTIVE));
857
858 data = readl(mmio + MIB_DATA);
859 return data;
860}
861
862
863
864
865static struct net_device_stats *amd8111e_get_stats(struct net_device *dev)
866{
867 struct amd8111e_priv *lp = netdev_priv(dev);
868 void __iomem *mmio = lp->mmio;
869 unsigned long flags;
870 struct net_device_stats *new_stats = &dev->stats;
871
872 if (!lp->opened)
873 return new_stats;
874 spin_lock_irqsave (&lp->lock, flags);
875
876
877 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
878 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
879 amd8111e_read_mib(mmio, rcv_unicast_pkts);
880
881
882 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
883
884
885 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
886
887
888 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
889
890
891
892 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
893 amd8111e_read_mib(mmio, rcv_fragments)+
894 amd8111e_read_mib(mmio, rcv_jabbers)+
895 amd8111e_read_mib(mmio, rcv_alignment_errors)+
896 amd8111e_read_mib(mmio, rcv_fcs_errors)+
897 amd8111e_read_mib(mmio, rcv_miss_pkts)+
898 lp->drv_rx_errors;
899
900
901 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
902
903
904 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
905
906
907 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
908
909
910 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
911
912
913 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
914
915
916 new_stats->rx_length_errors =
917 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
918 amd8111e_read_mib(mmio, rcv_oversize_pkts);
919
920
921 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
922
923
924 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
925
926
927 new_stats->rx_frame_errors =
928 amd8111e_read_mib(mmio, rcv_alignment_errors);
929
930
931 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
932
933
934 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
935
936
937 new_stats->tx_aborted_errors =
938 amd8111e_read_mib(mmio, xmt_excessive_collision);
939
940
941 new_stats->tx_carrier_errors =
942 amd8111e_read_mib(mmio, xmt_loss_carrier);
943
944
945 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
946
947
948 new_stats->tx_window_errors =
949 amd8111e_read_mib(mmio, xmt_late_collision);
950
951
952
953
954 spin_unlock_irqrestore (&lp->lock, flags);
955
956 return new_stats;
957}
958
959
960
961
962static int amd8111e_calc_coalesce(struct net_device *dev)
963{
964 struct amd8111e_priv *lp = netdev_priv(dev);
965 struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
966 int tx_pkt_rate;
967 int rx_pkt_rate;
968 int tx_data_rate;
969 int rx_data_rate;
970 int rx_pkt_size;
971 int tx_pkt_size;
972
973 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
974 coal_conf->tx_prev_packets = coal_conf->tx_packets;
975
976 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
977 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
978
979 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
980 coal_conf->rx_prev_packets = coal_conf->rx_packets;
981
982 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
983 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
984
985 if(rx_pkt_rate < 800){
986 if(coal_conf->rx_coal_type != NO_COALESCE){
987
988 coal_conf->rx_timeout = 0x0;
989 coal_conf->rx_event_count = 0;
990 amd8111e_set_coalesce(dev,RX_INTR_COAL);
991 coal_conf->rx_coal_type = NO_COALESCE;
992 }
993 }
994 else{
995
996 rx_pkt_size = rx_data_rate/rx_pkt_rate;
997 if (rx_pkt_size < 128){
998 if(coal_conf->rx_coal_type != NO_COALESCE){
999
1000 coal_conf->rx_timeout = 0;
1001 coal_conf->rx_event_count = 0;
1002 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1003 coal_conf->rx_coal_type = NO_COALESCE;
1004 }
1005
1006 }
1007 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1008
1009 if(coal_conf->rx_coal_type != LOW_COALESCE){
1010 coal_conf->rx_timeout = 1;
1011 coal_conf->rx_event_count = 4;
1012 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1013 coal_conf->rx_coal_type = LOW_COALESCE;
1014 }
1015 }
1016 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1017
1018 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1019 coal_conf->rx_timeout = 1;
1020 coal_conf->rx_event_count = 4;
1021 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1022 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1023 }
1024
1025 }
1026 else if(rx_pkt_size >= 1024){
1027 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1028 coal_conf->rx_timeout = 2;
1029 coal_conf->rx_event_count = 3;
1030 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1031 coal_conf->rx_coal_type = HIGH_COALESCE;
1032 }
1033 }
1034 }
1035
1036 if(tx_pkt_rate < 800){
1037 if(coal_conf->tx_coal_type != NO_COALESCE){
1038
1039 coal_conf->tx_timeout = 0x0;
1040 coal_conf->tx_event_count = 0;
1041 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1042 coal_conf->tx_coal_type = NO_COALESCE;
1043 }
1044 }
1045 else{
1046
1047 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1048 if (tx_pkt_size < 128){
1049
1050 if(coal_conf->tx_coal_type != NO_COALESCE){
1051
1052 coal_conf->tx_timeout = 0;
1053 coal_conf->tx_event_count = 0;
1054 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1055 coal_conf->tx_coal_type = NO_COALESCE;
1056 }
1057
1058 }
1059 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1060
1061 if(coal_conf->tx_coal_type != LOW_COALESCE){
1062 coal_conf->tx_timeout = 1;
1063 coal_conf->tx_event_count = 2;
1064 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1065 coal_conf->tx_coal_type = LOW_COALESCE;
1066
1067 }
1068 }
1069 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1070
1071 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1072 coal_conf->tx_timeout = 2;
1073 coal_conf->tx_event_count = 5;
1074 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1075 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1076 }
1077 } else if (tx_pkt_size >= 1024) {
1078 if (coal_conf->tx_coal_type != HIGH_COALESCE) {
1079 coal_conf->tx_timeout = 4;
1080 coal_conf->tx_event_count = 8;
1081 amd8111e_set_coalesce(dev, TX_INTR_COAL);
1082 coal_conf->tx_coal_type = HIGH_COALESCE;
1083 }
1084 }
1085 }
1086 return 0;
1087
1088}
1089
1090
1091
1092
1093static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1094{
1095
1096 struct net_device *dev = (struct net_device *)dev_id;
1097 struct amd8111e_priv *lp = netdev_priv(dev);
1098 void __iomem *mmio = lp->mmio;
1099 unsigned int intr0, intren0;
1100 unsigned int handled = 1;
1101
1102 if(unlikely(dev == NULL))
1103 return IRQ_NONE;
1104
1105 spin_lock(&lp->lock);
1106
1107
1108 writel(INTREN, mmio + CMD0);
1109
1110
1111 intr0 = readl(mmio + INT0);
1112 intren0 = readl(mmio + INTEN0);
1113
1114
1115
1116 if (!(intr0 & INTR)){
1117 handled = 0;
1118 goto err_no_interrupt;
1119 }
1120
1121
1122 writel(intr0, mmio + INT0);
1123
1124
1125 if (intr0 & RINT0) {
1126 if (napi_schedule_prep(&lp->napi)) {
1127
1128 writel(RINTEN0, mmio + INTEN0);
1129
1130 __napi_schedule(&lp->napi);
1131 } else if (intren0 & RINTEN0) {
1132 netdev_dbg(dev, "************Driver bug! interrupt while in poll\n");
1133
1134 writel(RINTEN0, mmio + INTEN0);
1135 }
1136 }
1137
1138
1139 if (intr0 & TINT0)
1140 amd8111e_tx(dev);
1141
1142
1143 if (intr0 & LCINT)
1144 amd8111e_link_change(dev);
1145
1146
1147 if (intr0 & STINT)
1148 amd8111e_calc_coalesce(dev);
1149
1150err_no_interrupt:
1151 writel( VAL0 | INTREN,mmio + CMD0);
1152
1153 spin_unlock(&lp->lock);
1154
1155 return IRQ_RETVAL(handled);
1156}
1157
1158#ifdef CONFIG_NET_POLL_CONTROLLER
1159static void amd8111e_poll(struct net_device *dev)
1160{
1161 unsigned long flags;
1162 local_irq_save(flags);
1163 amd8111e_interrupt(0, dev);
1164 local_irq_restore(flags);
1165}
1166#endif
1167
1168
1169
1170
1171
1172
1173static int amd8111e_close(struct net_device *dev)
1174{
1175 struct amd8111e_priv *lp = netdev_priv(dev);
1176 netif_stop_queue(dev);
1177
1178 napi_disable(&lp->napi);
1179
1180 spin_lock_irq(&lp->lock);
1181
1182 amd8111e_disable_interrupt(lp);
1183 amd8111e_stop_chip(lp);
1184
1185
1186 amd8111e_free_skbs(lp->amd8111e_net_dev);
1187
1188 netif_carrier_off(lp->amd8111e_net_dev);
1189
1190
1191 if(lp->options & OPTION_DYN_IPG_ENABLE)
1192 del_timer_sync(&lp->ipg_data.ipg_timer);
1193
1194 spin_unlock_irq(&lp->lock);
1195 free_irq(dev->irq, dev);
1196 amd8111e_free_ring(lp);
1197
1198
1199 amd8111e_get_stats(dev);
1200 lp->opened = 0;
1201 return 0;
1202}
1203
1204
1205
1206
1207static int amd8111e_open(struct net_device *dev)
1208{
1209 struct amd8111e_priv *lp = netdev_priv(dev);
1210
1211 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
1212 dev->name, dev))
1213 return -EAGAIN;
1214
1215 napi_enable(&lp->napi);
1216
1217 spin_lock_irq(&lp->lock);
1218
1219 amd8111e_init_hw_default(lp);
1220
1221 if(amd8111e_restart(dev)){
1222 spin_unlock_irq(&lp->lock);
1223 napi_disable(&lp->napi);
1224 if (dev->irq)
1225 free_irq(dev->irq, dev);
1226 return -ENOMEM;
1227 }
1228
1229 if(lp->options & OPTION_DYN_IPG_ENABLE){
1230 add_timer(&lp->ipg_data.ipg_timer);
1231 netdev_info(dev, "Dynamic IPG Enabled\n");
1232 }
1233
1234 lp->opened = 1;
1235
1236 spin_unlock_irq(&lp->lock);
1237
1238 netif_start_queue(dev);
1239
1240 return 0;
1241}
1242
1243
1244
1245
1246static int amd8111e_tx_queue_avail(struct amd8111e_priv *lp)
1247{
1248 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1249 if (lp->tx_skbuff[tx_index])
1250 return -1;
1251 else
1252 return 0;
1253
1254}
1255
1256
1257
1258
1259
1260
1261static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb,
1262 struct net_device *dev)
1263{
1264 struct amd8111e_priv *lp = netdev_priv(dev);
1265 int tx_index;
1266 unsigned long flags;
1267
1268 spin_lock_irqsave(&lp->lock, flags);
1269
1270 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1271
1272 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1273
1274 lp->tx_skbuff[tx_index] = skb;
1275 lp->tx_ring[tx_index].tx_flags = 0;
1276
1277#if AMD8111E_VLAN_TAG_USED
1278 if (skb_vlan_tag_present(skb)) {
1279 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1280 cpu_to_le16(TCC_VLAN_INSERT);
1281 lp->tx_ring[tx_index].tag_ctrl_info =
1282 cpu_to_le16(skb_vlan_tag_get(skb));
1283
1284 }
1285#endif
1286 lp->tx_dma_addr[tx_index] =
1287 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1288 lp->tx_ring[tx_index].buff_phy_addr =
1289 cpu_to_le32(lp->tx_dma_addr[tx_index]);
1290
1291
1292 wmb();
1293 lp->tx_ring[tx_index].tx_flags |=
1294 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1295
1296 lp->tx_idx++;
1297
1298
1299 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1300 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1301
1302 if(amd8111e_tx_queue_avail(lp) < 0){
1303 netif_stop_queue(dev);
1304 }
1305 spin_unlock_irqrestore(&lp->lock, flags);
1306 return NETDEV_TX_OK;
1307}
1308
1309static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1310{
1311 void __iomem *mmio = lp->mmio;
1312
1313 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1314 buf[1] = readl(mmio + XMT_RING_LEN0);
1315 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1316 buf[3] = readl(mmio + RCV_RING_LEN0);
1317 buf[4] = readl(mmio + CMD0);
1318 buf[5] = readl(mmio + CMD2);
1319 buf[6] = readl(mmio + CMD3);
1320 buf[7] = readl(mmio + CMD7);
1321 buf[8] = readl(mmio + INT0);
1322 buf[9] = readl(mmio + INTEN0);
1323 buf[10] = readl(mmio + LADRF);
1324 buf[11] = readl(mmio + LADRF+4);
1325 buf[12] = readl(mmio + STAT0);
1326}
1327
1328
1329
1330
1331
1332static void amd8111e_set_multicast_list(struct net_device *dev)
1333{
1334 struct netdev_hw_addr *ha;
1335 struct amd8111e_priv *lp = netdev_priv(dev);
1336 u32 mc_filter[2] ;
1337 int bit_num;
1338
1339 if(dev->flags & IFF_PROMISC){
1340 writel( VAL2 | PROM, lp->mmio + CMD2);
1341 return;
1342 }
1343 else
1344 writel( PROM, lp->mmio + CMD2);
1345 if (dev->flags & IFF_ALLMULTI ||
1346 netdev_mc_count(dev) > MAX_FILTER_SIZE) {
1347
1348 mc_filter[1] = mc_filter[0] = 0xffffffff;
1349 lp->options |= OPTION_MULTICAST_ENABLE;
1350 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1351 return;
1352 }
1353 if (netdev_mc_empty(dev)) {
1354
1355 mc_filter[1] = mc_filter[0] = 0;
1356 lp->options &= ~OPTION_MULTICAST_ENABLE;
1357 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1358
1359 writel(PROM, lp->mmio + CMD2);
1360 return;
1361 }
1362
1363 lp->options |= OPTION_MULTICAST_ENABLE;
1364 mc_filter[1] = mc_filter[0] = 0;
1365 netdev_for_each_mc_addr(ha, dev) {
1366 bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f;
1367 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1368 }
1369 amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1370
1371
1372 readl(lp->mmio + CMD2);
1373
1374}
1375
1376static void amd8111e_get_drvinfo(struct net_device *dev,
1377 struct ethtool_drvinfo *info)
1378{
1379 struct amd8111e_priv *lp = netdev_priv(dev);
1380 struct pci_dev *pci_dev = lp->pci_dev;
1381 strlcpy(info->driver, MODULE_NAME, sizeof(info->driver));
1382 strlcpy(info->version, MODULE_VERS, sizeof(info->version));
1383 snprintf(info->fw_version, sizeof(info->fw_version),
1384 "%u", chip_version);
1385 strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info));
1386}
1387
1388static int amd8111e_get_regs_len(struct net_device *dev)
1389{
1390 return AMD8111E_REG_DUMP_LEN;
1391}
1392
1393static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1394{
1395 struct amd8111e_priv *lp = netdev_priv(dev);
1396 regs->version = 0;
1397 amd8111e_read_regs(lp, buf);
1398}
1399
1400static int amd8111e_get_link_ksettings(struct net_device *dev,
1401 struct ethtool_link_ksettings *cmd)
1402{
1403 struct amd8111e_priv *lp = netdev_priv(dev);
1404 spin_lock_irq(&lp->lock);
1405 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
1406 spin_unlock_irq(&lp->lock);
1407 return 0;
1408}
1409
1410static int amd8111e_set_link_ksettings(struct net_device *dev,
1411 const struct ethtool_link_ksettings *cmd)
1412{
1413 struct amd8111e_priv *lp = netdev_priv(dev);
1414 int res;
1415 spin_lock_irq(&lp->lock);
1416 res = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
1417 spin_unlock_irq(&lp->lock);
1418 return res;
1419}
1420
1421static int amd8111e_nway_reset(struct net_device *dev)
1422{
1423 struct amd8111e_priv *lp = netdev_priv(dev);
1424 return mii_nway_restart(&lp->mii_if);
1425}
1426
1427static u32 amd8111e_get_link(struct net_device *dev)
1428{
1429 struct amd8111e_priv *lp = netdev_priv(dev);
1430 return mii_link_ok(&lp->mii_if);
1431}
1432
1433static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1434{
1435 struct amd8111e_priv *lp = netdev_priv(dev);
1436 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1437 if (lp->options & OPTION_WOL_ENABLE)
1438 wol_info->wolopts = WAKE_MAGIC;
1439}
1440
1441static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1442{
1443 struct amd8111e_priv *lp = netdev_priv(dev);
1444 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1445 return -EINVAL;
1446 spin_lock_irq(&lp->lock);
1447 if (wol_info->wolopts & WAKE_MAGIC)
1448 lp->options |=
1449 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1450 else if(wol_info->wolopts & WAKE_PHY)
1451 lp->options |=
1452 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1453 else
1454 lp->options &= ~OPTION_WOL_ENABLE;
1455 spin_unlock_irq(&lp->lock);
1456 return 0;
1457}
1458
1459static const struct ethtool_ops ops = {
1460 .get_drvinfo = amd8111e_get_drvinfo,
1461 .get_regs_len = amd8111e_get_regs_len,
1462 .get_regs = amd8111e_get_regs,
1463 .nway_reset = amd8111e_nway_reset,
1464 .get_link = amd8111e_get_link,
1465 .get_wol = amd8111e_get_wol,
1466 .set_wol = amd8111e_set_wol,
1467 .get_link_ksettings = amd8111e_get_link_ksettings,
1468 .set_link_ksettings = amd8111e_set_link_ksettings,
1469};
1470
1471
1472
1473
1474
1475static int amd8111e_ioctl(struct net_device *dev , struct ifreq *ifr, int cmd)
1476{
1477 struct mii_ioctl_data *data = if_mii(ifr);
1478 struct amd8111e_priv *lp = netdev_priv(dev);
1479 int err;
1480 u32 mii_regval;
1481
1482 switch(cmd) {
1483 case SIOCGMIIPHY:
1484 data->phy_id = lp->ext_phy_addr;
1485
1486
1487 case SIOCGMIIREG:
1488
1489 spin_lock_irq(&lp->lock);
1490 err = amd8111e_read_phy(lp, data->phy_id,
1491 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1492 spin_unlock_irq(&lp->lock);
1493
1494 data->val_out = mii_regval;
1495 return err;
1496
1497 case SIOCSMIIREG:
1498
1499 spin_lock_irq(&lp->lock);
1500 err = amd8111e_write_phy(lp, data->phy_id,
1501 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1502 spin_unlock_irq(&lp->lock);
1503
1504 return err;
1505
1506 default:
1507
1508 break;
1509 }
1510 return -EOPNOTSUPP;
1511}
1512static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1513{
1514 struct amd8111e_priv *lp = netdev_priv(dev);
1515 int i;
1516 struct sockaddr *addr = p;
1517
1518 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1519 spin_lock_irq(&lp->lock);
1520
1521 for (i = 0; i < ETH_ALEN; i++)
1522 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1523
1524 spin_unlock_irq(&lp->lock);
1525
1526 return 0;
1527}
1528
1529
1530
1531
1532static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1533{
1534 struct amd8111e_priv *lp = netdev_priv(dev);
1535 int err;
1536
1537 if (!netif_running(dev)) {
1538
1539
1540
1541 dev->mtu = new_mtu;
1542 return 0;
1543 }
1544
1545 spin_lock_irq(&lp->lock);
1546
1547
1548 writel(RUN, lp->mmio + CMD0);
1549
1550 dev->mtu = new_mtu;
1551
1552 err = amd8111e_restart(dev);
1553 spin_unlock_irq(&lp->lock);
1554 if(!err)
1555 netif_start_queue(dev);
1556 return err;
1557}
1558
1559static int amd8111e_enable_magicpkt(struct amd8111e_priv *lp)
1560{
1561 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1562 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1563
1564
1565 readl(lp->mmio + CMD7);
1566 return 0;
1567}
1568
1569static int amd8111e_enable_link_change(struct amd8111e_priv *lp)
1570{
1571
1572
1573 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1574
1575
1576 readl(lp->mmio + CMD7);
1577 return 0;
1578}
1579
1580
1581
1582
1583
1584
1585static void amd8111e_tx_timeout(struct net_device *dev)
1586{
1587 struct amd8111e_priv *lp = netdev_priv(dev);
1588 int err;
1589
1590 netdev_err(dev, "transmit timed out, resetting\n");
1591
1592 spin_lock_irq(&lp->lock);
1593 err = amd8111e_restart(dev);
1594 spin_unlock_irq(&lp->lock);
1595 if(!err)
1596 netif_wake_queue(dev);
1597}
1598static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1599{
1600 struct net_device *dev = pci_get_drvdata(pci_dev);
1601 struct amd8111e_priv *lp = netdev_priv(dev);
1602
1603 if (!netif_running(dev))
1604 return 0;
1605
1606
1607 spin_lock_irq(&lp->lock);
1608 amd8111e_disable_interrupt(lp);
1609 spin_unlock_irq(&lp->lock);
1610
1611 netif_device_detach(dev);
1612
1613
1614 spin_lock_irq(&lp->lock);
1615 if(lp->options & OPTION_DYN_IPG_ENABLE)
1616 del_timer_sync(&lp->ipg_data.ipg_timer);
1617 amd8111e_stop_chip(lp);
1618 spin_unlock_irq(&lp->lock);
1619
1620 if(lp->options & OPTION_WOL_ENABLE){
1621
1622 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1623 amd8111e_enable_magicpkt(lp);
1624 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1625 amd8111e_enable_link_change(lp);
1626
1627 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1628 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1629
1630 }
1631 else{
1632 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1633 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1634 }
1635
1636 pci_save_state(pci_dev);
1637 pci_set_power_state(pci_dev, PCI_D3hot);
1638
1639 return 0;
1640}
1641static int amd8111e_resume(struct pci_dev *pci_dev)
1642{
1643 struct net_device *dev = pci_get_drvdata(pci_dev);
1644 struct amd8111e_priv *lp = netdev_priv(dev);
1645
1646 if (!netif_running(dev))
1647 return 0;
1648
1649 pci_set_power_state(pci_dev, PCI_D0);
1650 pci_restore_state(pci_dev);
1651
1652 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1653 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1654
1655 netif_device_attach(dev);
1656
1657 spin_lock_irq(&lp->lock);
1658 amd8111e_restart(dev);
1659
1660 if(lp->options & OPTION_DYN_IPG_ENABLE)
1661 mod_timer(&lp->ipg_data.ipg_timer,
1662 jiffies + IPG_CONVERGE_JIFFIES);
1663 spin_unlock_irq(&lp->lock);
1664
1665 return 0;
1666}
1667
1668static void amd8111e_config_ipg(struct timer_list *t)
1669{
1670 struct amd8111e_priv *lp = from_timer(lp, t, ipg_data.ipg_timer);
1671 struct ipg_info *ipg_data = &lp->ipg_data;
1672 void __iomem *mmio = lp->mmio;
1673 unsigned int prev_col_cnt = ipg_data->col_cnt;
1674 unsigned int total_col_cnt;
1675 unsigned int tmp_ipg;
1676
1677 if(lp->link_config.duplex == DUPLEX_FULL){
1678 ipg_data->ipg = DEFAULT_IPG;
1679 return;
1680 }
1681
1682 if(ipg_data->ipg_state == SSTATE){
1683
1684 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1685
1686 ipg_data->timer_tick = 0;
1687 ipg_data->ipg = MIN_IPG - IPG_STEP;
1688 ipg_data->current_ipg = MIN_IPG;
1689 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1690 ipg_data->ipg_state = CSTATE;
1691 }
1692 else
1693 ipg_data->timer_tick++;
1694 }
1695
1696 if(ipg_data->ipg_state == CSTATE){
1697
1698
1699
1700 total_col_cnt = ipg_data->col_cnt =
1701 amd8111e_read_mib(mmio, xmt_collisions);
1702
1703 if ((total_col_cnt - prev_col_cnt) <
1704 (ipg_data->diff_col_cnt)){
1705
1706 ipg_data->diff_col_cnt =
1707 total_col_cnt - prev_col_cnt ;
1708
1709 ipg_data->ipg = ipg_data->current_ipg;
1710 }
1711
1712 ipg_data->current_ipg += IPG_STEP;
1713
1714 if (ipg_data->current_ipg <= MAX_IPG)
1715 tmp_ipg = ipg_data->current_ipg;
1716 else{
1717 tmp_ipg = ipg_data->ipg;
1718 ipg_data->ipg_state = SSTATE;
1719 }
1720 writew((u32)tmp_ipg, mmio + IPG);
1721 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1722 }
1723 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1724 return;
1725
1726}
1727
1728static void amd8111e_probe_ext_phy(struct net_device *dev)
1729{
1730 struct amd8111e_priv *lp = netdev_priv(dev);
1731 int i;
1732
1733 for (i = 0x1e; i >= 0; i--) {
1734 u32 id1, id2;
1735
1736 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1737 continue;
1738 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1739 continue;
1740 lp->ext_phy_id = (id1 << 16) | id2;
1741 lp->ext_phy_addr = i;
1742 return;
1743 }
1744 lp->ext_phy_id = 0;
1745 lp->ext_phy_addr = 1;
1746}
1747
1748static const struct net_device_ops amd8111e_netdev_ops = {
1749 .ndo_open = amd8111e_open,
1750 .ndo_stop = amd8111e_close,
1751 .ndo_start_xmit = amd8111e_start_xmit,
1752 .ndo_tx_timeout = amd8111e_tx_timeout,
1753 .ndo_get_stats = amd8111e_get_stats,
1754 .ndo_set_rx_mode = amd8111e_set_multicast_list,
1755 .ndo_validate_addr = eth_validate_addr,
1756 .ndo_set_mac_address = amd8111e_set_mac_address,
1757 .ndo_do_ioctl = amd8111e_ioctl,
1758 .ndo_change_mtu = amd8111e_change_mtu,
1759#ifdef CONFIG_NET_POLL_CONTROLLER
1760 .ndo_poll_controller = amd8111e_poll,
1761#endif
1762};
1763
1764static int amd8111e_probe_one(struct pci_dev *pdev,
1765 const struct pci_device_id *ent)
1766{
1767 int err, i;
1768 unsigned long reg_addr,reg_len;
1769 struct amd8111e_priv *lp;
1770 struct net_device *dev;
1771
1772 err = pci_enable_device(pdev);
1773 if(err){
1774 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
1775 return err;
1776 }
1777
1778 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1779 dev_err(&pdev->dev, "Cannot find PCI base address\n");
1780 err = -ENODEV;
1781 goto err_disable_pdev;
1782 }
1783
1784 err = pci_request_regions(pdev, MODULE_NAME);
1785 if(err){
1786 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
1787 goto err_disable_pdev;
1788 }
1789
1790 pci_set_master(pdev);
1791
1792
1793 if (!pdev->pm_cap) {
1794 dev_err(&pdev->dev, "No Power Management capability\n");
1795 err = -ENODEV;
1796 goto err_free_reg;
1797 }
1798
1799
1800 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) {
1801 dev_err(&pdev->dev, "DMA not supported\n");
1802 err = -ENODEV;
1803 goto err_free_reg;
1804 }
1805
1806 reg_addr = pci_resource_start(pdev, 0);
1807 reg_len = pci_resource_len(pdev, 0);
1808
1809 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1810 if (!dev) {
1811 err = -ENOMEM;
1812 goto err_free_reg;
1813 }
1814
1815 SET_NETDEV_DEV(dev, &pdev->dev);
1816
1817#if AMD8111E_VLAN_TAG_USED
1818 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX ;
1819#endif
1820
1821 lp = netdev_priv(dev);
1822 lp->pci_dev = pdev;
1823 lp->amd8111e_net_dev = dev;
1824 lp->pm_cap = pdev->pm_cap;
1825
1826 spin_lock_init(&lp->lock);
1827
1828 lp->mmio = devm_ioremap(&pdev->dev, reg_addr, reg_len);
1829 if (!lp->mmio) {
1830 dev_err(&pdev->dev, "Cannot map device registers\n");
1831 err = -ENOMEM;
1832 goto err_free_dev;
1833 }
1834
1835
1836 for (i = 0; i < ETH_ALEN; i++)
1837 dev->dev_addr[i] = readb(lp->mmio + PADR + i);
1838
1839
1840 lp->ext_phy_option = speed_duplex[card_idx];
1841 if(coalesce[card_idx])
1842 lp->options |= OPTION_INTR_COAL_ENABLE;
1843 if(dynamic_ipg[card_idx++])
1844 lp->options |= OPTION_DYN_IPG_ENABLE;
1845
1846
1847
1848 dev->netdev_ops = &amd8111e_netdev_ops;
1849 dev->ethtool_ops = &ops;
1850 dev->irq =pdev->irq;
1851 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1852 dev->min_mtu = AMD8111E_MIN_MTU;
1853 dev->max_mtu = AMD8111E_MAX_MTU;
1854 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1855
1856#if AMD8111E_VLAN_TAG_USED
1857 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1858#endif
1859
1860 amd8111e_probe_ext_phy(dev);
1861
1862
1863 lp->mii_if.dev = dev;
1864 lp->mii_if.mdio_read = amd8111e_mdio_read;
1865 lp->mii_if.mdio_write = amd8111e_mdio_write;
1866 lp->mii_if.phy_id = lp->ext_phy_addr;
1867
1868
1869 amd8111e_set_rx_buff_len(dev);
1870
1871
1872 err = register_netdev(dev);
1873 if (err) {
1874 dev_err(&pdev->dev, "Cannot register net device\n");
1875 goto err_free_dev;
1876 }
1877
1878 pci_set_drvdata(pdev, dev);
1879
1880
1881 if(lp->options & OPTION_DYN_IPG_ENABLE){
1882 timer_setup(&lp->ipg_data.ipg_timer, amd8111e_config_ipg, 0);
1883 lp->ipg_data.ipg_timer.expires = jiffies +
1884 IPG_CONVERGE_JIFFIES;
1885 lp->ipg_data.ipg = DEFAULT_IPG;
1886 lp->ipg_data.ipg_state = CSTATE;
1887 }
1888
1889
1890 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
1891 dev_info(&pdev->dev, "AMD-8111e Driver Version: %s\n", MODULE_VERS);
1892 dev_info(&pdev->dev, "[ Rev %x ] PCI 10/100BaseT Ethernet %pM\n",
1893 chip_version, dev->dev_addr);
1894 if (lp->ext_phy_id)
1895 dev_info(&pdev->dev, "Found MII PHY ID 0x%08x at address 0x%02x\n",
1896 lp->ext_phy_id, lp->ext_phy_addr);
1897 else
1898 dev_info(&pdev->dev, "Couldn't detect MII PHY, assuming address 0x01\n");
1899
1900 return 0;
1901
1902err_free_dev:
1903 free_netdev(dev);
1904
1905err_free_reg:
1906 pci_release_regions(pdev);
1907
1908err_disable_pdev:
1909 pci_disable_device(pdev);
1910 return err;
1911
1912}
1913
1914static void amd8111e_remove_one(struct pci_dev *pdev)
1915{
1916 struct net_device *dev = pci_get_drvdata(pdev);
1917
1918 if (dev) {
1919 unregister_netdev(dev);
1920 free_netdev(dev);
1921 pci_release_regions(pdev);
1922 pci_disable_device(pdev);
1923 }
1924}
1925
1926static const struct pci_device_id amd8111e_pci_tbl[] = {
1927 {
1928 .vendor = PCI_VENDOR_ID_AMD,
1929 .device = PCI_DEVICE_ID_AMD8111E_7462,
1930 },
1931 {
1932 .vendor = 0,
1933 }
1934};
1935MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
1936
1937static struct pci_driver amd8111e_driver = {
1938 .name = MODULE_NAME,
1939 .id_table = amd8111e_pci_tbl,
1940 .probe = amd8111e_probe_one,
1941 .remove = amd8111e_remove_one,
1942 .suspend = amd8111e_suspend,
1943 .resume = amd8111e_resume
1944};
1945
1946module_pci_driver(amd8111e_driver);
1947