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20#ifndef __CXGB4_DCB_H
21#define __CXGB4_DCB_H
22
23#include <linux/netdevice.h>
24#include <linux/dcbnl.h>
25#include <net/dcbnl.h>
26
27#ifdef CONFIG_CHELSIO_T4_DCB
28
29#define CXGB4_DCBX_FW_SUPPORT \
30 (DCB_CAP_DCBX_VER_CEE | \
31 DCB_CAP_DCBX_VER_IEEE | \
32 DCB_CAP_DCBX_LLD_MANAGED)
33#define CXGB4_DCBX_HOST_SUPPORT \
34 (DCB_CAP_DCBX_VER_CEE | \
35 DCB_CAP_DCBX_VER_IEEE | \
36 DCB_CAP_DCBX_HOST)
37
38#define CXGB4_MAX_PRIORITY CXGB4_MAX_DCBX_APP_SUPPORTED
39#define CXGB4_MAX_TCS CXGB4_MAX_DCBX_APP_SUPPORTED
40
41#define INIT_PORT_DCB_CMD(__pcmd, __port, __op, __action) \
42 do { \
43 memset(&(__pcmd), 0, sizeof(__pcmd)); \
44 (__pcmd).op_to_portid = \
45 cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | \
46 FW_CMD_REQUEST_F | \
47 FW_CMD_##__op##_F | \
48 FW_PORT_CMD_PORTID_V(__port)); \
49 (__pcmd).action_to_len16 = \
50 cpu_to_be32(FW_PORT_CMD_ACTION_V(__action) | \
51 FW_LEN16(pcmd)); \
52 } while (0)
53
54#define INIT_PORT_DCB_READ_PEER_CMD(__pcmd, __port) \
55 INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_RECV)
56
57#define INIT_PORT_DCB_READ_LOCAL_CMD(__pcmd, __port) \
58 INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_TRANS)
59
60#define INIT_PORT_DCB_READ_SYNC_CMD(__pcmd, __port) \
61 INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_DET)
62
63#define INIT_PORT_DCB_WRITE_CMD(__pcmd, __port) \
64 INIT_PORT_DCB_CMD(__pcmd, __port, EXEC, FW_PORT_ACTION_L2_DCB_CFG)
65
66#define IEEE_FAUX_SYNC(__dev, __dcb) \
67 do { \
68 if ((__dcb)->dcb_version == FW_PORT_DCB_VER_IEEE) \
69 cxgb4_dcb_state_fsm((__dev), \
70 CXGB4_DCB_INPUT_FW_ALLSYNCED); \
71 } while (0)
72
73
74
75enum cxgb4_dcb_state {
76 CXGB4_DCB_STATE_START,
77 CXGB4_DCB_STATE_HOST,
78 CXGB4_DCB_STATE_FW_INCOMPLETE,
79 CXGB4_DCB_STATE_FW_ALLSYNCED,
80};
81
82
83
84enum cxgb4_dcb_state_input {
85
86
87 CXGB4_DCB_INPUT_FW_DISABLED,
88 CXGB4_DCB_INPUT_FW_ENABLED,
89 CXGB4_DCB_INPUT_FW_INCOMPLETE,
90 CXGB4_DCB_INPUT_FW_ALLSYNCED,
91
92};
93
94
95
96enum cxgb4_dcb_fw_msgs {
97 CXGB4_DCB_FW_PGID = 0x01,
98 CXGB4_DCB_FW_PGRATE = 0x02,
99 CXGB4_DCB_FW_PRIORATE = 0x04,
100 CXGB4_DCB_FW_PFC = 0x08,
101 CXGB4_DCB_FW_APP_ID = 0x10,
102};
103
104#define CXGB4_MAX_DCBX_APP_SUPPORTED 8
105
106
107
108struct port_dcb_info {
109 enum cxgb4_dcb_state state;
110 enum cxgb4_dcb_fw_msgs msgs;
111 unsigned int supported;
112 bool enabled;
113
114
115
116
117 u32 pgid;
118 u8 dcb_version;
119 u8 pfcen;
120 u8 pg_num_tcs_supported;
121 u8 pfc_num_tcs_supported;
122 u8 pgrate[8];
123 u8 priorate[8];
124 u8 tsa[8];
125 struct app_priority {
126 u8 user_prio_map;
127 u8 sel_field;
128 u16 protocolid;
129 } app_priority[CXGB4_MAX_DCBX_APP_SUPPORTED];
130};
131
132void cxgb4_dcb_state_init(struct net_device *);
133void cxgb4_dcb_version_init(struct net_device *);
134void cxgb4_dcb_reset(struct net_device *dev);
135void cxgb4_dcb_state_fsm(struct net_device *, enum cxgb4_dcb_state_input);
136void cxgb4_dcb_handle_fw_update(struct adapter *, const struct fw_port_cmd *);
137void cxgb4_dcb_set_caps(struct adapter *, const struct fw_port_cmd *);
138extern const struct dcbnl_rtnl_ops cxgb4_dcb_ops;
139
140static inline __u8 bitswap_1(unsigned char val)
141{
142 return ((val & 0x80) >> 7) |
143 ((val & 0x40) >> 5) |
144 ((val & 0x20) >> 3) |
145 ((val & 0x10) >> 1) |
146 ((val & 0x08) << 1) |
147 ((val & 0x04) << 3) |
148 ((val & 0x02) << 5) |
149 ((val & 0x01) << 7);
150}
151#define CXGB4_DCB_ENABLED true
152
153#else
154
155static inline void cxgb4_dcb_state_init(struct net_device *dev)
156{
157}
158
159#define CXGB4_DCB_ENABLED false
160
161#endif
162
163#endif
164