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24#ifndef __IBM_NEWEMAC_MAL_H
25#define __IBM_NEWEMAC_MAL_H
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41
42#define MAL_CFG 0x00
43#define MAL_CFG_SR 0x80000000
44#define MAL_CFG_PLBB 0x00004000
45#define MAL_CFG_OPBBL 0x00000080
46#define MAL_CFG_EOPIE 0x00000004
47#define MAL_CFG_LEA 0x00000002
48#define MAL_CFG_SD 0x00000001
49
50
51#define MAL1_CFG_PLBP_MASK 0x00c00000
52#define MAL1_CFG_PLBP_10 0x00800000
53#define MAL1_CFG_GA 0x00200000
54#define MAL1_CFG_OA 0x00100000
55#define MAL1_CFG_PLBLE 0x00080000
56#define MAL1_CFG_PLBT_MASK 0x00078000
57#define MAL1_CFG_DEFAULT (MAL1_CFG_PLBP_10 | MAL1_CFG_PLBT_MASK)
58
59
60#define MAL2_CFG_RPP_MASK 0x00c00000
61#define MAL2_CFG_RPP_10 0x00800000
62#define MAL2_CFG_RMBS_MASK 0x00300000
63#define MAL2_CFG_WPP_MASK 0x000c0000
64#define MAL2_CFG_WPP_10 0x00080000
65#define MAL2_CFG_WMBS_MASK 0x00030000
66#define MAL2_CFG_PLBLE 0x00008000
67#define MAL2_CFG_DEFAULT (MAL2_CFG_RMBS_MASK | MAL2_CFG_WMBS_MASK | \
68 MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10)
69
70#define MAL_ESR 0x01
71#define MAL_ESR_EVB 0x80000000
72#define MAL_ESR_CIDT 0x40000000
73#define MAL_ESR_CID_MASK 0x3e000000
74#define MAL_ESR_CID_SHIFT 25
75#define MAL_ESR_DE 0x00100000
76#define MAL_ESR_OTE 0x00040000
77#define MAL_ESR_OSE 0x00020000
78#define MAL_ESR_PEIN 0x00010000
79#define MAL_ESR_DEI 0x00000010
80#define MAL_ESR_OTEI 0x00000004
81#define MAL_ESR_OSEI 0x00000002
82#define MAL_ESR_PBEI 0x00000001
83
84
85#define MAL1_ESR_ONE 0x00080000
86#define MAL1_ESR_ONEI 0x00000008
87
88
89#define MAL2_ESR_PTE 0x00800000
90#define MAL2_ESR_PRE 0x00400000
91#define MAL2_ESR_PWE 0x00200000
92#define MAL2_ESR_PTEI 0x00000080
93#define MAL2_ESR_PREI 0x00000040
94#define MAL2_ESR_PWEI 0x00000020
95
96
97#define MAL_IER 0x02
98
99#define MAL_IER_DE 0x00000010
100#define MAL_IER_OTE 0x00000004
101#define MAL_IER_OE 0x00000002
102#define MAL_IER_PE 0x00000001
103
104
105#define MAL_IER_PTE 0x00000080
106#define MAL_IER_PRE 0x00000040
107#define MAL_IER_PWE 0x00000020
108
109#define MAL_IER_SOC_EVENTS (MAL_IER_PTE | MAL_IER_PRE | MAL_IER_PWE)
110#define MAL_IER_EVENTS (MAL_IER_SOC_EVENTS | MAL_IER_DE | \
111 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
112
113#define MAL_TXCASR 0x04
114#define MAL_TXCARR 0x05
115#define MAL_TXEOBISR 0x06
116#define MAL_TXDEIR 0x07
117#define MAL_RXCASR 0x10
118#define MAL_RXCARR 0x11
119#define MAL_RXEOBISR 0x12
120#define MAL_RXDEIR 0x13
121#define MAL_TXCTPR(n) ((n) + 0x20)
122#define MAL_RXCTPR(n) ((n) + 0x40)
123#define MAL_RCBS(n) ((n) + 0x60)
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126
127
128#define MAL_MAX_TX_SIZE 4080
129#define MAL_MAX_RX_SIZE 4080
130
131static inline int mal_rx_size(int len)
132{
133 len = (len + 0xf) & ~0xf;
134 return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
135}
136
137static inline int mal_tx_chunks(int len)
138{
139 return DIV_ROUND_UP(len, MAL_MAX_TX_SIZE);
140}
141
142#define MAL_CHAN_MASK(n) (0x80000000 >> (n))
143
144
145struct mal_descriptor {
146 u16 ctrl;
147 u16 data_len;
148 u32 data_ptr;
149};
150
151
152
153#define MAL_RX_CTRL_EMPTY 0x8000
154#define MAL_RX_CTRL_WRAP 0x4000
155#define MAL_RX_CTRL_CM 0x2000
156#define MAL_RX_CTRL_LAST 0x1000
157#define MAL_RX_CTRL_FIRST 0x0800
158#define MAL_RX_CTRL_INTR 0x0400
159#define MAL_RX_CTRL_SINGLE (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
160#define MAL_IS_SINGLE_RX(ctrl) (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
161
162#define MAL_TX_CTRL_READY 0x8000
163#define MAL_TX_CTRL_WRAP 0x4000
164#define MAL_TX_CTRL_CM 0x2000
165#define MAL_TX_CTRL_LAST 0x1000
166#define MAL_TX_CTRL_INTR 0x0400
167
168struct mal_commac_ops {
169 void (*poll_tx) (void *dev);
170 int (*poll_rx) (void *dev, int budget);
171 int (*peek_rx) (void *dev);
172 void (*rxde) (void *dev);
173};
174
175struct mal_commac {
176 struct mal_commac_ops *ops;
177 void *dev;
178 struct list_head poll_list;
179 long flags;
180#define MAL_COMMAC_RX_STOPPED 0
181#define MAL_COMMAC_POLL_DISABLED 1
182 u32 tx_chan_mask;
183 u32 rx_chan_mask;
184 struct list_head list;
185};
186
187struct mal_instance {
188 int version;
189 dcr_host_t dcr_host;
190
191 int num_tx_chans;
192 int num_rx_chans;
193 int txeob_irq;
194 int rxeob_irq;
195 int txde_irq;
196 int rxde_irq;
197 int serr_irq;
198
199 struct list_head poll_list;
200 struct napi_struct napi;
201
202 struct list_head list;
203 u32 tx_chan_mask;
204 u32 rx_chan_mask;
205
206 dma_addr_t bd_dma;
207 struct mal_descriptor *bd_virt;
208
209 struct platform_device *ofdev;
210 int index;
211 spinlock_t lock;
212
213 struct net_device dummy_dev;
214
215 unsigned int features;
216};
217
218static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
219{
220 return dcr_read(mal->dcr_host, reg);
221}
222
223static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
224{
225 dcr_write(mal->dcr_host, reg, val);
226}
227
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231
232
233#define MAL_FTR_CLEAR_ICINTSTAT 0x00000001
234
235
236
237
238#define MAL_FTR_COMMON_ERR_INT 0x00000002
239
240enum {
241 MAL_FTRS_ALWAYS = 0,
242
243 MAL_FTRS_POSSIBLE =
244#ifdef CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT
245 MAL_FTR_CLEAR_ICINTSTAT |
246#endif
247#ifdef CONFIG_IBM_EMAC_MAL_COMMON_ERR
248 MAL_FTR_COMMON_ERR_INT |
249#endif
250 0,
251};
252
253static inline int mal_has_feature(struct mal_instance *dev,
254 unsigned long feature)
255{
256 return (MAL_FTRS_ALWAYS & feature) ||
257 (MAL_FTRS_POSSIBLE & dev->features & feature);
258}
259
260
261int mal_init(void);
262void mal_exit(void);
263
264int mal_register_commac(struct mal_instance *mal,
265 struct mal_commac *commac);
266void mal_unregister_commac(struct mal_instance *mal,
267 struct mal_commac *commac);
268int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size);
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270
271
272
273int mal_tx_bd_offset(struct mal_instance *mal, int channel);
274int mal_rx_bd_offset(struct mal_instance *mal, int channel);
275
276void mal_enable_tx_channel(struct mal_instance *mal, int channel);
277void mal_disable_tx_channel(struct mal_instance *mal, int channel);
278void mal_enable_rx_channel(struct mal_instance *mal, int channel);
279void mal_disable_rx_channel(struct mal_instance *mal, int channel);
280
281void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac);
282void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac);
283
284
285void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac);
286void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac);
287
288
289struct mal_regs {
290 u32 tx_count;
291 u32 rx_count;
292
293 u32 cfg;
294 u32 esr;
295 u32 ier;
296 u32 tx_casr;
297 u32 tx_carr;
298 u32 tx_eobisr;
299 u32 tx_deir;
300 u32 rx_casr;
301 u32 rx_carr;
302 u32 rx_eobisr;
303 u32 rx_deir;
304 u32 tx_ctpr[32];
305 u32 rx_ctpr[32];
306 u32 rcbs[32];
307};
308
309int mal_get_regs_len(struct mal_instance *mal);
310void *mal_dump_regs(struct mal_instance *mal, void *buf);
311
312#endif
313