1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (c) 2018 Intel Corporation */ 3 4#ifndef _IGC_DEFINES_H_ 5#define _IGC_DEFINES_H_ 6 7#define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 8 9/* PCI Bus Info */ 10#define PCIE_DEVICE_CONTROL2 0x28 11#define PCIE_DEVICE_CONTROL2_16ms 0x0005 12 13/* Physical Func Reset Done Indication */ 14#define IGC_CTRL_EXT_LINK_MODE_MASK 0x00C00000 15 16/* Loop limit on how long we wait for auto-negotiation to complete */ 17#define COPPER_LINK_UP_LIMIT 10 18#define PHY_AUTO_NEG_LIMIT 45 19#define PHY_FORCE_LIMIT 20 20 21/* Number of 100 microseconds we wait for PCI Express master disable */ 22#define MASTER_DISABLE_TIMEOUT 800 23/*Blocks new Master requests */ 24#define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004 25/* Status of Master requests. */ 26#define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000 27 28/* PCI Express Control */ 29#define IGC_GCR_CMPL_TMOUT_MASK 0x0000F000 30#define IGC_GCR_CMPL_TMOUT_10ms 0x00001000 31#define IGC_GCR_CMPL_TMOUT_RESEND 0x00010000 32#define IGC_GCR_CAP_VER2 0x00040000 33 34/* Receive Address 35 * Number of high/low register pairs in the RAR. The RAR (Receive Address 36 * Registers) holds the directed and multicast addresses that we monitor. 37 * Technically, we have 16 spots. However, we reserve one of these spots 38 * (RAR[15]) for our directed address used by controllers with 39 * manageability enabled, allowing us room for 15 multicast addresses. 40 */ 41#define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */ 42#define IGC_RAH_POOL_1 0x00040000 43#define IGC_RAL_MAC_ADDR_LEN 4 44#define IGC_RAH_MAC_ADDR_LEN 2 45 46/* Error Codes */ 47#define IGC_SUCCESS 0 48#define IGC_ERR_NVM 1 49#define IGC_ERR_PHY 2 50#define IGC_ERR_CONFIG 3 51#define IGC_ERR_PARAM 4 52#define IGC_ERR_MAC_INIT 5 53#define IGC_ERR_RESET 9 54#define IGC_ERR_MASTER_REQUESTS_PENDING 10 55#define IGC_ERR_BLK_PHY_RESET 12 56#define IGC_ERR_SWFW_SYNC 13 57 58/* Device Control */ 59#define IGC_CTRL_RST 0x04000000 /* Global reset */ 60 61#define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 62#define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 63#define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */ 64#define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 65 66#define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 67#define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 68 69#define IGC_CONNSW_AUTOSENSE_EN 0x1 70 71/* PBA constants */ 72#define IGC_PBA_34K 0x0022 73 74/* SW Semaphore Register */ 75#define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 76#define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 77 78/* SWFW_SYNC Definitions */ 79#define IGC_SWFW_EEP_SM 0x1 80#define IGC_SWFW_PHY0_SM 0x2 81 82/* Autoneg Advertisement Register */ 83#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 84#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 85#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 86#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 87#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 88#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 89 90/* Link Partner Ability Register (Base Page) */ 91#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 92#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 93 94/* 1000BASE-T Control Register */ 95#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 96#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 97#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 98 99/* 1000BASE-T Status Register */ 100#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 101#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 102 103/* PHY GPY 211 registers */ 104#define STANDARD_AN_REG_MASK 0x0007 /* MMD */ 105#define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */ 106#define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */ 107#define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */ 108 109/* NVM Control */ 110/* Number of milliseconds for NVM auto read done after MAC reset. */ 111#define AUTO_READ_DONE_TIMEOUT 10 112#define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 113#define IGC_EECD_REQ 0x00000040 /* NVM Access Request */ 114#define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */ 115/* NVM Addressing bits based on type 0=small, 1=large */ 116#define IGC_EECD_ADDR_BITS 0x00000400 117#define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 118#define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 119#define IGC_EECD_SIZE_EX_SHIFT 11 120#define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */ 121#define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done*/ 122#define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */ 123#define IGC_FLUDONE_ATTEMPTS 20000 124#define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 125 126/* Offset to data in NVM read/write registers */ 127#define IGC_NVM_RW_REG_DATA 16 128#define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 129#define IGC_NVM_RW_REG_START 1 /* Start operation */ 130#define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 131#define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */ 132 133/* NVM Word Offsets */ 134#define NVM_CHECKSUM_REG 0x003F 135 136/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 137#define NVM_SUM 0xBABA 138 139#define NVM_PBA_OFFSET_0 8 140#define NVM_PBA_OFFSET_1 9 141#define NVM_RESERVED_WORD 0xFFFF 142#define NVM_PBA_PTR_GUARD 0xFAFA 143#define NVM_WORD_SIZE_BASE_SHIFT 6 144 145/* Collision related configuration parameters */ 146#define IGC_COLLISION_THRESHOLD 15 147#define IGC_CT_SHIFT 4 148#define IGC_COLLISION_DISTANCE 63 149#define IGC_COLD_SHIFT 12 150 151/* Device Status */ 152#define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 153#define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 154#define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 155#define IGC_STATUS_FUNC_SHIFT 2 156#define IGC_STATUS_FUNC_1 0x00000004 /* Function 1 */ 157#define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */ 158#define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 159#define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 160#define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s */ 161 162#define SPEED_10 10 163#define SPEED_100 100 164#define SPEED_1000 1000 165#define SPEED_2500 2500 166#define HALF_DUPLEX 1 167#define FULL_DUPLEX 2 168 169/* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */ 170#define ADVERTISE_10_HALF 0x0001 171#define ADVERTISE_10_FULL 0x0002 172#define ADVERTISE_100_HALF 0x0004 173#define ADVERTISE_100_FULL 0x0008 174#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 175#define ADVERTISE_1000_FULL 0x0020 176#define ADVERTISE_2500_HALF 0x0040 /* Not used, just FYI */ 177#define ADVERTISE_2500_FULL 0x0080 178 179#define IGC_ALL_SPEED_DUPLEX_2500 ( \ 180 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 181 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 182 183#define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500 184 185/* Interrupt Cause Read */ 186#define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */ 187#define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */ 188#define IGC_ICR_LSC BIT(2) /* Link Status Change */ 189#define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */ 190#define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */ 191#define IGC_ICR_RXO BIT(6) /* Rx overrun */ 192#define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */ 193#define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */ 194 195/* If this bit asserted, the driver should claim the interrupt */ 196#define IGC_ICR_INT_ASSERTED BIT(31) 197 198#define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */ 199 200#define IMS_ENABLE_MASK ( \ 201 IGC_IMS_RXT0 | \ 202 IGC_IMS_TXDW | \ 203 IGC_IMS_RXDMT0 | \ 204 IGC_IMS_RXSEQ | \ 205 IGC_IMS_LSC) 206 207/* Interrupt Mask Set */ 208#define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */ 209#define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */ 210#define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */ 211#define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */ 212#define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */ 213#define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */ 214#define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */ 215 216#define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */ 217#define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */ 218 219/* Interrupt Cause Set */ 220#define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */ 221#define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* rx desc min. threshold */ 222#define IGC_ICS_DRSTA IGC_ICR_DRSTA /* Device Reset Aserted */ 223 224#define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 225#define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 226#define IGC_IVAR_VALID 0x80 227#define IGC_GPIE_NSICR 0x00000001 228#define IGC_GPIE_MSIX_MODE 0x00000010 229#define IGC_GPIE_EIAME 0x40000000 230#define IGC_GPIE_PBA 0x80000000 231 232/* Transmit Descriptor bit definitions */ 233#define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 234#define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 235#define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 236#define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 237#define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */ 238#define IGC_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 239#define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 240#define IGC_TXD_CMD_RS 0x08000000 /* Report Status */ 241#define IGC_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 242#define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 243#define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 244#define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 245#define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 246#define IGC_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 247#define IGC_TXD_STAT_LC 0x00000004 /* Late Collisions */ 248#define IGC_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 249#define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */ 250#define IGC_TXD_CMD_IP 0x02000000 /* IP packet */ 251#define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 252#define IGC_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 253#define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 254 255/* Transmit Control */ 256#define IGC_TCTL_EN 0x00000002 /* enable Tx */ 257#define IGC_TCTL_PSP 0x00000008 /* pad short packets */ 258#define IGC_TCTL_CT 0x00000ff0 /* collision threshold */ 259#define IGC_TCTL_COLD 0x003ff000 /* collision distance */ 260#define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 261#define IGC_TCTL_MULR 0x10000000 /* Multiple request support */ 262 263#define IGC_CT_SHIFT 4 264#define IGC_COLLISION_THRESHOLD 15 265 266/* Flow Control Constants */ 267#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 268#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 269#define FLOW_CONTROL_TYPE 0x8808 270/* Enable XON frame transmission */ 271#define IGC_FCRTL_XONE 0x80000000 272 273/* Management Control */ 274#define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 275#define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 276 277/* Receive Control */ 278#define IGC_RCTL_RST 0x00000001 /* Software reset */ 279#define IGC_RCTL_EN 0x00000002 /* enable */ 280#define IGC_RCTL_SBP 0x00000004 /* store bad packet */ 281#define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */ 282#define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */ 283#define IGC_RCTL_LPE 0x00000020 /* long packet enable */ 284#define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 285#define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 286 287#define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 288#define IGC_RCTL_BAM 0x00008000 /* broadcast enable */ 289 290/* Receive Descriptor bit definitions */ 291#define IGC_RXD_STAT_EOP 0x02 /* End of Packet */ 292 293#define IGC_RXDEXT_STATERR_CE 0x01000000 294#define IGC_RXDEXT_STATERR_SE 0x02000000 295#define IGC_RXDEXT_STATERR_SEQ 0x04000000 296#define IGC_RXDEXT_STATERR_CXE 0x10000000 297#define IGC_RXDEXT_STATERR_TCPE 0x20000000 298#define IGC_RXDEXT_STATERR_IPE 0x40000000 299#define IGC_RXDEXT_STATERR_RXE 0x80000000 300 301/* Same mask, but for extended and packet split descriptors */ 302#define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \ 303 IGC_RXDEXT_STATERR_CE | \ 304 IGC_RXDEXT_STATERR_SE | \ 305 IGC_RXDEXT_STATERR_SEQ | \ 306 IGC_RXDEXT_STATERR_CXE | \ 307 IGC_RXDEXT_STATERR_RXE) 308 309/* Header split receive */ 310#define IGC_RFCTL_IPV6_EX_DIS 0x00010000 311#define IGC_RFCTL_LEF 0x00040000 312 313#define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 314 315#define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */ 316#define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */ 317#define IGC_RCTL_DPF 0x00400000 /* discard pause frames */ 318#define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 319#define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 320 321#define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 322#define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 323 324/* GPY211 - I225 defines */ 325#define GPY_MMD_MASK 0xFFFF0000 326#define GPY_MMD_SHIFT 16 327#define GPY_REG_MASK 0x0000FFFF 328 329#define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 330 331/* MAC definitions */ 332#define IGC_FACTPS_MNGCG 0x20000000 333#define IGC_FWSM_MODE_MASK 0xE 334#define IGC_FWSM_MODE_SHIFT 1 335 336/* Management Control */ 337#define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 338#define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 339 340/* PHY */ 341#define PHY_REVISION_MASK 0xFFFFFFF0 342#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 343#define IGC_GEN_POLL_TIMEOUT 1920 344 345/* PHY Control Register */ 346#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 347#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 348#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 349#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 350#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 351#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 352#define MII_CR_SPEED_1000 0x0040 353#define MII_CR_SPEED_100 0x2000 354#define MII_CR_SPEED_10 0x0000 355 356/* PHY Status Register */ 357#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 358#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 359 360/* PHY 1000 MII Register/Bit Definitions */ 361/* PHY Registers defined by IEEE */ 362#define PHY_CONTROL 0x00 /* Control Register */ 363#define PHY_STATUS 0x01 /* Status Register */ 364#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 365#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 366#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 367#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 368#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 369#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 370 371/* Bit definitions for valid PHY IDs. I = Integrated E = External */ 372#define I225_I_PHY_ID 0x67C9DC00 373 374/* MDI Control */ 375#define IGC_MDIC_DATA_MASK 0x0000FFFF 376#define IGC_MDIC_REG_MASK 0x001F0000 377#define IGC_MDIC_REG_SHIFT 16 378#define IGC_MDIC_PHY_MASK 0x03E00000 379#define IGC_MDIC_PHY_SHIFT 21 380#define IGC_MDIC_OP_WRITE 0x04000000 381#define IGC_MDIC_OP_READ 0x08000000 382#define IGC_MDIC_READY 0x10000000 383#define IGC_MDIC_INT_EN 0x20000000 384#define IGC_MDIC_ERROR 0x40000000 385#define IGC_MDIC_DEST 0x80000000 386 387#define IGC_N0_QUEUE -1 388 389#endif /* _IGC_DEFINES_H_ */ 390