1
2
3
4#ifndef _MLXSW_REG_H
5#define _MLXSW_REG_H
6
7#include <linux/kernel.h>
8#include <linux/string.h>
9#include <linux/bitops.h>
10#include <linux/if_vlan.h>
11
12#include "item.h"
13#include "port.h"
14
15struct mlxsw_reg_info {
16 u16 id;
17 u16 len;
18 const char *name;
19};
20
21#define MLXSW_REG_DEFINE(_name, _id, _len) \
22static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
23 .id = _id, \
24 .len = _len, \
25 .name = #_name, \
26}
27
28#define MLXSW_REG(type) (&mlxsw_reg_##type)
29#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31
32
33
34
35
36#define MLXSW_REG_SGCR_ID 0x2000
37#define MLXSW_REG_SGCR_LEN 0x10
38
39MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40
41
42
43
44
45
46
47MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48
49static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50{
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_llb_set(payload, !!llb);
53}
54
55
56
57
58
59#define MLXSW_REG_SPAD_ID 0x2002
60#define MLXSW_REG_SPAD_LEN 0x10
61
62MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63
64
65
66
67
68
69
70MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71
72
73
74
75
76
77
78#define MLXSW_REG_SMID_ID 0x2007
79#define MLXSW_REG_SMID_LEN 0x240
80
81MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
82
83
84
85
86
87MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
88
89
90
91
92
93
94MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
95
96
97
98
99
100MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
101
102
103
104
105
106MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
107
108static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
109 u8 port, bool set)
110{
111 MLXSW_REG_ZERO(smid, payload);
112 mlxsw_reg_smid_swid_set(payload, 0);
113 mlxsw_reg_smid_mid_set(payload, mid);
114 mlxsw_reg_smid_port_set(payload, port, set);
115 mlxsw_reg_smid_port_mask_set(payload, port, 1);
116}
117
118
119
120
121
122#define MLXSW_REG_SSPR_ID 0x2008
123#define MLXSW_REG_SSPR_LEN 0x8
124
125MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
126
127
128
129
130
131
132
133
134
135
136
137MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
138
139
140
141
142
143
144MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
145
146
147
148
149
150
151
152MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
153
154
155
156
157
158
159
160
161
162MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
163
164static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
165{
166 MLXSW_REG_ZERO(sspr, payload);
167 mlxsw_reg_sspr_m_set(payload, 1);
168 mlxsw_reg_sspr_local_port_set(payload, local_port);
169 mlxsw_reg_sspr_sub_port_set(payload, 0);
170 mlxsw_reg_sspr_system_port_set(payload, local_port);
171}
172
173
174
175
176
177
178#define MLXSW_REG_SFDAT_ID 0x2009
179#define MLXSW_REG_SFDAT_LEN 0x8
180
181MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
182
183
184
185
186
187MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
188
189
190
191
192
193
194
195
196MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
197
198static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
199{
200 MLXSW_REG_ZERO(sfdat, payload);
201 mlxsw_reg_sfdat_swid_set(payload, 0);
202 mlxsw_reg_sfdat_age_time_set(payload, age_time);
203}
204
205
206
207
208
209
210
211
212#define MLXSW_REG_SFD_ID 0x200A
213#define MLXSW_REG_SFD_BASE_LEN 0x10
214#define MLXSW_REG_SFD_REC_LEN 0x10
215#define MLXSW_REG_SFD_REC_MAX_COUNT 64
216#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
218
219MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
220
221
222
223
224
225MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
226
227enum mlxsw_reg_sfd_op {
228
229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
230
231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
232
233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
234
235
236
237 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
238
239
240
241
242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
243
244
245
246
247
248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
249
250
251
252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
253};
254
255
256
257
258
259MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
260
261
262
263
264
265
266
267
268MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
269
270
271
272
273
274
275
276
277MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
278
279static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
280 u32 record_locator)
281{
282 MLXSW_REG_ZERO(sfd, payload);
283 mlxsw_reg_sfd_op_set(payload, op);
284 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
285}
286
287
288
289
290
291MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
292 MLXSW_REG_SFD_REC_LEN, 0x00, false);
293
294enum mlxsw_reg_sfd_rec_type {
295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
299};
300
301
302
303
304
305MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
306 MLXSW_REG_SFD_REC_LEN, 0x00, false);
307
308enum mlxsw_reg_sfd_rec_policy {
309
310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
311
312
313
314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
315
316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
317};
318
319
320
321
322
323MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
324 MLXSW_REG_SFD_REC_LEN, 0x00, false);
325
326
327
328
329
330
331
332MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
333 MLXSW_REG_SFD_REC_LEN, 0x00, false);
334
335
336
337
338
339MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
340 MLXSW_REG_SFD_REC_LEN, 0x02);
341
342enum mlxsw_reg_sfd_rec_action {
343
344 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
345
346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
347
348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
349
350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
352};
353
354
355
356
357
358
359MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
360 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
361
362
363
364
365
366
367
368MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
369 MLXSW_REG_SFD_REC_LEN, 0x08, false);
370
371
372
373
374
375
376
377
378
379
380
381MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
382 MLXSW_REG_SFD_REC_LEN, 0x08, false);
383
384
385
386
387
388MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
389 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
390
391static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
392 enum mlxsw_reg_sfd_rec_type rec_type,
393 const char *mac,
394 enum mlxsw_reg_sfd_rec_action action)
395{
396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
397
398 if (rec_index >= num_rec)
399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
404}
405
406static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 enum mlxsw_reg_sfd_rec_policy policy,
408 const char *mac, u16 fid_vid,
409 enum mlxsw_reg_sfd_rec_action action,
410 u8 local_port)
411{
412 mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
418}
419
420static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
421 char *mac, u16 *p_fid_vid,
422 u8 *p_local_port)
423{
424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
427}
428
429
430
431
432
433
434MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
435 MLXSW_REG_SFD_REC_LEN, 0x08, false);
436
437
438
439
440
441
442
443
444
445
446
447MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
448 MLXSW_REG_SFD_REC_LEN, 0x08, false);
449
450
451
452
453
454MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
455 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
456
457
458
459
460
461MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
462 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
463
464static inline void
465mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
466 enum mlxsw_reg_sfd_rec_policy policy,
467 const char *mac, u16 fid_vid,
468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
469 u16 lag_id)
470{
471 mlxsw_reg_sfd_rec_pack(payload, rec_index,
472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
473 mac, action);
474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
479}
480
481static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
482 char *mac, u16 *p_vid,
483 u16 *p_lag_id)
484{
485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
488}
489
490
491
492
493
494
495
496
497MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
498 MLXSW_REG_SFD_REC_LEN, 0x08, false);
499
500
501
502
503
504
505MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
506 MLXSW_REG_SFD_REC_LEN, 0x08, false);
507
508
509
510
511
512
513
514MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
515 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
516
517static inline void
518mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
519 const char *mac, u16 fid_vid,
520 enum mlxsw_reg_sfd_rec_action action, u16 mid)
521{
522 mlxsw_reg_sfd_rec_pack(payload, rec_index,
523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
527}
528
529
530
531
532
533
534
535MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
537
538
539
540
541
542MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
543 MLXSW_REG_SFD_REC_LEN, 0x08, false);
544
545enum mlxsw_reg_sfd_uc_tunnel_protocol {
546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
548};
549
550
551
552
553
554MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
556
557
558
559
560
561
562
563
564MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
566
567static inline void
568mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
569 enum mlxsw_reg_sfd_rec_policy policy,
570 const char *mac, u16 fid,
571 enum mlxsw_reg_sfd_rec_action action, u32 uip,
572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
573{
574 mlxsw_reg_sfd_rec_pack(payload, rec_index,
575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
576 action);
577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
582}
583
584
585
586
587
588
589#define MLXSW_REG_SFN_ID 0x200B
590#define MLXSW_REG_SFN_BASE_LEN 0x10
591#define MLXSW_REG_SFN_REC_LEN 0x10
592#define MLXSW_REG_SFN_REC_MAX_COUNT 64
593#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
595
596MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
597
598
599
600
601
602MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
603
604
605
606
607
608MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
609
610
611
612
613
614
615
616
617
618MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
619
620static inline void mlxsw_reg_sfn_pack(char *payload)
621{
622 MLXSW_REG_ZERO(sfn, payload);
623 mlxsw_reg_sfn_swid_set(payload, 0);
624 mlxsw_reg_sfn_end_set(payload, 1);
625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
626}
627
628
629
630
631
632MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
633 MLXSW_REG_SFN_REC_LEN, 0x00, false);
634
635enum mlxsw_reg_sfn_rec_type {
636
637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
638
639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
640
641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
642
643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
644};
645
646
647
648
649
650MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
651 MLXSW_REG_SFN_REC_LEN, 0x00, false);
652
653
654
655
656
657MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
658 MLXSW_REG_SFN_REC_LEN, 0x02);
659
660
661
662
663
664
665MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
666 MLXSW_REG_SFN_REC_LEN, 0x08, false);
667
668
669
670
671
672MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
673 MLXSW_REG_SFN_REC_LEN, 0x08, false);
674
675
676
677
678
679MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
680 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
681
682static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
683 char *mac, u16 *p_vid,
684 u8 *p_local_port)
685{
686 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
687 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
688 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
689}
690
691
692
693
694
695MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
696 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
697
698static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
699 char *mac, u16 *p_vid,
700 u16 *p_lag_id)
701{
702 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
703 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
704 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
705}
706
707
708
709
710
711#define MLXSW_REG_SPMS_ID 0x200D
712#define MLXSW_REG_SPMS_LEN 0x404
713
714MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
715
716
717
718
719
720MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
721
722enum mlxsw_reg_spms_state {
723 MLXSW_REG_SPMS_STATE_NO_CHANGE,
724 MLXSW_REG_SPMS_STATE_DISCARDING,
725 MLXSW_REG_SPMS_STATE_LEARNING,
726 MLXSW_REG_SPMS_STATE_FORWARDING,
727};
728
729
730
731
732
733
734
735
736
737MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
738
739static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
740{
741 MLXSW_REG_ZERO(spms, payload);
742 mlxsw_reg_spms_local_port_set(payload, local_port);
743}
744
745static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
746 enum mlxsw_reg_spms_state state)
747{
748 mlxsw_reg_spms_state_set(payload, vid, state);
749}
750
751
752
753
754
755#define MLXSW_REG_SPVID_ID 0x200E
756#define MLXSW_REG_SPVID_LEN 0x08
757
758MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
759
760
761
762
763
764MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
765
766
767
768
769
770
771MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
772
773
774
775
776
777MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
778
779static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
780{
781 MLXSW_REG_ZERO(spvid, payload);
782 mlxsw_reg_spvid_local_port_set(payload, local_port);
783 mlxsw_reg_spvid_pvid_set(payload, pvid);
784}
785
786
787
788
789
790
791
792#define MLXSW_REG_SPVM_ID 0x200F
793#define MLXSW_REG_SPVM_BASE_LEN 0x04
794#define MLXSW_REG_SPVM_REC_LEN 0x04
795#define MLXSW_REG_SPVM_REC_MAX_COUNT 255
796#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
797 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
798
799MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
800
801
802
803
804
805
806
807MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
808
809
810
811
812
813
814MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
815
816
817
818
819
820MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
821
822
823
824
825
826
827MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
828
829
830
831
832
833MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
834
835
836
837
838
839MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
840 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
841 MLXSW_REG_SPVM_REC_LEN, 0, false);
842
843
844
845
846
847MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
848 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
849 MLXSW_REG_SPVM_REC_LEN, 0, false);
850
851
852
853
854
855
856MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
857 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
858 MLXSW_REG_SPVM_REC_LEN, 0, false);
859
860
861
862
863
864MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
865 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
866 MLXSW_REG_SPVM_REC_LEN, 0, false);
867
868static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
869 u16 vid_begin, u16 vid_end,
870 bool is_member, bool untagged)
871{
872 int size = vid_end - vid_begin + 1;
873 int i;
874
875 MLXSW_REG_ZERO(spvm, payload);
876 mlxsw_reg_spvm_local_port_set(payload, local_port);
877 mlxsw_reg_spvm_num_rec_set(payload, size);
878
879 for (i = 0; i < size; i++) {
880 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
881 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
882 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
883 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
884 }
885}
886
887
888
889
890
891
892#define MLXSW_REG_SPAFT_ID 0x2010
893#define MLXSW_REG_SPAFT_LEN 0x08
894
895MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
896
897
898
899
900
901
902
903MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
904
905
906
907
908
909
910MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
911
912
913
914
915
916MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
917
918
919
920
921
922MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
923
924
925
926
927
928MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
929
930static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
931 bool allow_untagged)
932{
933 MLXSW_REG_ZERO(spaft, payload);
934 mlxsw_reg_spaft_local_port_set(payload, local_port);
935 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
936 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
937 mlxsw_reg_spaft_allow_tagged_set(payload, true);
938}
939
940
941
942
943
944
945#define MLXSW_REG_SFGC_ID 0x2011
946#define MLXSW_REG_SFGC_LEN 0x10
947
948MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
949
950enum mlxsw_reg_sfgc_type {
951 MLXSW_REG_SFGC_TYPE_BROADCAST,
952 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
953 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
954 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
955 MLXSW_REG_SFGC_TYPE_RESERVED,
956 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
957 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
958 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
959 MLXSW_REG_SFGC_TYPE_MAX,
960};
961
962
963
964
965
966MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
967
968enum mlxsw_reg_sfgc_bridge_type {
969 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
970 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
971};
972
973
974
975
976
977
978MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
979
980enum mlxsw_flood_table_type {
981 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
982 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
983 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
984 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
985 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
986};
987
988
989
990
991
992
993
994MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
995
996
997
998
999
1000
1001MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1002
1003
1004
1005
1006
1007MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1008
1009
1010
1011
1012
1013MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1014
1015
1016
1017
1018
1019MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1020
1021static inline void
1022mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1023 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1024 enum mlxsw_flood_table_type table_type,
1025 unsigned int flood_table)
1026{
1027 MLXSW_REG_ZERO(sfgc, payload);
1028 mlxsw_reg_sfgc_type_set(payload, type);
1029 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1030 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1031 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1032 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1033}
1034
1035
1036
1037
1038
1039
1040#define MLXSW_REG_SFTR_ID 0x2012
1041#define MLXSW_REG_SFTR_LEN 0x420
1042
1043MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1044
1045
1046
1047
1048
1049MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1050
1051
1052
1053
1054
1055
1056MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1057
1058
1059
1060
1061
1062
1063MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1064
1065
1066
1067
1068
1069MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1070
1071
1072
1073
1074
1075MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1076
1077
1078
1079
1080
1081MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1082
1083
1084
1085
1086
1087MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1088
1089static inline void mlxsw_reg_sftr_pack(char *payload,
1090 unsigned int flood_table,
1091 unsigned int index,
1092 enum mlxsw_flood_table_type table_type,
1093 unsigned int range, u8 port, bool set)
1094{
1095 MLXSW_REG_ZERO(sftr, payload);
1096 mlxsw_reg_sftr_swid_set(payload, 0);
1097 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1098 mlxsw_reg_sftr_index_set(payload, index);
1099 mlxsw_reg_sftr_table_type_set(payload, table_type);
1100 mlxsw_reg_sftr_range_set(payload, range);
1101 mlxsw_reg_sftr_port_set(payload, port, set);
1102 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1103}
1104
1105
1106
1107
1108
1109
1110#define MLXSW_REG_SFDF_ID 0x2013
1111#define MLXSW_REG_SFDF_LEN 0x14
1112
1113MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1114
1115
1116
1117
1118
1119MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1120
1121enum mlxsw_reg_sfdf_flush_type {
1122 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1123 MLXSW_REG_SFDF_FLUSH_PER_FID,
1124 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1125 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1126 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1127 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1128 MLXSW_REG_SFDF_FLUSH_PER_NVE,
1129 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1130};
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1147
1148
1149
1150
1151
1152
1153
1154MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1155
1156static inline void mlxsw_reg_sfdf_pack(char *payload,
1157 enum mlxsw_reg_sfdf_flush_type type)
1158{
1159 MLXSW_REG_ZERO(sfdf, payload);
1160 mlxsw_reg_sfdf_flush_type_set(payload, type);
1161 mlxsw_reg_sfdf_flush_static_set(payload, true);
1162}
1163
1164
1165
1166
1167
1168MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1169
1170
1171
1172
1173
1174MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1175
1176
1177
1178
1179
1180MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1181
1182
1183
1184
1185
1186MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1187
1188
1189
1190
1191
1192MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1193
1194
1195
1196
1197
1198
1199
1200#define MLXSW_REG_SLDR_ID 0x2014
1201#define MLXSW_REG_SLDR_LEN 0x0C
1202
1203MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1204
1205enum mlxsw_reg_sldr_op {
1206
1207 MLXSW_REG_SLDR_OP_LAG_CREATE,
1208 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1209
1210 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1211
1212 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1213};
1214
1215
1216
1217
1218
1219MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1220
1221
1222
1223
1224
1225MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1226
1227static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1228{
1229 MLXSW_REG_ZERO(sldr, payload);
1230 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1231 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1232}
1233
1234static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1235{
1236 MLXSW_REG_ZERO(sldr, payload);
1237 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1238 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1239}
1240
1241
1242
1243
1244
1245
1246
1247MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1248
1249
1250
1251
1252
1253MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1254
1255static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1256 u8 local_port)
1257{
1258 MLXSW_REG_ZERO(sldr, payload);
1259 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1260 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1261 mlxsw_reg_sldr_num_ports_set(payload, 1);
1262 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1263}
1264
1265static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1266 u8 local_port)
1267{
1268 MLXSW_REG_ZERO(sldr, payload);
1269 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1270 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1271 mlxsw_reg_sldr_num_ports_set(payload, 1);
1272 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1273}
1274
1275
1276
1277
1278
1279
1280#define MLXSW_REG_SLCR_ID 0x2015
1281#define MLXSW_REG_SLCR_LEN 0x10
1282
1283MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1284
1285enum mlxsw_reg_slcr_pp {
1286
1287 MLXSW_REG_SLCR_PP_GLOBAL,
1288
1289 MLXSW_REG_SLCR_PP_PER_PORT,
1290};
1291
1292
1293
1294
1295
1296
1297MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1298
1299
1300
1301
1302
1303
1304
1305
1306MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1307
1308enum mlxsw_reg_slcr_type {
1309 MLXSW_REG_SLCR_TYPE_CRC,
1310 MLXSW_REG_SLCR_TYPE_XOR,
1311 MLXSW_REG_SLCR_TYPE_RANDOM,
1312};
1313
1314
1315
1316
1317
1318MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1319
1320
1321#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1322
1323#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1324
1325#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1326#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1327 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1328 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1329
1330#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1331
1332#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1333#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1334 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1335 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1336
1337#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1338
1339#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1340#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1341 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1342 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1343
1344#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1345
1346#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1347#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1348 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1349 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1350
1351#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1352
1353#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1354
1355#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1356
1357#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1358
1359#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1360
1361#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1362
1363#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1364
1365#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1366
1367#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1368
1369#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1370
1371
1372
1373
1374
1375
1376
1377
1378MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1379
1380
1381
1382
1383
1384MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1385
1386static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1387{
1388 MLXSW_REG_ZERO(slcr, payload);
1389 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1390 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1391 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1392 mlxsw_reg_slcr_seed_set(payload, seed);
1393}
1394
1395
1396
1397
1398
1399
1400#define MLXSW_REG_SLCOR_ID 0x2016
1401#define MLXSW_REG_SLCOR_LEN 0x10
1402
1403MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1404
1405enum mlxsw_reg_slcor_col {
1406
1407 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1408 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1409 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1410 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1411};
1412
1413
1414
1415
1416
1417MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1418
1419
1420
1421
1422
1423
1424MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1425
1426
1427
1428
1429
1430MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1431
1432
1433
1434
1435
1436
1437MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1438
1439static inline void mlxsw_reg_slcor_pack(char *payload,
1440 u8 local_port, u16 lag_id,
1441 enum mlxsw_reg_slcor_col col)
1442{
1443 MLXSW_REG_ZERO(slcor, payload);
1444 mlxsw_reg_slcor_col_set(payload, col);
1445 mlxsw_reg_slcor_local_port_set(payload, local_port);
1446 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1447}
1448
1449static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1450 u8 local_port, u16 lag_id,
1451 u8 port_index)
1452{
1453 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1454 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1455 mlxsw_reg_slcor_port_index_set(payload, port_index);
1456}
1457
1458static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1459 u8 local_port, u16 lag_id)
1460{
1461 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1462 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1463}
1464
1465static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1466 u8 local_port, u16 lag_id)
1467{
1468 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1469 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1470}
1471
1472static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1473 u8 local_port, u16 lag_id)
1474{
1475 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1476 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1477}
1478
1479
1480
1481
1482
1483#define MLXSW_REG_SPMLR_ID 0x2018
1484#define MLXSW_REG_SPMLR_LEN 0x8
1485
1486MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1487
1488
1489
1490
1491
1492MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1493
1494
1495
1496
1497
1498
1499MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1500
1501enum mlxsw_reg_spmlr_learn_mode {
1502 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1503 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1504 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1505};
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1519
1520static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1521 enum mlxsw_reg_spmlr_learn_mode mode)
1522{
1523 MLXSW_REG_ZERO(spmlr, payload);
1524 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1525 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1526 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1527}
1528
1529
1530
1531
1532
1533
1534#define MLXSW_REG_SVFA_ID 0x201C
1535#define MLXSW_REG_SVFA_LEN 0x10
1536
1537MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1538
1539
1540
1541
1542
1543MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1544
1545
1546
1547
1548
1549
1550
1551MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1552
1553enum mlxsw_reg_svfa_mt {
1554 MLXSW_REG_SVFA_MT_VID_TO_FID,
1555 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1556};
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1567
1568
1569
1570
1571
1572
1573
1574
1575MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1576
1577
1578
1579
1580
1581MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1582
1583
1584
1585
1586
1587MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1588
1589
1590
1591
1592
1593
1594
1595MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1596
1597
1598
1599
1600
1601
1602
1603MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1604
1605static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1606 enum mlxsw_reg_svfa_mt mt, bool valid,
1607 u16 fid, u16 vid)
1608{
1609 MLXSW_REG_ZERO(svfa, payload);
1610 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1611 mlxsw_reg_svfa_swid_set(payload, 0);
1612 mlxsw_reg_svfa_local_port_set(payload, local_port);
1613 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1614 mlxsw_reg_svfa_v_set(payload, valid);
1615 mlxsw_reg_svfa_fid_set(payload, fid);
1616 mlxsw_reg_svfa_vid_set(payload, vid);
1617}
1618
1619
1620
1621
1622
1623#define MLXSW_REG_SVPE_ID 0x201E
1624#define MLXSW_REG_SVPE_LEN 0x4
1625
1626MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1627
1628
1629
1630
1631
1632
1633
1634MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1635
1636
1637
1638
1639
1640
1641
1642MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1643
1644static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1645 bool enable)
1646{
1647 MLXSW_REG_ZERO(svpe, payload);
1648 mlxsw_reg_svpe_local_port_set(payload, local_port);
1649 mlxsw_reg_svpe_vp_en_set(payload, enable);
1650}
1651
1652
1653
1654
1655
1656#define MLXSW_REG_SFMR_ID 0x201F
1657#define MLXSW_REG_SFMR_LEN 0x18
1658
1659MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1660
1661enum mlxsw_reg_sfmr_op {
1662 MLXSW_REG_SFMR_OP_CREATE_FID,
1663 MLXSW_REG_SFMR_OP_DESTROY_FID,
1664};
1665
1666
1667
1668
1669
1670
1671
1672MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1673
1674
1675
1676
1677
1678MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1679
1680
1681
1682
1683
1684
1685
1686MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1687
1688
1689
1690
1691
1692
1693
1694
1695MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1696
1697
1698
1699
1700
1701
1702
1703MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1704
1705
1706
1707
1708
1709
1710
1711
1712MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1713
1714
1715
1716
1717
1718
1719
1720MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1721
1722static inline void mlxsw_reg_sfmr_pack(char *payload,
1723 enum mlxsw_reg_sfmr_op op, u16 fid,
1724 u16 fid_offset)
1725{
1726 MLXSW_REG_ZERO(sfmr, payload);
1727 mlxsw_reg_sfmr_op_set(payload, op);
1728 mlxsw_reg_sfmr_fid_set(payload, fid);
1729 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1730 mlxsw_reg_sfmr_vtfp_set(payload, false);
1731 mlxsw_reg_sfmr_vv_set(payload, false);
1732}
1733
1734
1735
1736
1737
1738#define MLXSW_REG_SPVMLR_ID 0x2020
1739#define MLXSW_REG_SPVMLR_BASE_LEN 0x04
1740#define MLXSW_REG_SPVMLR_REC_LEN 0x04
1741#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1742#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1743 MLXSW_REG_SPVMLR_REC_LEN * \
1744 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1745
1746MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1747
1748
1749
1750
1751
1752
1753
1754MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1755
1756
1757
1758
1759
1760MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1761
1762
1763
1764
1765
1766
1767MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1768 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1769
1770
1771
1772
1773
1774MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1775 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1776
1777static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1778 u16 vid_begin, u16 vid_end,
1779 bool learn_enable)
1780{
1781 int num_rec = vid_end - vid_begin + 1;
1782 int i;
1783
1784 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1785
1786 MLXSW_REG_ZERO(spvmlr, payload);
1787 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1788 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1789
1790 for (i = 0; i < num_rec; i++) {
1791 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1792 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1793 }
1794}
1795
1796
1797
1798
1799
1800#define MLXSW_REG_CWTP_ID 0x2802
1801#define MLXSW_REG_CWTP_BASE_LEN 0x28
1802#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1803#define MLXSW_REG_CWTP_LEN 0x40
1804
1805MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1806
1807
1808
1809
1810
1811
1812MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1813
1814
1815
1816
1817
1818MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1819
1820
1821
1822
1823
1824MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1825 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1826
1827
1828
1829
1830
1831
1832MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1833 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1834
1835
1836
1837
1838
1839MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1840 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1841
1842#define MLXSW_REG_CWTP_MIN_VALUE 64
1843#define MLXSW_REG_CWTP_MAX_PROFILE 2
1844#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1845
1846static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1847 u8 traffic_class)
1848{
1849 int i;
1850
1851 MLXSW_REG_ZERO(cwtp, payload);
1852 mlxsw_reg_cwtp_local_port_set(payload, local_port);
1853 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1854
1855 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1856 mlxsw_reg_cwtp_profile_min_set(payload, i,
1857 MLXSW_REG_CWTP_MIN_VALUE);
1858 mlxsw_reg_cwtp_profile_max_set(payload, i,
1859 MLXSW_REG_CWTP_MIN_VALUE);
1860 }
1861}
1862
1863#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1864
1865static inline void
1866mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1867 u32 probability)
1868{
1869 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1870
1871 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1872 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1873 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1874}
1875
1876
1877
1878
1879
1880#define MLXSW_REG_CWTPM_ID 0x2803
1881#define MLXSW_REG_CWTPM_LEN 0x44
1882
1883MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1884
1885
1886
1887
1888
1889
1890MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1891
1892
1893
1894
1895
1896MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1897
1898
1899
1900
1901
1902
1903
1904MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1905
1906
1907
1908
1909
1910
1911
1912MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1913
1914
1915
1916
1917
1918
1919
1920MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1921
1922
1923
1924
1925
1926
1927
1928MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1929
1930
1931
1932
1933
1934
1935
1936MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
1937
1938
1939
1940
1941
1942
1943
1944MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
1945
1946
1947
1948
1949
1950
1951
1952MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
1953
1954
1955
1956
1957
1958
1959
1960MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
1961
1962#define MLXSW_REG_CWTPM_RESET_PROFILE 0
1963
1964static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
1965 u8 traffic_class, u8 profile,
1966 bool wred, bool ecn)
1967{
1968 MLXSW_REG_ZERO(cwtpm, payload);
1969 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
1970 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
1971 mlxsw_reg_cwtpm_ew_set(payload, wred);
1972 mlxsw_reg_cwtpm_ee_set(payload, ecn);
1973 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
1974 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
1975 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
1976 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
1977 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
1978 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
1979}
1980
1981
1982
1983
1984
1985#define MLXSW_REG_PGCR_ID 0x3001
1986#define MLXSW_REG_PGCR_LEN 0x20
1987
1988MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
1989
1990
1991
1992
1993
1994
1995MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
1996
1997static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
1998{
1999 MLXSW_REG_ZERO(pgcr, payload);
2000 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2001}
2002
2003
2004
2005
2006
2007#define MLXSW_REG_PPBT_ID 0x3002
2008#define MLXSW_REG_PPBT_LEN 0x14
2009
2010MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2011
2012enum mlxsw_reg_pxbt_e {
2013 MLXSW_REG_PXBT_E_IACL,
2014 MLXSW_REG_PXBT_E_EACL,
2015};
2016
2017
2018
2019
2020MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2021
2022enum mlxsw_reg_pxbt_op {
2023 MLXSW_REG_PXBT_OP_BIND,
2024 MLXSW_REG_PXBT_OP_UNBIND,
2025};
2026
2027
2028
2029
2030MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2031
2032
2033
2034
2035
2036MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2037
2038
2039
2040
2041
2042
2043
2044MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2045
2046
2047
2048
2049
2050
2051MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2052
2053static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2054 enum mlxsw_reg_pxbt_op op,
2055 u8 local_port, u16 acl_info)
2056{
2057 MLXSW_REG_ZERO(ppbt, payload);
2058 mlxsw_reg_ppbt_e_set(payload, e);
2059 mlxsw_reg_ppbt_op_set(payload, op);
2060 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2061 mlxsw_reg_ppbt_g_set(payload, true);
2062 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2063}
2064
2065
2066
2067
2068
2069#define MLXSW_REG_PACL_ID 0x3004
2070#define MLXSW_REG_PACL_LEN 0x70
2071
2072MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2073
2074
2075
2076
2077
2078
2079MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2080
2081
2082
2083
2084
2085
2086MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2087
2088#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2089
2090
2091
2092
2093
2094
2095MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2096 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2097
2098static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2099 bool valid, const char *tcam_region_info)
2100{
2101 MLXSW_REG_ZERO(pacl, payload);
2102 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2103 mlxsw_reg_pacl_v_set(payload, valid);
2104 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2105}
2106
2107
2108
2109
2110
2111#define MLXSW_REG_PAGT_ID 0x3005
2112#define MLXSW_REG_PAGT_BASE_LEN 0x30
2113#define MLXSW_REG_PAGT_ACL_LEN 4
2114#define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2115#define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2116 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2117
2118MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2130
2131
2132
2133
2134
2135
2136MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2137
2138
2139
2140
2141
2142MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2143
2144static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2145{
2146 MLXSW_REG_ZERO(pagt, payload);
2147 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2148}
2149
2150static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2151 u16 acl_id)
2152{
2153 u8 size = mlxsw_reg_pagt_size_get(payload);
2154
2155 if (index >= size)
2156 mlxsw_reg_pagt_size_set(payload, index + 1);
2157 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2158}
2159
2160
2161
2162
2163
2164
2165#define MLXSW_REG_PTAR_ID 0x3006
2166#define MLXSW_REG_PTAR_BASE_LEN 0x20
2167#define MLXSW_REG_PTAR_KEY_ID_LEN 1
2168#define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2169#define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2170 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2171
2172MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2173
2174enum mlxsw_reg_ptar_op {
2175
2176 MLXSW_REG_PTAR_OP_ALLOC,
2177
2178 MLXSW_REG_PTAR_OP_RESIZE,
2179
2180 MLXSW_REG_PTAR_OP_FREE,
2181
2182 MLXSW_REG_PTAR_OP_TEST,
2183};
2184
2185
2186
2187
2188MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2189
2190
2191
2192
2193
2194
2195MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2196
2197enum mlxsw_reg_ptar_key_type {
2198 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50,
2199 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51,
2200};
2201
2202
2203
2204
2205
2206MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2217
2218
2219
2220
2221
2222
2223MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2224
2225
2226
2227
2228
2229
2230
2231MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2232 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2243 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2244
2245static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2246 enum mlxsw_reg_ptar_key_type key_type,
2247 u16 region_size, u16 region_id,
2248 const char *tcam_region_info)
2249{
2250 MLXSW_REG_ZERO(ptar, payload);
2251 mlxsw_reg_ptar_op_set(payload, op);
2252 mlxsw_reg_ptar_action_set_type_set(payload, 2);
2253 mlxsw_reg_ptar_key_type_set(payload, key_type);
2254 mlxsw_reg_ptar_region_size_set(payload, region_size);
2255 mlxsw_reg_ptar_region_id_set(payload, region_id);
2256 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2257}
2258
2259static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2260 u16 key_id)
2261{
2262 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2263}
2264
2265static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2266{
2267 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2268}
2269
2270
2271
2272
2273
2274#define MLXSW_REG_PPBS_ID 0x300C
2275#define MLXSW_REG_PPBS_LEN 0x14
2276
2277MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2278
2279
2280
2281
2282
2283
2284MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2285
2286
2287
2288
2289
2290MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2291
2292static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2293 u16 system_port)
2294{
2295 MLXSW_REG_ZERO(ppbs, payload);
2296 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2297 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2298}
2299
2300
2301
2302
2303
2304#define MLXSW_REG_PRCR_ID 0x300D
2305#define MLXSW_REG_PRCR_LEN 0x40
2306
2307MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2308
2309enum mlxsw_reg_prcr_op {
2310
2311
2312
2313
2314 MLXSW_REG_PRCR_OP_MOVE,
2315
2316
2317
2318
2319 MLXSW_REG_PRCR_OP_COPY,
2320};
2321
2322
2323
2324
2325MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2326
2327
2328
2329
2330
2331MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2332
2333
2334
2335
2336
2337MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2338
2339
2340
2341
2342
2343MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2344 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2345
2346
2347
2348
2349
2350MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2351
2352
2353
2354
2355
2356MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2357 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2358
2359static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2360 const char *src_tcam_region_info,
2361 u16 src_offset,
2362 const char *dest_tcam_region_info,
2363 u16 dest_offset, u16 size)
2364{
2365 MLXSW_REG_ZERO(prcr, payload);
2366 mlxsw_reg_prcr_op_set(payload, op);
2367 mlxsw_reg_prcr_offset_set(payload, src_offset);
2368 mlxsw_reg_prcr_size_set(payload, size);
2369 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2370 src_tcam_region_info);
2371 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2372 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2373 dest_tcam_region_info);
2374}
2375
2376
2377
2378
2379
2380
2381#define MLXSW_REG_PEFA_ID 0x300F
2382#define MLXSW_REG_PEFA_LEN 0xB0
2383
2384MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2385
2386
2387
2388
2389
2390MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2391
2392
2393
2394
2395
2396
2397
2398
2399MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2400
2401
2402
2403
2404
2405
2406
2407MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2408
2409#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2410
2411
2412
2413
2414
2415
2416MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2417
2418static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2419 const char *flex_action_set)
2420{
2421 MLXSW_REG_ZERO(pefa, payload);
2422 mlxsw_reg_pefa_index_set(payload, index);
2423 mlxsw_reg_pefa_ca_set(payload, ca);
2424 if (flex_action_set)
2425 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2426 flex_action_set);
2427}
2428
2429static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2430{
2431 *p_a = mlxsw_reg_pefa_a_get(payload);
2432}
2433
2434
2435
2436
2437
2438
2439
2440
2441#define MLXSW_REG_PTCE2_ID 0x3017
2442#define MLXSW_REG_PTCE2_LEN 0x1D8
2443
2444MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2445
2446
2447
2448
2449
2450MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2451
2452
2453
2454
2455
2456
2457MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2458
2459enum mlxsw_reg_ptce2_op {
2460
2461 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2462
2463
2464
2465 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2466
2467
2468
2469
2470 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2471
2472 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2473
2474 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2475};
2476
2477
2478
2479
2480MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2481
2482
2483
2484
2485MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2486
2487
2488
2489
2490
2491
2492
2493
2494MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2495
2496
2497
2498
2499
2500MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2501 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2502
2503#define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2504
2505
2506
2507
2508
2509MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2510 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2511
2512
2513
2514
2515
2516
2517
2518MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2519 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2520
2521
2522
2523
2524
2525MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2526 MLXSW_REG_FLEX_ACTION_SET_LEN);
2527
2528static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2529 enum mlxsw_reg_ptce2_op op,
2530 const char *tcam_region_info,
2531 u16 offset, u32 priority)
2532{
2533 MLXSW_REG_ZERO(ptce2, payload);
2534 mlxsw_reg_ptce2_v_set(payload, valid);
2535 mlxsw_reg_ptce2_op_set(payload, op);
2536 mlxsw_reg_ptce2_offset_set(payload, offset);
2537 mlxsw_reg_ptce2_priority_set(payload, priority);
2538 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2539}
2540
2541
2542
2543
2544
2545#define MLXSW_REG_PERPT_ID 0x3021
2546#define MLXSW_REG_PERPT_LEN 0x80
2547
2548MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2549
2550
2551
2552
2553
2554
2555MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2556
2557
2558
2559
2560
2561
2562MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2563
2564enum mlxsw_reg_perpt_key_size {
2565 MLXSW_REG_PERPT_KEY_SIZE_2KB,
2566 MLXSW_REG_PERPT_KEY_SIZE_4KB,
2567 MLXSW_REG_PERPT_KEY_SIZE_8KB,
2568 MLXSW_REG_PERPT_KEY_SIZE_12KB,
2569};
2570
2571
2572
2573
2574MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2575
2576
2577
2578
2579
2580
2581
2582
2583MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2584
2585
2586
2587
2588
2589MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2590
2591
2592
2593
2594
2595
2596MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2597
2598
2599
2600
2601
2602
2603MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2604
2605
2606
2607
2608
2609MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2610
2611
2612
2613
2614
2615MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2616
2617
2618
2619
2620
2621
2622
2623MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2624
2625static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2626 unsigned long *erp_vector,
2627 unsigned long size)
2628{
2629 unsigned long bit;
2630
2631 for_each_set_bit(bit, erp_vector, size)
2632 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2633}
2634
2635static inline void
2636mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2637 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2638 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2639 char *mask)
2640{
2641 MLXSW_REG_ZERO(perpt, payload);
2642 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2643 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2644 mlxsw_reg_perpt_key_size_set(payload, key_size);
2645 mlxsw_reg_perpt_bf_bypass_set(payload, true);
2646 mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2647 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2648 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2649 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2650 mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2651}
2652
2653
2654
2655
2656
2657
2658#define MLXSW_REG_PERAR_ID 0x3026
2659#define MLXSW_REG_PERAR_LEN 0x08
2660
2661MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2662
2663
2664
2665
2666
2667
2668MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2669
2670static inline unsigned int
2671mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2672{
2673 return DIV_ROUND_UP(block_num, 4);
2674}
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2685
2686static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2687 u16 hw_region)
2688{
2689 MLXSW_REG_ZERO(perar, payload);
2690 mlxsw_reg_perar_region_id_set(payload, region_id);
2691 mlxsw_reg_perar_hw_region_set(payload, hw_region);
2692}
2693
2694
2695
2696
2697
2698
2699#define MLXSW_REG_PTCE3_ID 0x3027
2700#define MLXSW_REG_PTCE3_LEN 0xF0
2701
2702MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2703
2704
2705
2706
2707
2708MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2709
2710enum mlxsw_reg_ptce3_op {
2711
2712
2713
2714
2715
2716 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2717
2718 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2719
2720 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2721};
2722
2723
2724
2725
2726MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2727
2728
2729
2730
2731
2732
2733
2734MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2735
2736
2737
2738
2739
2740MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2741 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2742
2743
2744
2745
2746
2747
2748MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2749 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2750
2751
2752
2753
2754
2755MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2756
2757
2758
2759
2760
2761
2762MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2774
2775
2776
2777
2778
2779
2780MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2793
2794
2795
2796
2797
2798
2799
2800MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2824
2825
2826
2827
2828
2829
2830MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2831
2832static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2833 enum mlxsw_reg_ptce3_op op,
2834 u32 priority,
2835 const char *tcam_region_info,
2836 const char *key, u8 erp_id,
2837 bool large_exists, u32 lkey_id,
2838 u32 action_pointer)
2839{
2840 MLXSW_REG_ZERO(ptce3, payload);
2841 mlxsw_reg_ptce3_v_set(payload, valid);
2842 mlxsw_reg_ptce3_op_set(payload, op);
2843 mlxsw_reg_ptce3_priority_set(payload, priority);
2844 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2845 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2846 mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2847 mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2848 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2849 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2850}
2851
2852
2853
2854
2855
2856
2857#define MLXSW_REG_PERCR_ID 0x302A
2858#define MLXSW_REG_PERCR_LEN 0x80
2859
2860MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2861
2862
2863
2864
2865
2866
2867MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2868
2869
2870
2871
2872
2873MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2874
2875
2876
2877
2878
2879MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2880
2881
2882
2883
2884
2885
2886
2887
2888MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
2889
2890
2891
2892
2893
2894
2895
2896MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
2897
2898static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
2899{
2900 MLXSW_REG_ZERO(percr, payload);
2901 mlxsw_reg_percr_region_id_set(payload, region_id);
2902 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
2903 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
2904 mlxsw_reg_percr_bf_bypass_set(payload, true);
2905}
2906
2907
2908
2909
2910
2911
2912#define MLXSW_REG_PERERP_ID 0x302B
2913#define MLXSW_REG_PERERP_LEN 0x1C
2914
2915MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
2916
2917
2918
2919
2920
2921
2922MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
2923
2924
2925
2926
2927
2928MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
2929
2930
2931
2932
2933
2934MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
2935
2936
2937
2938
2939
2940
2941MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
2942
2943
2944
2945
2946
2947
2948
2949
2950MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
2951
2952
2953
2954
2955
2956
2957
2958
2959MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
2960
2961
2962
2963
2964
2965
2966
2967MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
2968
2969static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
2970 unsigned long *erp_vector,
2971 unsigned long size)
2972{
2973 unsigned long bit;
2974
2975 for_each_set_bit(bit, erp_vector, size)
2976 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
2977}
2978
2979static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
2980 bool ctcam_le, bool erpt_pointer_valid,
2981 u8 erpt_bank_pointer, u8 erpt_pointer,
2982 u8 master_rp_id)
2983{
2984 MLXSW_REG_ZERO(pererp, payload);
2985 mlxsw_reg_pererp_region_id_set(payload, region_id);
2986 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
2987 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
2988 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
2989 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
2990 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
2991}
2992
2993
2994
2995
2996
2997
2998
2999#define MLXSW_REG_IEDR_ID 0x3804
3000#define MLXSW_REG_IEDR_BASE_LEN 0x10
3001#define MLXSW_REG_IEDR_REC_LEN 0x8
3002#define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3003#define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
3004 MLXSW_REG_IEDR_REC_LEN * \
3005 MLXSW_REG_IEDR_REC_MAX_COUNT)
3006
3007MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3008
3009
3010
3011
3012
3013MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3014
3015
3016
3017
3018
3019MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3020 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3021
3022
3023
3024
3025
3026MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3027 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3028
3029
3030
3031
3032
3033MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3034 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3035
3036static inline void mlxsw_reg_iedr_pack(char *payload)
3037{
3038 MLXSW_REG_ZERO(iedr, payload);
3039}
3040
3041static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3042 u8 rec_type, u16 rec_size,
3043 u32 rec_index_start)
3044{
3045 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3046
3047 if (rec_index >= num_rec)
3048 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3049 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3050 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3051 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3052}
3053
3054
3055
3056
3057
3058
3059#define MLXSW_REG_QPTS_ID 0x4002
3060#define MLXSW_REG_QPTS_LEN 0x8
3061
3062MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3063
3064
3065
3066
3067
3068
3069
3070MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3071
3072enum mlxsw_reg_qpts_trust_state {
3073 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3074 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2,
3075};
3076
3077
3078
3079
3080
3081MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3082
3083static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3084 enum mlxsw_reg_qpts_trust_state ts)
3085{
3086 MLXSW_REG_ZERO(qpts, payload);
3087
3088 mlxsw_reg_qpts_local_port_set(payload, local_port);
3089 mlxsw_reg_qpts_trust_state_set(payload, ts);
3090}
3091
3092
3093
3094
3095
3096
3097#define MLXSW_REG_QPCR_ID 0x4004
3098#define MLXSW_REG_QPCR_LEN 0x28
3099
3100MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3101
3102enum mlxsw_reg_qpcr_g {
3103 MLXSW_REG_QPCR_G_GLOBAL = 2,
3104 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3105};
3106
3107
3108
3109
3110
3111MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3112
3113
3114
3115
3116
3117MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3118
3119
3120
3121
3122
3123
3124MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3125
3126
3127
3128
3129
3130
3131
3132MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3133
3134enum mlxsw_reg_qpcr_ir_units {
3135 MLXSW_REG_QPCR_IR_UNITS_M,
3136 MLXSW_REG_QPCR_IR_UNITS_K,
3137};
3138
3139
3140
3141
3142
3143
3144
3145MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3146
3147enum mlxsw_reg_qpcr_rate_type {
3148 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3149 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3150};
3151
3152
3153
3154
3155
3156
3157
3158MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3172
3173
3174
3175
3176
3177
3178
3179
3180MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3191
3192#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3193
3194
3195
3196
3197
3198MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3199
3200enum mlxsw_reg_qpcr_action {
3201
3202 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3203
3204
3205
3206 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3207};
3208
3209
3210
3211
3212
3213
3214MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3215
3216static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3217 enum mlxsw_reg_qpcr_ir_units ir_units,
3218 bool bytes, u32 cir, u16 cbs)
3219{
3220 MLXSW_REG_ZERO(qpcr, payload);
3221 mlxsw_reg_qpcr_pid_set(payload, pid);
3222 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3223 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3224 mlxsw_reg_qpcr_violate_action_set(payload,
3225 MLXSW_REG_QPCR_ACTION_DISCARD);
3226 mlxsw_reg_qpcr_cir_set(payload, cir);
3227 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3228 mlxsw_reg_qpcr_bytes_set(payload, bytes);
3229 mlxsw_reg_qpcr_cbs_set(payload, cbs);
3230}
3231
3232
3233
3234
3235
3236
3237#define MLXSW_REG_QTCT_ID 0x400A
3238#define MLXSW_REG_QTCT_LEN 0x08
3239
3240MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3241
3242
3243
3244
3245
3246
3247
3248MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3249
3250
3251
3252
3253
3254
3255MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3256
3257
3258
3259
3260
3261MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3272
3273static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3274 u8 switch_prio, u8 tclass)
3275{
3276 MLXSW_REG_ZERO(qtct, payload);
3277 mlxsw_reg_qtct_local_port_set(payload, local_port);
3278 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3279 mlxsw_reg_qtct_tclass_set(payload, tclass);
3280}
3281
3282
3283
3284
3285
3286#define MLXSW_REG_QEEC_ID 0x400D
3287#define MLXSW_REG_QEEC_LEN 0x20
3288
3289MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3290
3291
3292
3293
3294
3295
3296
3297MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3298
3299enum mlxsw_reg_qeec_hr {
3300 MLXSW_REG_QEEC_HIERARCY_PORT,
3301 MLXSW_REG_QEEC_HIERARCY_GROUP,
3302 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3303 MLXSW_REG_QEEC_HIERARCY_TC,
3304};
3305
3306
3307
3308
3309
3310
3311
3312
3313MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3314
3315
3316
3317
3318
3319MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3320
3321
3322
3323
3324
3325
3326
3327MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3328
3329
3330
3331
3332
3333
3334
3335
3336MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3337
3338enum {
3339 MLXSW_REG_QEEC_BYTES_MODE,
3340 MLXSW_REG_QEEC_PACKETS_MODE,
3341};
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3353
3354
3355#define MLXSW_REG_QEEC_MIS_MIN 200000
3356
3357
3358
3359
3360
3361
3362
3363MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3364
3365
3366
3367
3368
3369
3370
3371
3372MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3373
3374
3375#define MLXSW_REG_QEEC_MAS_DIS 200000000
3376
3377
3378
3379
3380
3381
3382
3383MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3384
3385
3386
3387
3388
3389
3390
3391
3392MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3393
3394
3395
3396
3397
3398
3399
3400
3401MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3412
3413static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3414 enum mlxsw_reg_qeec_hr hr, u8 index,
3415 u8 next_index)
3416{
3417 MLXSW_REG_ZERO(qeec, payload);
3418 mlxsw_reg_qeec_local_port_set(payload, local_port);
3419 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3420 mlxsw_reg_qeec_element_index_set(payload, index);
3421 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3422}
3423
3424
3425
3426
3427
3428#define MLXSW_REG_QRWE_ID 0x400F
3429#define MLXSW_REG_QRWE_LEN 0x08
3430
3431MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3432
3433
3434
3435
3436
3437
3438
3439MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3440
3441
3442
3443
3444
3445MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3446
3447
3448
3449
3450
3451MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3452
3453static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3454 bool rewrite_pcp, bool rewrite_dscp)
3455{
3456 MLXSW_REG_ZERO(qrwe, payload);
3457 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3458 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3459 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3460}
3461
3462
3463
3464
3465
3466#define MLXSW_REG_QPDSM_ID 0x4011
3467#define MLXSW_REG_QPDSM_BASE_LEN 0x04
3468#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4
3469#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3470#define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
3471 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
3472 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3473
3474MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3475
3476
3477
3478
3479
3480MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3481
3482
3483
3484
3485
3486MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3487 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3488 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3489
3490
3491
3492
3493
3494
3495MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3496 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3497 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3498
3499
3500
3501
3502
3503MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3504 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3505 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3506
3507
3508
3509
3510
3511
3512MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3513 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3514 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3515
3516
3517
3518
3519
3520MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3521 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3522 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3523
3524
3525
3526
3527
3528
3529MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3530 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3531 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3532
3533static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3534{
3535 MLXSW_REG_ZERO(qpdsm, payload);
3536 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3537}
3538
3539static inline void
3540mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3541{
3542 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3543 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3544 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3545 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3546 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3547 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3548}
3549
3550
3551
3552
3553
3554
3555#define MLXSW_REG_QPDPM_ID 0x4013
3556#define MLXSW_REG_QPDPM_BASE_LEN 0x4
3557#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2
3558#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3559#define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
3560 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
3561 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3562
3563MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3564
3565
3566
3567
3568
3569MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3570
3571
3572
3573
3574
3575
3576
3577MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3578 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3579
3580
3581
3582
3583
3584MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3585 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3586 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3587
3588static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3589{
3590 MLXSW_REG_ZERO(qpdpm, payload);
3591 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3592}
3593
3594static inline void
3595mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3596{
3597 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3598 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3599}
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610#define MLXSW_REG_QTCTM_ID 0x401A
3611#define MLXSW_REG_QTCTM_LEN 0x08
3612
3613MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3614
3615
3616
3617
3618
3619
3620MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3621
3622
3623
3624
3625
3626
3627MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3628
3629static inline void
3630mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3631{
3632 MLXSW_REG_ZERO(qtctm, payload);
3633 mlxsw_reg_qtctm_local_port_set(payload, local_port);
3634 mlxsw_reg_qtctm_mc_set(payload, mc);
3635}
3636
3637
3638
3639
3640
3641#define MLXSW_REG_PMLP_ID 0x5002
3642#define MLXSW_REG_PMLP_LEN 0x40
3643
3644MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3645
3646
3647
3648
3649
3650
3651MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3652
3653
3654
3655
3656
3657MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3658
3659
3660
3661
3662
3663
3664
3665
3666MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3667
3668
3669
3670
3671
3672MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3673
3674
3675
3676
3677
3678MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3679
3680
3681
3682
3683
3684
3685MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3686
3687static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3688{
3689 MLXSW_REG_ZERO(pmlp, payload);
3690 mlxsw_reg_pmlp_local_port_set(payload, local_port);
3691}
3692
3693
3694
3695
3696
3697#define MLXSW_REG_PMTU_ID 0x5003
3698#define MLXSW_REG_PMTU_LEN 0x10
3699
3700MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
3701
3702
3703
3704
3705
3706MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
3707
3708
3709
3710
3711
3712
3713
3714
3715MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
3716
3717
3718
3719
3720
3721
3722
3723MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
3724
3725
3726
3727
3728
3729
3730
3731
3732MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
3733
3734static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
3735 u16 new_mtu)
3736{
3737 MLXSW_REG_ZERO(pmtu, payload);
3738 mlxsw_reg_pmtu_local_port_set(payload, local_port);
3739 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
3740 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
3741 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
3742}
3743
3744
3745
3746
3747
3748
3749
3750
3751#define MLXSW_REG_PTYS_ID 0x5004
3752#define MLXSW_REG_PTYS_LEN 0x40
3753
3754MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
3755
3756
3757
3758
3759
3760
3761
3762MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
3763
3764
3765
3766
3767
3768MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
3769
3770#define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
3771#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
3772
3773
3774
3775
3776
3777
3778
3779
3780MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
3781
3782enum {
3783 MLXSW_REG_PTYS_AN_STATUS_NA,
3784 MLXSW_REG_PTYS_AN_STATUS_OK,
3785 MLXSW_REG_PTYS_AN_STATUS_FAIL,
3786};
3787
3788
3789
3790
3791
3792MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
3793
3794#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
3795#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
3796#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
3797#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
3798#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
3799#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
3800#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
3801#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
3802#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
3803#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
3804#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
3805#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
3806#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
3807#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
3808#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
3809#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
3810#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
3811#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
3812#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
3813#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
3814#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
3815#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
3816#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
3817#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
3818#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
3819#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
3820#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
3821#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
3822
3823
3824
3825
3826
3827MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
3828
3829
3830
3831
3832
3833MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
3834
3835#define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
3836#define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
3837#define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
3838#define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
3839#define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
3840#define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
3841
3842
3843
3844
3845
3846MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
3847
3848
3849
3850
3851
3852MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
3853
3854
3855
3856
3857
3858MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
3859
3860
3861
3862
3863
3864MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
3865
3866
3867
3868
3869
3870MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
3871
3872
3873
3874
3875
3876MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
3877
3878
3879
3880
3881
3882MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
3883
3884
3885
3886
3887
3888
3889MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32);
3890
3891static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
3892 u32 proto_admin, bool autoneg)
3893{
3894 MLXSW_REG_ZERO(ptys, payload);
3895 mlxsw_reg_ptys_local_port_set(payload, local_port);
3896 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
3897 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
3898 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
3899}
3900
3901static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
3902 u32 *p_eth_proto_cap,
3903 u32 *p_eth_proto_adm,
3904 u32 *p_eth_proto_oper)
3905{
3906 if (p_eth_proto_cap)
3907 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
3908 if (p_eth_proto_adm)
3909 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
3910 if (p_eth_proto_oper)
3911 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
3912}
3913
3914static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
3915 u16 proto_admin, u16 link_width)
3916{
3917 MLXSW_REG_ZERO(ptys, payload);
3918 mlxsw_reg_ptys_local_port_set(payload, local_port);
3919 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
3920 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
3921 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
3922}
3923
3924static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
3925 u16 *p_ib_link_width_cap,
3926 u16 *p_ib_proto_oper,
3927 u16 *p_ib_link_width_oper)
3928{
3929 if (p_ib_proto_cap)
3930 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
3931 if (p_ib_link_width_cap)
3932 *p_ib_link_width_cap =
3933 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
3934 if (p_ib_proto_oper)
3935 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
3936 if (p_ib_link_width_oper)
3937 *p_ib_link_width_oper =
3938 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
3939}
3940
3941
3942
3943
3944
3945#define MLXSW_REG_PPAD_ID 0x5005
3946#define MLXSW_REG_PPAD_LEN 0x10
3947
3948MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
3949
3950
3951
3952
3953
3954
3955
3956MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
3957
3958
3959
3960
3961
3962MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
3963
3964
3965
3966
3967
3968
3969MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
3970
3971static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
3972 u8 local_port)
3973{
3974 MLXSW_REG_ZERO(ppad, payload);
3975 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
3976 mlxsw_reg_ppad_local_port_set(payload, local_port);
3977}
3978
3979
3980
3981
3982
3983#define MLXSW_REG_PAOS_ID 0x5006
3984#define MLXSW_REG_PAOS_LEN 0x10
3985
3986MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
3987
3988
3989
3990
3991
3992
3993
3994
3995MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
3996
3997
3998
3999
4000
4001MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4023
4024
4025
4026
4027
4028MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4029
4030
4031
4032
4033
4034
4035MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4036
4037
4038
4039
4040
4041
4042
4043
4044MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4045
4046static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4047 enum mlxsw_port_admin_status status)
4048{
4049 MLXSW_REG_ZERO(paos, payload);
4050 mlxsw_reg_paos_swid_set(payload, 0);
4051 mlxsw_reg_paos_local_port_set(payload, local_port);
4052 mlxsw_reg_paos_admin_status_set(payload, status);
4053 mlxsw_reg_paos_oper_status_set(payload, 0);
4054 mlxsw_reg_paos_ase_set(payload, 1);
4055 mlxsw_reg_paos_ee_set(payload, 1);
4056 mlxsw_reg_paos_e_set(payload, 1);
4057}
4058
4059
4060
4061
4062
4063#define MLXSW_REG_PFCC_ID 0x5007
4064#define MLXSW_REG_PFCC_LEN 0x20
4065
4066MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4067
4068
4069
4070
4071
4072MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4073
4074
4075
4076
4077
4078
4079
4080MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4081
4082
4083
4084
4085
4086
4087
4088
4089MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4090
4091
4092
4093
4094
4095
4096
4097
4098MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4111
4112
4113
4114
4115
4116
4117MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4118
4119
4120
4121
4122
4123
4124MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4125
4126
4127
4128
4129
4130
4131
4132MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4133
4134
4135
4136
4137
4138
4139
4140MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4153
4154
4155
4156
4157
4158
4159
4160MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4161
4162
4163
4164
4165
4166
4167
4168MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4169
4170
4171
4172
4173
4174
4175
4176
4177MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4178
4179#define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4180
4181static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4182{
4183 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4184 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4185 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4186 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4187}
4188
4189static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4190{
4191 MLXSW_REG_ZERO(pfcc, payload);
4192 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4193}
4194
4195
4196
4197
4198
4199#define MLXSW_REG_PPCNT_ID 0x5008
4200#define MLXSW_REG_PPCNT_LEN 0x100
4201#define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4202
4203MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4215
4216
4217
4218
4219
4220
4221
4222MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4223
4224
4225
4226
4227
4228
4229
4230MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4231
4232enum mlxsw_reg_ppcnt_grp {
4233 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4234 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4235 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4236 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4237 MLXSW_REG_PPCNT_TC_CNT = 0x11,
4238 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4239};
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4258
4259
4260
4261
4262
4263
4264
4265MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4276
4277
4278
4279
4280
4281
4282MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4283 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4284
4285
4286
4287
4288MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4289 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4290
4291
4292
4293
4294MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4295 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4296
4297
4298
4299
4300MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4301 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4302
4303
4304
4305
4306MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4307 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4308
4309
4310
4311
4312MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4313 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4314
4315
4316
4317
4318MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4319 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4320
4321
4322
4323
4324MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4325 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4326
4327
4328
4329
4330MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4331 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4332
4333
4334
4335
4336MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4337 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4338
4339
4340
4341
4342MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4343 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4344
4345
4346
4347
4348MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4349 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4350
4351
4352
4353
4354MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4355 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4356
4357
4358
4359
4360MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4361 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4362
4363
4364
4365
4366MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4367 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4368
4369
4370
4371
4372MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4373 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4374
4375
4376
4377
4378MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4379 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4380
4381
4382
4383
4384MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4385 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4386
4387
4388
4389
4390MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4391 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4392
4393
4394
4395
4396
4397
4398MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4399 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4400
4401
4402
4403
4404MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4405 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4406
4407
4408
4409
4410MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4411 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4412
4413
4414
4415
4416MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4417 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4418
4419
4420
4421
4422MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4423 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4424
4425
4426
4427
4428MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4429 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4430
4431
4432
4433
4434MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4435 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4436
4437
4438
4439
4440MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4441 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4442
4443
4444
4445
4446MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4447 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4448
4449
4450
4451
4452MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4453 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4454
4455
4456
4457
4458
4459
4460MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4461 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4462
4463
4464
4465
4466
4467
4468MLXSW_ITEM64(reg, ppcnt, rx_octets,
4469 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4470
4471
4472
4473
4474MLXSW_ITEM64(reg, ppcnt, rx_frames,
4475 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4476
4477
4478
4479
4480MLXSW_ITEM64(reg, ppcnt, tx_octets,
4481 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4482
4483
4484
4485
4486MLXSW_ITEM64(reg, ppcnt, tx_frames,
4487 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4488
4489
4490
4491
4492MLXSW_ITEM64(reg, ppcnt, rx_pause,
4493 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4494
4495
4496
4497
4498MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
4499 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4500
4501
4502
4503
4504MLXSW_ITEM64(reg, ppcnt, tx_pause,
4505 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4506
4507
4508
4509
4510MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
4511 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4512
4513
4514
4515
4516MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
4517 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
4528 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4529
4530
4531
4532
4533
4534
4535MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
4536 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4537
4538
4539
4540
4541
4542
4543MLXSW_ITEM64(reg, ppcnt, wred_discard,
4544 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4545
4546static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
4547 enum mlxsw_reg_ppcnt_grp grp,
4548 u8 prio_tc)
4549{
4550 MLXSW_REG_ZERO(ppcnt, payload);
4551 mlxsw_reg_ppcnt_swid_set(payload, 0);
4552 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
4553 mlxsw_reg_ppcnt_pnat_set(payload, 0);
4554 mlxsw_reg_ppcnt_grp_set(payload, grp);
4555 mlxsw_reg_ppcnt_clr_set(payload, 0);
4556 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
4557}
4558
4559
4560
4561
4562
4563#define MLXSW_REG_PLIB_ID 0x500A
4564#define MLXSW_REG_PLIB_LEN 0x10
4565
4566MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
4567
4568
4569
4570
4571
4572MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
4573
4574
4575
4576
4577
4578MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
4579
4580
4581
4582
4583
4584#define MLXSW_REG_PPTB_ID 0x500B
4585#define MLXSW_REG_PPTB_LEN 0x10
4586
4587MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
4588
4589enum {
4590 MLXSW_REG_PPTB_MM_UM,
4591 MLXSW_REG_PPTB_MM_UNICAST,
4592 MLXSW_REG_PPTB_MM_MULTICAST,
4593};
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
4605
4606
4607
4608
4609
4610MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
4611
4612
4613
4614
4615
4616MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
4617
4618
4619
4620
4621
4622
4623MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
4624
4625
4626
4627
4628
4629
4630MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
4631
4632
4633
4634
4635
4636
4637MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
4638
4639
4640
4641
4642
4643
4644
4645
4646MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
4647
4648
4649
4650
4651
4652
4653MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
4654
4655#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
4656
4657static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
4658{
4659 MLXSW_REG_ZERO(pptb, payload);
4660 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
4661 mlxsw_reg_pptb_local_port_set(payload, local_port);
4662 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
4663 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
4664}
4665
4666static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
4667 u8 buff)
4668{
4669 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
4670 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
4671}
4672
4673
4674
4675
4676
4677
4678#define MLXSW_REG_PBMC_ID 0x500C
4679#define MLXSW_REG_PBMC_LEN 0x6C
4680
4681MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
4682
4683
4684
4685
4686
4687MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
4688
4689
4690
4691
4692
4693
4694MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
4695
4696
4697
4698
4699
4700
4701
4702MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
4703
4704#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
4705
4706
4707
4708
4709
4710
4711
4712MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
4713
4714
4715
4716
4717
4718
4719
4720
4721MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
4722
4723
4724
4725
4726
4727
4728MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
4740 0x08, 0x04, false);
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
4752 0x08, 0x04, false);
4753
4754static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
4755 u16 xoff_timer_value, u16 xoff_refresh)
4756{
4757 MLXSW_REG_ZERO(pbmc, payload);
4758 mlxsw_reg_pbmc_local_port_set(payload, local_port);
4759 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
4760 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
4761}
4762
4763static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
4764 int buf_index,
4765 u16 size)
4766{
4767 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
4768 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
4769 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
4770}
4771
4772static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
4773 int buf_index, u16 size,
4774 u16 threshold)
4775{
4776 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
4777 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
4778 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
4779 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
4780 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
4781}
4782
4783
4784
4785
4786
4787
4788#define MLXSW_REG_PSPA_ID 0x500D
4789#define MLXSW_REG_PSPA_LEN 0x8
4790
4791MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
4792
4793
4794
4795
4796
4797MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
4798
4799
4800
4801
4802
4803MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
4804
4805
4806
4807
4808
4809
4810MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
4811
4812static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
4813{
4814 MLXSW_REG_ZERO(pspa, payload);
4815 mlxsw_reg_pspa_swid_set(payload, swid);
4816 mlxsw_reg_pspa_local_port_set(payload, local_port);
4817 mlxsw_reg_pspa_sub_port_set(payload, 0);
4818}
4819
4820
4821
4822
4823
4824#define MLXSW_REG_HTGT_ID 0x7002
4825#define MLXSW_REG_HTGT_LEN 0x20
4826
4827MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
4828
4829
4830
4831
4832
4833MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
4834
4835#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0
4836
4837
4838
4839
4840
4841MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
4842
4843enum mlxsw_reg_htgt_trap_group {
4844 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4845 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
4846 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
4847 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
4848 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
4849 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
4850 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
4851 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
4852 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
4853 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
4854 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
4855 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
4856 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
4857 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
4858 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
4859 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
4860 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
4861 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
4862 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
4863 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
4864 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
4865};
4866
4867
4868
4869
4870
4871
4872
4873MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
4874
4875enum {
4876 MLXSW_REG_HTGT_POLICER_DISABLE,
4877 MLXSW_REG_HTGT_POLICER_ENABLE,
4878};
4879
4880
4881
4882
4883
4884MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
4885
4886#define MLXSW_REG_HTGT_INVALID_POLICER 0xff
4887
4888
4889
4890
4891
4892MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
4893
4894#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
4906
4907
4908
4909
4910
4911MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
4912
4913#define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
4927
4928#define MLXSW_REG_HTGT_DEFAULT_TC 7
4929
4930
4931
4932
4933
4934MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
4935
4936enum mlxsw_reg_htgt_local_path_rdq {
4937 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
4938 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
4939 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
4940 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
4941};
4942
4943
4944
4945
4946MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
4947
4948static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
4949 u8 priority, u8 tc)
4950{
4951 MLXSW_REG_ZERO(htgt, payload);
4952
4953 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
4954 mlxsw_reg_htgt_pide_set(payload,
4955 MLXSW_REG_HTGT_POLICER_DISABLE);
4956 } else {
4957 mlxsw_reg_htgt_pide_set(payload,
4958 MLXSW_REG_HTGT_POLICER_ENABLE);
4959 mlxsw_reg_htgt_pid_set(payload, policer_id);
4960 }
4961
4962 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
4963 mlxsw_reg_htgt_trap_group_set(payload, group);
4964 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
4965 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
4966 mlxsw_reg_htgt_priority_set(payload, priority);
4967 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
4968 mlxsw_reg_htgt_local_path_rdq_set(payload, group);
4969}
4970
4971
4972
4973
4974
4975#define MLXSW_REG_HPKT_ID 0x7003
4976#define MLXSW_REG_HPKT_LEN 0x10
4977
4978MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
4979
4980enum {
4981 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
4982 MLXSW_REG_HPKT_ACK_REQUIRED,
4983};
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
4994
4995enum mlxsw_reg_hpkt_action {
4996 MLXSW_REG_HPKT_ACTION_FORWARD,
4997 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
4998 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
4999 MLXSW_REG_HPKT_ACTION_DISCARD,
5000 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
5001 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
5002};
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
5018
5019
5020
5021
5022
5023MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
5024
5025
5026
5027
5028
5029
5030
5031
5032MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
5033
5034enum {
5035 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
5036 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
5037 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
5038};
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
5049
5050static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
5051 enum mlxsw_reg_htgt_trap_group trap_group,
5052 bool is_ctrl)
5053{
5054 MLXSW_REG_ZERO(hpkt, payload);
5055 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
5056 mlxsw_reg_hpkt_action_set(payload, action);
5057 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
5058 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
5059 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
5060 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
5061 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
5062}
5063
5064
5065
5066
5067
5068#define MLXSW_REG_RGCR_ID 0x8001
5069#define MLXSW_REG_RGCR_LEN 0x28
5070
5071MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5072
5073
5074
5075
5076
5077MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5078
5079
5080
5081
5082
5083MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5084
5085
5086
5087
5088
5089
5090MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5128
5129static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5130 bool ipv6_en)
5131{
5132 MLXSW_REG_ZERO(rgcr, payload);
5133 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5134 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5135}
5136
5137
5138
5139
5140
5141#define MLXSW_REG_RITR_ID 0x8002
5142#define MLXSW_REG_RITR_LEN 0x40
5143
5144MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5145
5146
5147
5148
5149
5150MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5151
5152
5153
5154
5155
5156
5157MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5158
5159
5160
5161
5162
5163
5164MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5165
5166
5167
5168
5169
5170MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5171
5172
5173
5174
5175
5176MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5177
5178enum mlxsw_reg_ritr_if_type {
5179
5180 MLXSW_REG_RITR_VLAN_IF,
5181
5182 MLXSW_REG_RITR_FID_IF,
5183
5184 MLXSW_REG_RITR_SP_IF,
5185
5186 MLXSW_REG_RITR_LOOPBACK_IF,
5187};
5188
5189
5190
5191
5192
5193MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5194
5195enum {
5196 MLXSW_REG_RITR_RIF_CREATE,
5197 MLXSW_REG_RITR_RIF_DEL,
5198};
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5210
5211
5212
5213
5214
5215MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5216
5217
5218
5219
5220
5221
5222
5223
5224MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5225
5226
5227
5228
5229
5230
5231
5232
5233MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5234
5235
5236
5237
5238
5239
5240
5241MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5242
5243
5244
5245
5246
5247
5248
5249MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5250
5251
5252
5253
5254
5255
5256
5257
5258MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5259
5260
5261
5262
5263
5264MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5265
5266
5267
5268
5269
5270MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5271
5272
5273
5274
5275
5276MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5277
5278
5279
5280
5281
5282
5283MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5284
5285
5286
5287
5288
5289
5290MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5291
5292
5293
5294
5295
5296
5297MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5298
5299
5300
5301
5302
5303
5304
5305MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5306
5307
5308
5309
5310
5311
5312
5313
5314MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5315
5316static inline void mlxsw_reg_ritr_fid_set(char *payload,
5317 enum mlxsw_reg_ritr_if_type rif_type,
5318 u16 fid)
5319{
5320 if (rif_type == MLXSW_REG_RITR_FID_IF)
5321 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5322 else
5323 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5324}
5325
5326
5327
5328
5329
5330
5331
5332
5333MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
5334
5335
5336
5337
5338
5339
5340MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
5341
5342
5343
5344
5345
5346MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
5347
5348
5349
5350enum mlxsw_reg_ritr_loopback_protocol {
5351
5352 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5353
5354 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
5355};
5356
5357
5358
5359
5360MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
5361
5362enum mlxsw_reg_ritr_loopback_ipip_type {
5363
5364 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
5365
5366 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
5367
5368 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
5369};
5370
5371
5372
5373
5374
5375MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
5376
5377enum mlxsw_reg_ritr_loopback_ipip_options {
5378
5379 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
5380};
5381
5382
5383
5384
5385MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
5386
5387
5388
5389
5390
5391
5392
5393MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
5394
5395
5396
5397
5398
5399MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
5400MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
5401
5402
5403
5404
5405
5406
5407MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
5408
5409
5410enum mlxsw_reg_ritr_counter_set_type {
5411
5412 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
5413
5414
5415
5416
5417
5418
5419 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
5420};
5421
5422
5423
5424
5425
5426MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
5427
5428
5429
5430
5431
5432MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
5433
5434
5435
5436
5437
5438MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
5439
5440
5441
5442
5443
5444MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
5445
5446static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
5447 bool enable, bool egress)
5448{
5449 enum mlxsw_reg_ritr_counter_set_type set_type;
5450
5451 if (enable)
5452 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
5453 else
5454 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
5455 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
5456
5457 if (egress)
5458 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
5459 else
5460 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
5461}
5462
5463static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
5464{
5465 MLXSW_REG_ZERO(ritr, payload);
5466 mlxsw_reg_ritr_rif_set(payload, rif);
5467}
5468
5469static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
5470 u16 system_port, u16 vid)
5471{
5472 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
5473 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
5474 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
5475}
5476
5477static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
5478 enum mlxsw_reg_ritr_if_type type,
5479 u16 rif, u16 vr_id, u16 mtu)
5480{
5481 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
5482
5483 MLXSW_REG_ZERO(ritr, payload);
5484 mlxsw_reg_ritr_enable_set(payload, enable);
5485 mlxsw_reg_ritr_ipv4_set(payload, 1);
5486 mlxsw_reg_ritr_ipv6_set(payload, 1);
5487 mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
5488 mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
5489 mlxsw_reg_ritr_type_set(payload, type);
5490 mlxsw_reg_ritr_op_set(payload, op);
5491 mlxsw_reg_ritr_rif_set(payload, rif);
5492 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
5493 mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
5494 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
5495 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
5496 mlxsw_reg_ritr_lb_en_set(payload, 1);
5497 mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
5498 mlxsw_reg_ritr_mtu_set(payload, mtu);
5499}
5500
5501static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
5502{
5503 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
5504}
5505
5506static inline void
5507mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
5508 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5509 enum mlxsw_reg_ritr_loopback_ipip_options options,
5510 u16 uvr_id, u32 gre_key)
5511{
5512 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
5513 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
5514 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
5515 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
5516}
5517
5518static inline void
5519mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
5520 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5521 enum mlxsw_reg_ritr_loopback_ipip_options options,
5522 u16 uvr_id, u32 usip, u32 gre_key)
5523{
5524 mlxsw_reg_ritr_loopback_protocol_set(payload,
5525 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
5526 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
5527 uvr_id, gre_key);
5528 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
5529}
5530
5531
5532
5533
5534
5535#define MLXSW_REG_RTAR_ID 0x8004
5536#define MLXSW_REG_RTAR_LEN 0x20
5537
5538MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
5539
5540enum mlxsw_reg_rtar_op {
5541 MLXSW_REG_RTAR_OP_ALLOCATE,
5542 MLXSW_REG_RTAR_OP_RESIZE,
5543 MLXSW_REG_RTAR_OP_DEALLOCATE,
5544};
5545
5546
5547
5548
5549MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
5550
5551enum mlxsw_reg_rtar_key_type {
5552 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
5553 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
5554};
5555
5556
5557
5558
5559
5560MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
5561
5562
5563
5564
5565
5566
5567
5568
5569MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
5570
5571static inline void mlxsw_reg_rtar_pack(char *payload,
5572 enum mlxsw_reg_rtar_op op,
5573 enum mlxsw_reg_rtar_key_type key_type,
5574 u16 region_size)
5575{
5576 MLXSW_REG_ZERO(rtar, payload);
5577 mlxsw_reg_rtar_op_set(payload, op);
5578 mlxsw_reg_rtar_key_type_set(payload, key_type);
5579 mlxsw_reg_rtar_region_size_set(payload, region_size);
5580}
5581
5582
5583
5584
5585
5586
5587#define MLXSW_REG_RATR_ID 0x8008
5588#define MLXSW_REG_RATR_LEN 0x2C
5589
5590MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
5591
5592enum mlxsw_reg_ratr_op {
5593
5594 MLXSW_REG_RATR_OP_QUERY_READ = 0,
5595
5596 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
5597
5598 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
5599
5600
5601
5602
5603
5604
5605 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
5606};
5607
5608
5609
5610
5611
5612
5613
5614MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
5629
5630
5631
5632
5633
5634
5635MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
5636
5637enum mlxsw_reg_ratr_type {
5638
5639 MLXSW_REG_RATR_TYPE_ETHERNET,
5640
5641
5642
5643 MLXSW_REG_RATR_TYPE_IPOIB_UC,
5644
5645
5646
5647
5648 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
5649
5650
5651
5652 MLXSW_REG_RATR_TYPE_IPOIB_MC,
5653
5654
5655
5656 MLXSW_REG_RATR_TYPE_MPLS,
5657
5658
5659
5660 MLXSW_REG_RATR_TYPE_IPIP,
5661};
5662
5663
5664
5665
5666
5667MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
5668
5669
5670
5671
5672
5673
5674
5675
5676MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
5677
5678
5679
5680
5681
5682MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
5683
5684enum mlxsw_reg_ratr_trap_action {
5685 MLXSW_REG_RATR_TRAP_ACTION_NOP,
5686 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
5687 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
5688 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
5689 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
5690};
5691
5692
5693
5694
5695
5696MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
5697
5698
5699
5700
5701
5702MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
5703
5704enum mlxsw_reg_ratr_trap_id {
5705 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
5706 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
5707};
5708
5709
5710
5711
5712
5713
5714
5715MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
5716
5717
5718
5719
5720
5721MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
5722
5723enum mlxsw_reg_ratr_ipip_type {
5724
5725 MLXSW_REG_RATR_IPIP_TYPE_IPV4,
5726
5727 MLXSW_REG_RATR_IPIP_TYPE_IPV6,
5728};
5729
5730
5731
5732
5733
5734
5735MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
5736
5737
5738
5739
5740
5741
5742MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
5743
5744
5745
5746
5747
5748
5749MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
5750
5751enum mlxsw_reg_flow_counter_set_type {
5752
5753 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
5754
5755 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
5756
5757 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
5758};
5759
5760
5761
5762
5763
5764MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
5765
5766
5767
5768
5769
5770MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
5771
5772static inline void
5773mlxsw_reg_ratr_pack(char *payload,
5774 enum mlxsw_reg_ratr_op op, bool valid,
5775 enum mlxsw_reg_ratr_type type,
5776 u32 adjacency_index, u16 egress_rif)
5777{
5778 MLXSW_REG_ZERO(ratr, payload);
5779 mlxsw_reg_ratr_op_set(payload, op);
5780 mlxsw_reg_ratr_v_set(payload, valid);
5781 mlxsw_reg_ratr_type_set(payload, type);
5782 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
5783 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
5784 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
5785}
5786
5787static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
5788 const char *dest_mac)
5789{
5790 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
5791}
5792
5793static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
5794{
5795 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
5796 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
5797}
5798
5799static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
5800 bool counter_enable)
5801{
5802 enum mlxsw_reg_flow_counter_set_type set_type;
5803
5804 if (counter_enable)
5805 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
5806 else
5807 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
5808
5809 mlxsw_reg_ratr_counter_index_set(payload, counter_index);
5810 mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
5811}
5812
5813
5814
5815
5816
5817#define MLXSW_REG_RDPM_ID 0x8009
5818#define MLXSW_REG_RDPM_BASE_LEN 0x00
5819#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
5820#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
5821#define MLXSW_REG_RDPM_LEN 0x40
5822#define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
5823 MLXSW_REG_RDPM_LEN - \
5824 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
5825
5826MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
5827
5828
5829
5830
5831
5832MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
5833 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
5834
5835
5836
5837
5838
5839MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
5840 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
5841
5842static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
5843 u8 prio)
5844{
5845 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
5846 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
5847}
5848
5849
5850
5851
5852
5853#define MLXSW_REG_RICNT_ID 0x800B
5854#define MLXSW_REG_RICNT_LEN 0x100
5855
5856MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
5857
5858
5859
5860
5861
5862MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
5863
5864enum mlxsw_reg_ricnt_counter_set_type {
5865
5866 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
5867
5868
5869
5870
5871
5872
5873 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
5874};
5875
5876
5877
5878
5879
5880MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
5881
5882enum mlxsw_reg_ricnt_opcode {
5883
5884 MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
5885
5886
5887
5888 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
5889};
5890
5891
5892
5893
5894
5895MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
5896
5897
5898
5899
5900
5901MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
5902
5903
5904
5905
5906
5907MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
5908
5909
5910
5911
5912
5913MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
5914
5915
5916
5917
5918
5919
5920MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
5921
5922
5923
5924
5925
5926
5927MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
5928
5929
5930
5931
5932
5933
5934MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
5935
5936
5937
5938
5939
5940MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
5941
5942
5943
5944
5945
5946MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
5947
5948
5949
5950
5951
5952
5953MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
5954
5955
5956
5957
5958
5959
5960MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
5961
5962static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
5963 enum mlxsw_reg_ricnt_opcode op)
5964{
5965 MLXSW_REG_ZERO(ricnt, payload);
5966 mlxsw_reg_ricnt_op_set(payload, op);
5967 mlxsw_reg_ricnt_counter_index_set(payload, index);
5968 mlxsw_reg_ricnt_counter_set_type_set(payload,
5969 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
5970}
5971
5972
5973
5974
5975
5976#define MLXSW_REG_RRCR_ID 0x800F
5977#define MLXSW_REG_RRCR_LEN 0x24
5978
5979MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
5980
5981enum mlxsw_reg_rrcr_op {
5982
5983 MLXSW_REG_RRCR_OP_MOVE,
5984
5985 MLXSW_REG_RRCR_OP_COPY,
5986};
5987
5988
5989
5990
5991MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
5992
5993
5994
5995
5996
5997MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
5998
5999
6000
6001
6002
6003MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
6004
6005
6006
6007
6008
6009
6010MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
6011
6012
6013
6014
6015
6016MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
6017
6018static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
6019 u16 offset, u16 size,
6020 enum mlxsw_reg_rtar_key_type table_id,
6021 u16 dest_offset)
6022{
6023 MLXSW_REG_ZERO(rrcr, payload);
6024 mlxsw_reg_rrcr_op_set(payload, op);
6025 mlxsw_reg_rrcr_offset_set(payload, offset);
6026 mlxsw_reg_rrcr_size_set(payload, size);
6027 mlxsw_reg_rrcr_table_id_set(payload, table_id);
6028 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
6029}
6030
6031
6032
6033
6034
6035#define MLXSW_REG_RALTA_ID 0x8010
6036#define MLXSW_REG_RALTA_LEN 0x04
6037
6038MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
6039
6040
6041
6042
6043
6044
6045
6046MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
6047
6048enum mlxsw_reg_ralxx_protocol {
6049 MLXSW_REG_RALXX_PROTOCOL_IPV4,
6050 MLXSW_REG_RALXX_PROTOCOL_IPV6,
6051};
6052
6053
6054
6055
6056
6057
6058MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
6059
6060
6061
6062
6063
6064
6065
6066MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
6067
6068static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6069 enum mlxsw_reg_ralxx_protocol protocol,
6070 u8 tree_id)
6071{
6072 MLXSW_REG_ZERO(ralta, payload);
6073 mlxsw_reg_ralta_op_set(payload, !alloc);
6074 mlxsw_reg_ralta_protocol_set(payload, protocol);
6075 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6076}
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087#define MLXSW_REG_RALST_ID 0x8011
6088#define MLXSW_REG_RALST_LEN 0x104
6089
6090MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6091
6092
6093
6094
6095
6096
6097
6098MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6099
6100
6101
6102
6103
6104MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6105
6106#define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6107#define MLXSW_REG_RALST_BIN_OFFSET 0x04
6108#define MLXSW_REG_RALST_BIN_COUNT 128
6109
6110
6111
6112
6113
6114
6115
6116MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6117
6118
6119
6120
6121
6122
6123
6124MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6125 false);
6126
6127static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6128{
6129 MLXSW_REG_ZERO(ralst, payload);
6130
6131
6132 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6133 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6134
6135 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6136 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6137}
6138
6139static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6140 u8 left_child_bin,
6141 u8 right_child_bin)
6142{
6143 int bin_index = bin_number - 1;
6144
6145 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6146 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6147 right_child_bin);
6148}
6149
6150
6151
6152
6153
6154#define MLXSW_REG_RALTB_ID 0x8012
6155#define MLXSW_REG_RALTB_LEN 0x04
6156
6157MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6158
6159
6160
6161
6162
6163
6164MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6165
6166
6167
6168
6169
6170MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6171
6172
6173
6174
6175
6176
6177
6178MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6179
6180static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6181 enum mlxsw_reg_ralxx_protocol protocol,
6182 u8 tree_id)
6183{
6184 MLXSW_REG_ZERO(raltb, payload);
6185 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6186 mlxsw_reg_raltb_protocol_set(payload, protocol);
6187 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6188}
6189
6190
6191
6192
6193
6194
6195#define MLXSW_REG_RALUE_ID 0x8013
6196#define MLXSW_REG_RALUE_LEN 0x38
6197
6198MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6199
6200
6201
6202
6203
6204MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6205
6206enum mlxsw_reg_ralue_op {
6207
6208 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6209
6210
6211
6212 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6213
6214
6215
6216
6217 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6218
6219
6220
6221
6222 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6223
6224
6225
6226 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6227
6228
6229
6230 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6231};
6232
6233
6234
6235
6236
6237MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6238
6239
6240
6241
6242
6243
6244
6245
6246MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6247
6248
6249
6250
6251
6252
6253MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6254
6255#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
6256#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
6257#define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
6258
6259
6260
6261
6262
6263
6264
6265
6266MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6267
6268
6269
6270
6271
6272
6273
6274MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6285MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6286
6287enum mlxsw_reg_ralue_entry_type {
6288 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6289 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6290 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6291};
6292
6293
6294
6295
6296
6297
6298MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6309
6310enum mlxsw_reg_ralue_action_type {
6311 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6312 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6313 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6314};
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
6326
6327enum mlxsw_reg_ralue_trap_action {
6328 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
6329 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
6330 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
6331 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
6332 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
6333};
6334
6335
6336
6337
6338
6339
6340MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
6341
6342
6343
6344
6345
6346
6347
6348MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
6349
6350
6351
6352
6353
6354
6355MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
6366
6367
6368
6369
6370
6371
6372MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
6385
6386
6387
6388
6389
6390
6391
6392MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
6393
6394static inline void mlxsw_reg_ralue_pack(char *payload,
6395 enum mlxsw_reg_ralxx_protocol protocol,
6396 enum mlxsw_reg_ralue_op op,
6397 u16 virtual_router, u8 prefix_len)
6398{
6399 MLXSW_REG_ZERO(ralue, payload);
6400 mlxsw_reg_ralue_protocol_set(payload, protocol);
6401 mlxsw_reg_ralue_op_set(payload, op);
6402 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
6403 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
6404 mlxsw_reg_ralue_entry_type_set(payload,
6405 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
6406 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
6407}
6408
6409static inline void mlxsw_reg_ralue_pack4(char *payload,
6410 enum mlxsw_reg_ralxx_protocol protocol,
6411 enum mlxsw_reg_ralue_op op,
6412 u16 virtual_router, u8 prefix_len,
6413 u32 dip)
6414{
6415 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6416 mlxsw_reg_ralue_dip4_set(payload, dip);
6417}
6418
6419static inline void mlxsw_reg_ralue_pack6(char *payload,
6420 enum mlxsw_reg_ralxx_protocol protocol,
6421 enum mlxsw_reg_ralue_op op,
6422 u16 virtual_router, u8 prefix_len,
6423 const void *dip)
6424{
6425 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6426 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
6427}
6428
6429static inline void
6430mlxsw_reg_ralue_act_remote_pack(char *payload,
6431 enum mlxsw_reg_ralue_trap_action trap_action,
6432 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
6433{
6434 mlxsw_reg_ralue_action_type_set(payload,
6435 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
6436 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6437 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6438 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
6439 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
6440}
6441
6442static inline void
6443mlxsw_reg_ralue_act_local_pack(char *payload,
6444 enum mlxsw_reg_ralue_trap_action trap_action,
6445 u16 trap_id, u16 local_erif)
6446{
6447 mlxsw_reg_ralue_action_type_set(payload,
6448 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
6449 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6450 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6451 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
6452}
6453
6454static inline void
6455mlxsw_reg_ralue_act_ip2me_pack(char *payload)
6456{
6457 mlxsw_reg_ralue_action_type_set(payload,
6458 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6459}
6460
6461static inline void
6462mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
6463{
6464 mlxsw_reg_ralue_action_type_set(payload,
6465 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6466 mlxsw_reg_ralue_ip2me_v_set(payload, 1);
6467 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
6468}
6469
6470
6471
6472
6473
6474
6475#define MLXSW_REG_RAUHT_ID 0x8014
6476#define MLXSW_REG_RAUHT_LEN 0x74
6477
6478MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
6479
6480enum mlxsw_reg_rauht_type {
6481 MLXSW_REG_RAUHT_TYPE_IPV4,
6482 MLXSW_REG_RAUHT_TYPE_IPV6,
6483};
6484
6485
6486
6487
6488MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
6489
6490enum mlxsw_reg_rauht_op {
6491 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
6492
6493 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
6494
6495
6496
6497 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
6498
6499
6500
6501 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
6502
6503
6504
6505
6506 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
6507
6508 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
6509
6510 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
6511
6512
6513
6514};
6515
6516
6517
6518
6519MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
6520
6521
6522
6523
6524
6525
6526
6527
6528MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
6529
6530
6531
6532
6533
6534MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
6535
6536
6537
6538
6539
6540MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
6541MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
6542
6543enum mlxsw_reg_rauht_trap_action {
6544 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
6545 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
6546 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
6547 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
6548 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
6549};
6550
6551
6552
6553
6554MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
6555
6556enum mlxsw_reg_rauht_trap_id {
6557 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
6558 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
6559};
6560
6561
6562
6563
6564
6565
6566
6567
6568MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
6569
6570
6571
6572
6573
6574MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
6575
6576
6577
6578
6579
6580MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
6581
6582
6583
6584
6585
6586MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
6587
6588static inline void mlxsw_reg_rauht_pack(char *payload,
6589 enum mlxsw_reg_rauht_op op, u16 rif,
6590 const char *mac)
6591{
6592 MLXSW_REG_ZERO(rauht, payload);
6593 mlxsw_reg_rauht_op_set(payload, op);
6594 mlxsw_reg_rauht_rif_set(payload, rif);
6595 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
6596}
6597
6598static inline void mlxsw_reg_rauht_pack4(char *payload,
6599 enum mlxsw_reg_rauht_op op, u16 rif,
6600 const char *mac, u32 dip)
6601{
6602 mlxsw_reg_rauht_pack(payload, op, rif, mac);
6603 mlxsw_reg_rauht_dip4_set(payload, dip);
6604}
6605
6606static inline void mlxsw_reg_rauht_pack6(char *payload,
6607 enum mlxsw_reg_rauht_op op, u16 rif,
6608 const char *mac, const char *dip)
6609{
6610 mlxsw_reg_rauht_pack(payload, op, rif, mac);
6611 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
6612 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
6613}
6614
6615static inline void mlxsw_reg_rauht_pack_counter(char *payload,
6616 u64 counter_index)
6617{
6618 mlxsw_reg_rauht_counter_index_set(payload, counter_index);
6619 mlxsw_reg_rauht_counter_set_type_set(payload,
6620 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
6621}
6622
6623
6624
6625
6626
6627
6628
6629#define MLXSW_REG_RALEU_ID 0x8015
6630#define MLXSW_REG_RALEU_LEN 0x28
6631
6632MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
6633
6634
6635
6636
6637
6638MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
6639
6640
6641
6642
6643
6644
6645MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
6646
6647
6648
6649
6650
6651MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
6652
6653
6654
6655
6656
6657MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
6658
6659
6660
6661
6662
6663MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
6664
6665
6666
6667
6668
6669MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
6670
6671static inline void mlxsw_reg_raleu_pack(char *payload,
6672 enum mlxsw_reg_ralxx_protocol protocol,
6673 u16 virtual_router,
6674 u32 adjacency_index, u16 ecmp_size,
6675 u32 new_adjacency_index,
6676 u16 new_ecmp_size)
6677{
6678 MLXSW_REG_ZERO(raleu, payload);
6679 mlxsw_reg_raleu_protocol_set(payload, protocol);
6680 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
6681 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
6682 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
6683 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
6684 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
6685}
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695
6696#define MLXSW_REG_RAUHTD_ID 0x8018
6697#define MLXSW_REG_RAUHTD_BASE_LEN 0x20
6698#define MLXSW_REG_RAUHTD_REC_LEN 0x20
6699#define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
6700#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
6701 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
6702#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
6703
6704MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
6705
6706#define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
6707#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
6708
6709
6710
6711
6712
6713
6714
6715
6716MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
6717
6718enum mlxsw_reg_rauhtd_op {
6719 MLXSW_REG_RAUHTD_OP_DUMP,
6720 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
6721};
6722
6723
6724
6725
6726MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
6727
6728
6729
6730
6731
6732
6733
6734
6735
6736MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
6737
6738
6739
6740
6741
6742
6743MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
6744
6745enum mlxsw_reg_rauhtd_type {
6746 MLXSW_REG_RAUHTD_TYPE_IPV4,
6747 MLXSW_REG_RAUHTD_TYPE_IPV6,
6748};
6749
6750
6751
6752
6753
6754
6755
6756MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
6757
6758
6759
6760
6761
6762
6763MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
6764
6765static inline void mlxsw_reg_rauhtd_pack(char *payload,
6766 enum mlxsw_reg_rauhtd_type type)
6767{
6768 MLXSW_REG_ZERO(rauhtd, payload);
6769 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
6770 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
6771 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
6772 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
6773 mlxsw_reg_rauhtd_type_set(payload, type);
6774}
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
6785 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
6786 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
6787
6788
6789
6790
6791
6792
6793
6794MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
6795 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
6796
6797#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
6798
6799
6800
6801
6802
6803
6804MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
6805 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
6806
6807
6808
6809
6810
6811MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
6812 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
6813
6814
6815
6816
6817
6818MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
6819 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
6820
6821#define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
6822
6823
6824
6825
6826
6827
6828MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
6829 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
6830
6831
6832
6833
6834
6835MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
6836 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
6837
6838
6839
6840
6841
6842MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
6843 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
6844
6845static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
6846 int ent_index, u16 *p_rif,
6847 u32 *p_dip)
6848{
6849 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
6850 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
6851}
6852
6853static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
6854 int rec_index, u16 *p_rif,
6855 char *p_dip)
6856{
6857 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
6858 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
6859}
6860
6861
6862
6863
6864
6865
6866#define MLXSW_REG_RTDP_ID 0x8020
6867#define MLXSW_REG_RTDP_LEN 0x44
6868
6869MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
6870
6871enum mlxsw_reg_rtdp_type {
6872 MLXSW_REG_RTDP_TYPE_NVE,
6873 MLXSW_REG_RTDP_TYPE_IPIP,
6874};
6875
6876
6877
6878
6879
6880MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
6881
6882
6883
6884
6885
6886
6887MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
6888
6889
6890
6891
6892
6893
6894
6895MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
6896
6897enum mlxsw_reg_rtdp_ipip_sip_check {
6898
6899 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
6900
6901
6902
6903 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
6904
6905
6906
6907 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
6908};
6909
6910
6911
6912
6913
6914
6915MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
6916
6917
6918#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
6919
6920#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
6921
6922#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
6923
6924
6925
6926
6927
6928
6929MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
6930
6931
6932
6933
6934
6935
6936
6937
6938
6939
6940MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
6941
6942
6943
6944
6945
6946
6947MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
6948
6949
6950
6951
6952
6953
6954
6955
6956MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
6957
6958
6959
6960
6961
6962
6963MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
6964
6965static inline void mlxsw_reg_rtdp_pack(char *payload,
6966 enum mlxsw_reg_rtdp_type type,
6967 u32 tunnel_index)
6968{
6969 MLXSW_REG_ZERO(rtdp, payload);
6970 mlxsw_reg_rtdp_type_set(payload, type);
6971 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
6972}
6973
6974static inline void
6975mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
6976 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
6977 unsigned int type_check, bool gre_key_check,
6978 u32 ipv4_usip, u32 expected_gre_key)
6979{
6980 mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
6981 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
6982 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
6983 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
6984 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
6985 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
6986}
6987
6988
6989
6990
6991
6992
6993#define MLXSW_REG_RIGR2_ID 0x8023
6994#define MLXSW_REG_RIGR2_LEN 0xB0
6995
6996#define MLXSW_REG_RIGR2_MAX_ERIFS 32
6997
6998MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
6999
7000
7001
7002
7003
7004MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
7005
7006
7007
7008
7009
7010MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
7011
7012
7013
7014
7015
7016
7017MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
7018
7019
7020
7021
7022
7023MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
7024
7025
7026
7027
7028
7029
7030
7031
7032MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
7033
7034
7035
7036
7037
7038
7039
7040
7041
7042MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
7043
7044
7045
7046
7047
7048
7049
7050MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
7051
7052static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
7053 bool vnext, u32 next_rigr_index)
7054{
7055 MLXSW_REG_ZERO(rigr2, payload);
7056 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
7057 mlxsw_reg_rigr2_vnext_set(payload, vnext);
7058 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
7059 mlxsw_reg_rigr2_vrmid_set(payload, 0);
7060 mlxsw_reg_rigr2_rmid_index_set(payload, 0);
7061}
7062
7063static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
7064 bool v, u16 erif)
7065{
7066 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
7067 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
7068}
7069
7070
7071
7072
7073#define MLXSW_REG_RECR2_ID 0x8025
7074#define MLXSW_REG_RECR2_LEN 0x38
7075
7076MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7077
7078
7079
7080
7081
7082MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7083
7084
7085
7086
7087
7088MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7089
7090
7091
7092
7093
7094MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7095
7096enum {
7097
7098 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
7099
7100 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4,
7101
7102 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
7103
7104 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6,
7105
7106 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7,
7107
7108 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
7109};
7110
7111
7112
7113
7114
7115
7116MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7117
7118enum {
7119
7120 MLXSW_REG_RECR2_IPV4_SIP0 = 9,
7121 MLXSW_REG_RECR2_IPV4_SIP3 = 12,
7122
7123 MLXSW_REG_RECR2_IPV4_DIP0 = 13,
7124 MLXSW_REG_RECR2_IPV4_DIP3 = 16,
7125
7126 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17,
7127
7128 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21,
7129 MLXSW_REG_RECR2_IPV6_SIP8 = 29,
7130 MLXSW_REG_RECR2_IPV6_SIP15 = 36,
7131
7132 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37,
7133 MLXSW_REG_RECR2_IPV6_DIP8 = 45,
7134 MLXSW_REG_RECR2_IPV6_DIP15 = 52,
7135
7136 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53,
7137
7138 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57,
7139
7140 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74,
7141
7142 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75,
7143};
7144
7145
7146
7147
7148
7149MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7150
7151static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7152{
7153 int i;
7154
7155 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7156 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7157 true);
7158}
7159
7160static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7161{
7162 int i;
7163
7164 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7165 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7166 true);
7167}
7168
7169static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7170{
7171 int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7172
7173 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7174
7175 i = MLXSW_REG_RECR2_IPV6_SIP8;
7176 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7177 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7178 true);
7179}
7180
7181static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7182{
7183 int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7184
7185 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7186
7187 i = MLXSW_REG_RECR2_IPV6_DIP8;
7188 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7189 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7190 true);
7191}
7192
7193static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7194{
7195 MLXSW_REG_ZERO(recr2, payload);
7196 mlxsw_reg_recr2_pp_set(payload, false);
7197 mlxsw_reg_recr2_sh_set(payload, true);
7198 mlxsw_reg_recr2_seed_set(payload, seed);
7199}
7200
7201
7202
7203
7204
7205#define MLXSW_REG_RMFT2_ID 0x8027
7206#define MLXSW_REG_RMFT2_LEN 0x174
7207
7208MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7209
7210
7211
7212
7213
7214MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7215
7216enum mlxsw_reg_rmft2_type {
7217 MLXSW_REG_RMFT2_TYPE_IPV4,
7218 MLXSW_REG_RMFT2_TYPE_IPV6
7219};
7220
7221
7222
7223
7224MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7225
7226enum mlxsw_sp_reg_rmft2_op {
7227
7228
7229
7230
7231
7232
7233
7234 MLXSW_REG_RMFT2_OP_READ_WRITE,
7235};
7236
7237
7238
7239
7240
7241MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7242
7243
7244
7245
7246
7247
7248MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7249
7250
7251
7252
7253
7254MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7255
7256
7257
7258
7259
7260MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7261
7262enum mlxsw_reg_rmft2_irif_mask {
7263 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7264 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7265};
7266
7267
7268
7269
7270
7271MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7272
7273
7274
7275
7276
7277MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7278
7279
7280
7281
7282
7283MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7284MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7285
7286
7287
7288
7289
7290
7291MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7292MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7293
7294
7295
7296
7297
7298MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7299MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7300
7301
7302
7303
7304
7305
7306MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7307MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7308
7309
7310
7311
7312
7313
7314
7315
7316
7317
7318
7319
7320MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
7321 MLXSW_REG_FLEX_ACTION_SET_LEN);
7322
7323static inline void
7324mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
7325 u16 virtual_router,
7326 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7327 const char *flex_action_set)
7328{
7329 MLXSW_REG_ZERO(rmft2, payload);
7330 mlxsw_reg_rmft2_v_set(payload, v);
7331 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
7332 mlxsw_reg_rmft2_offset_set(payload, offset);
7333 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
7334 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
7335 mlxsw_reg_rmft2_irif_set(payload, irif);
7336 if (flex_action_set)
7337 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
7338 flex_action_set);
7339}
7340
7341static inline void
7342mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7343 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7344 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
7345 const char *flexible_action_set)
7346{
7347 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7348 irif_mask, irif, flexible_action_set);
7349 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
7350 mlxsw_reg_rmft2_dip4_set(payload, dip4);
7351 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
7352 mlxsw_reg_rmft2_sip4_set(payload, sip4);
7353 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
7354}
7355
7356static inline void
7357mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7358 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7359 struct in6_addr dip6, struct in6_addr dip6_mask,
7360 struct in6_addr sip6, struct in6_addr sip6_mask,
7361 const char *flexible_action_set)
7362{
7363 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7364 irif_mask, irif, flexible_action_set);
7365 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
7366 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
7367 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
7368 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
7369 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
7370}
7371
7372
7373
7374
7375
7376#define MLXSW_REG_MFCR_ID 0x9001
7377#define MLXSW_REG_MFCR_LEN 0x08
7378
7379MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
7380
7381enum mlxsw_reg_mfcr_pwm_frequency {
7382 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
7383 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
7384 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
7385 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
7386 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
7387 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
7388 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
7389 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
7390};
7391
7392
7393
7394
7395
7396MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
7397
7398#define MLXSW_MFCR_TACHOS_MAX 10
7399
7400
7401
7402
7403
7404MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
7405
7406#define MLXSW_MFCR_PWMS_MAX 5
7407
7408
7409
7410
7411
7412MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
7413
7414static inline void
7415mlxsw_reg_mfcr_pack(char *payload,
7416 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
7417{
7418 MLXSW_REG_ZERO(mfcr, payload);
7419 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
7420}
7421
7422static inline void
7423mlxsw_reg_mfcr_unpack(char *payload,
7424 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
7425 u16 *p_tacho_active, u8 *p_pwm_active)
7426{
7427 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
7428 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
7429 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
7430}
7431
7432
7433
7434
7435
7436#define MLXSW_REG_MFSC_ID 0x9002
7437#define MLXSW_REG_MFSC_LEN 0x08
7438
7439MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
7440
7441
7442
7443
7444
7445MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
7446
7447
7448
7449
7450
7451
7452MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
7453
7454static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
7455 u8 pwm_duty_cycle)
7456{
7457 MLXSW_REG_ZERO(mfsc, payload);
7458 mlxsw_reg_mfsc_pwm_set(payload, pwm);
7459 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
7460}
7461
7462
7463
7464
7465
7466
7467#define MLXSW_REG_MFSM_ID 0x9003
7468#define MLXSW_REG_MFSM_LEN 0x08
7469
7470MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
7471
7472
7473
7474
7475
7476MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
7477
7478
7479
7480
7481
7482MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
7483
7484static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
7485{
7486 MLXSW_REG_ZERO(mfsm, payload);
7487 mlxsw_reg_mfsm_tacho_set(payload, tacho);
7488}
7489
7490
7491
7492
7493
7494
7495
7496#define MLXSW_REG_MFSL_ID 0x9004
7497#define MLXSW_REG_MFSL_LEN 0x0C
7498
7499MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
7500
7501
7502
7503
7504
7505MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
7506
7507
7508
7509
7510
7511MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
7512
7513
7514
7515
7516
7517MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
7518
7519static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
7520 u16 tach_min, u16 tach_max)
7521{
7522 MLXSW_REG_ZERO(mfsl, payload);
7523 mlxsw_reg_mfsl_tacho_set(payload, tacho);
7524 mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
7525 mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
7526}
7527
7528static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
7529 u16 *p_tach_min, u16 *p_tach_max)
7530{
7531 if (p_tach_min)
7532 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
7533
7534 if (p_tach_max)
7535 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
7536}
7537
7538
7539
7540
7541
7542
7543#define MLXSW_REG_MTCAP_ID 0x9009
7544#define MLXSW_REG_MTCAP_LEN 0x08
7545
7546MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
7547
7548
7549
7550
7551
7552
7553MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
7554
7555
7556
7557
7558
7559
7560
7561#define MLXSW_REG_MTMP_ID 0x900A
7562#define MLXSW_REG_MTMP_LEN 0x20
7563
7564MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
7565
7566
7567
7568
7569
7570
7571
7572MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
7573
7574
7575#define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
7576
7577
7578
7579
7580
7581
7582MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
7583
7584
7585
7586
7587
7588MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
7589
7590
7591
7592
7593
7594MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
7595
7596
7597
7598
7599
7600
7601MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
7602
7603
7604
7605
7606
7607
7608
7609
7610MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
7611
7612#define MLXSW_REG_MTMP_THRESH_HI 0x348
7613
7614
7615
7616
7617
7618MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
7619
7620
7621
7622
7623
7624MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
7625
7626#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
7627
7628
7629
7630
7631
7632MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
7633
7634static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
7635 bool max_temp_enable,
7636 bool max_temp_reset)
7637{
7638 MLXSW_REG_ZERO(mtmp, payload);
7639 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
7640 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
7641 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
7642 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
7643 MLXSW_REG_MTMP_THRESH_HI);
7644}
7645
7646static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
7647 unsigned int *p_max_temp,
7648 char *sensor_name)
7649{
7650 u16 temp;
7651
7652 if (p_temp) {
7653 temp = mlxsw_reg_mtmp_temperature_get(payload);
7654 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
7655 }
7656 if (p_max_temp) {
7657 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
7658 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
7659 }
7660 if (sensor_name)
7661 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
7662}
7663
7664
7665
7666
7667
7668
7669#define MLXSW_REG_MCIA_ID 0x9014
7670#define MLXSW_REG_MCIA_LEN 0x40
7671
7672MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
7673
7674
7675
7676
7677
7678
7679
7680MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
7681
7682
7683
7684
7685
7686MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
7687
7688
7689
7690
7691
7692MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
7693
7694
7695
7696
7697
7698MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
7699
7700
7701
7702
7703
7704MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
7705
7706
7707
7708
7709
7710MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
7711
7712
7713
7714
7715
7716MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
7717
7718#define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48
7719
7720
7721
7722
7723
7724MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
7725
7726static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
7727 u8 page_number, u16 device_addr,
7728 u8 size, u8 i2c_device_addr)
7729{
7730 MLXSW_REG_ZERO(mcia, payload);
7731 mlxsw_reg_mcia_module_set(payload, module);
7732 mlxsw_reg_mcia_l_set(payload, lock);
7733 mlxsw_reg_mcia_page_number_set(payload, page_number);
7734 mlxsw_reg_mcia_device_address_set(payload, device_addr);
7735 mlxsw_reg_mcia_size_set(payload, size);
7736 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
7737}
7738
7739
7740
7741
7742
7743
7744#define MLXSW_REG_MPAT_ID 0x901A
7745#define MLXSW_REG_MPAT_LEN 0x78
7746
7747MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
7748
7749
7750
7751
7752
7753MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
7754
7755
7756
7757
7758
7759MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
7760
7761
7762
7763
7764
7765MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
7766
7767
7768
7769
7770
7771
7772
7773
7774
7775
7776MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
7777
7778
7779
7780
7781
7782
7783
7784
7785
7786MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
7787
7788enum mlxsw_reg_mpat_span_type {
7789
7790
7791
7792 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
7793
7794
7795
7796
7797
7798 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
7799
7800
7801
7802
7803 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
7804};
7805
7806
7807
7808
7809
7810MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
7811
7812
7813
7814
7815
7816
7817
7818
7819
7820MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
7821
7822
7823
7824
7825
7826enum mlxsw_reg_mpat_eth_rspan_version {
7827 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
7828};
7829
7830
7831
7832
7833
7834MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
7835
7836
7837
7838
7839
7840MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
7841
7842
7843
7844
7845
7846MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
7847
7848
7849
7850
7851
7852enum mlxsw_reg_mpat_eth_rspan_protocol {
7853 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
7854 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
7855};
7856
7857
7858
7859
7860
7861MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
7862
7863
7864
7865
7866
7867MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
7868
7869
7870
7871
7872
7873MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
7874
7875
7876
7877
7878
7879MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
7880MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
7881
7882
7883
7884
7885
7886MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
7887MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
7888
7889static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
7890 u16 system_port, bool e,
7891 enum mlxsw_reg_mpat_span_type span_type)
7892{
7893 MLXSW_REG_ZERO(mpat, payload);
7894 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
7895 mlxsw_reg_mpat_system_port_set(payload, system_port);
7896 mlxsw_reg_mpat_e_set(payload, e);
7897 mlxsw_reg_mpat_qos_set(payload, 1);
7898 mlxsw_reg_mpat_be_set(payload, 1);
7899 mlxsw_reg_mpat_span_type_set(payload, span_type);
7900}
7901
7902static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
7903{
7904 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
7905}
7906
7907static inline void
7908mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
7909 enum mlxsw_reg_mpat_eth_rspan_version version,
7910 const char *mac,
7911 bool tp)
7912{
7913 mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
7914 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
7915 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
7916}
7917
7918static inline void
7919mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
7920 const char *smac,
7921 u32 sip, u32 dip)
7922{
7923 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
7924 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
7925 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
7926 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
7927 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
7928 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
7929}
7930
7931static inline void
7932mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
7933 const char *smac,
7934 struct in6_addr sip, struct in6_addr dip)
7935{
7936 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
7937 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
7938 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
7939 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
7940 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
7941 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
7942}
7943
7944
7945
7946
7947
7948
7949#define MLXSW_REG_MPAR_ID 0x901B
7950#define MLXSW_REG_MPAR_LEN 0x08
7951
7952MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
7953
7954
7955
7956
7957
7958MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
7959
7960enum mlxsw_reg_mpar_i_e {
7961 MLXSW_REG_MPAR_TYPE_EGRESS,
7962 MLXSW_REG_MPAR_TYPE_INGRESS,
7963};
7964
7965
7966
7967
7968
7969MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
7970
7971
7972
7973
7974
7975
7976MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
7977
7978
7979
7980
7981
7982MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
7983
7984static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
7985 enum mlxsw_reg_mpar_i_e i_e,
7986 bool enable, u8 pa_id)
7987{
7988 MLXSW_REG_ZERO(mpar, payload);
7989 mlxsw_reg_mpar_local_port_set(payload, local_port);
7990 mlxsw_reg_mpar_enable_set(payload, enable);
7991 mlxsw_reg_mpar_i_e_set(payload, i_e);
7992 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
7993}
7994
7995
7996
7997
7998
7999
8000#define MLXSW_REG_MRSR_ID 0x9023
8001#define MLXSW_REG_MRSR_LEN 0x08
8002
8003MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
8004
8005
8006
8007
8008
8009
8010
8011MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
8012
8013static inline void mlxsw_reg_mrsr_pack(char *payload)
8014{
8015 MLXSW_REG_ZERO(mrsr, payload);
8016 mlxsw_reg_mrsr_command_set(payload, 1);
8017}
8018
8019
8020
8021
8022
8023#define MLXSW_REG_MLCR_ID 0x902B
8024#define MLXSW_REG_MLCR_LEN 0x0C
8025
8026MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
8027
8028
8029
8030
8031
8032MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
8033
8034#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
8035
8036
8037
8038
8039
8040
8041
8042MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
8043
8044
8045
8046
8047
8048
8049MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
8050
8051static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
8052 bool active)
8053{
8054 MLXSW_REG_ZERO(mlcr, payload);
8055 mlxsw_reg_mlcr_local_port_set(payload, local_port);
8056 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
8057 MLXSW_REG_MLCR_DURATION_MAX : 0);
8058}
8059
8060
8061
8062
8063
8064#define MLXSW_REG_MCQI_ID 0x9061
8065#define MLXSW_REG_MCQI_BASE_LEN 0x18
8066#define MLXSW_REG_MCQI_CAP_LEN 0x14
8067#define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
8068
8069MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
8070
8071
8072
8073
8074
8075MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
8076
8077enum mlxfw_reg_mcqi_info_type {
8078 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
8079};
8080
8081
8082
8083
8084
8085MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
8086
8087
8088
8089
8090
8091
8092MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
8093
8094
8095
8096
8097
8098
8099MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
8100
8101
8102
8103
8104
8105MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
8106
8107
8108
8109
8110
8111
8112MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
8113
8114
8115
8116
8117
8118MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
8119
8120static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
8121{
8122 MLXSW_REG_ZERO(mcqi, payload);
8123 mlxsw_reg_mcqi_component_index_set(payload, component_index);
8124 mlxsw_reg_mcqi_info_type_set(payload,
8125 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
8126 mlxsw_reg_mcqi_offset_set(payload, 0);
8127 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
8128}
8129
8130static inline void mlxsw_reg_mcqi_unpack(char *payload,
8131 u32 *p_cap_max_component_size,
8132 u8 *p_cap_log_mcda_word_size,
8133 u16 *p_cap_mcda_max_write_size)
8134{
8135 *p_cap_max_component_size =
8136 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
8137 *p_cap_log_mcda_word_size =
8138 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
8139 *p_cap_mcda_max_write_size =
8140 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
8141}
8142
8143
8144
8145
8146
8147#define MLXSW_REG_MCC_ID 0x9062
8148#define MLXSW_REG_MCC_LEN 0x1C
8149
8150MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
8151
8152enum mlxsw_reg_mcc_instruction {
8153 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
8154 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
8155 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
8156 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
8157 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
8158 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
8159};
8160
8161
8162
8163
8164
8165
8166MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
8167
8168
8169
8170
8171
8172
8173MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
8174
8175
8176
8177
8178
8179MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
8180
8181
8182
8183
8184
8185
8186MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
8187
8188
8189
8190
8191
8192MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
8193
8194
8195
8196
8197
8198
8199
8200MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
8201
8202static inline void mlxsw_reg_mcc_pack(char *payload,
8203 enum mlxsw_reg_mcc_instruction instr,
8204 u16 component_index, u32 update_handle,
8205 u32 component_size)
8206{
8207 MLXSW_REG_ZERO(mcc, payload);
8208 mlxsw_reg_mcc_instruction_set(payload, instr);
8209 mlxsw_reg_mcc_component_index_set(payload, component_index);
8210 mlxsw_reg_mcc_update_handle_set(payload, update_handle);
8211 mlxsw_reg_mcc_component_size_set(payload, component_size);
8212}
8213
8214static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
8215 u8 *p_error_code, u8 *p_control_state)
8216{
8217 if (p_update_handle)
8218 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
8219 if (p_error_code)
8220 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
8221 if (p_control_state)
8222 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
8223}
8224
8225
8226
8227
8228
8229#define MLXSW_REG_MCDA_ID 0x9063
8230#define MLXSW_REG_MCDA_BASE_LEN 0x10
8231#define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
8232#define MLXSW_REG_MCDA_LEN \
8233 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
8234
8235MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
8236
8237
8238
8239
8240
8241MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
8242
8243
8244
8245
8246
8247
8248MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
8249
8250
8251
8252
8253
8254MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
8255
8256
8257
8258
8259
8260MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
8261
8262static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
8263 u32 offset, u16 size, u8 *data)
8264{
8265 int i;
8266
8267 MLXSW_REG_ZERO(mcda, payload);
8268 mlxsw_reg_mcda_update_handle_set(payload, update_handle);
8269 mlxsw_reg_mcda_offset_set(payload, offset);
8270 mlxsw_reg_mcda_size_set(payload, size);
8271
8272 for (i = 0; i < size / 4; i++)
8273 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
8274}
8275
8276
8277
8278
8279
8280#define MLXSW_REG_MPSC_ID 0x9080
8281#define MLXSW_REG_MPSC_LEN 0x1C
8282
8283MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
8284
8285
8286
8287
8288
8289
8290MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
8291
8292
8293
8294
8295
8296MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
8297
8298#define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
8299
8300
8301
8302
8303
8304
8305MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
8306
8307static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
8308 u32 rate)
8309{
8310 MLXSW_REG_ZERO(mpsc, payload);
8311 mlxsw_reg_mpsc_local_port_set(payload, local_port);
8312 mlxsw_reg_mpsc_e_set(payload, e);
8313 mlxsw_reg_mpsc_rate_set(payload, rate);
8314}
8315
8316
8317
8318
8319#define MLXSW_REG_MGPC_ID 0x9081
8320#define MLXSW_REG_MGPC_LEN 0x18
8321
8322MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
8323
8324
8325
8326
8327
8328MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
8329
8330
8331
8332
8333
8334MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
8335
8336enum mlxsw_reg_mgpc_opcode {
8337
8338 MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
8339
8340 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
8341};
8342
8343
8344
8345
8346
8347MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
8348
8349
8350
8351
8352
8353MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
8354
8355
8356
8357
8358
8359MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
8360
8361static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
8362 enum mlxsw_reg_mgpc_opcode opcode,
8363 enum mlxsw_reg_flow_counter_set_type set_type)
8364{
8365 MLXSW_REG_ZERO(mgpc, payload);
8366 mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
8367 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
8368 mlxsw_reg_mgpc_opcode_set(payload, opcode);
8369}
8370
8371
8372
8373
8374
8375
8376#define MLXSW_REG_MPRS_ID 0x9083
8377#define MLXSW_REG_MPRS_LEN 0x14
8378
8379MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
8380
8381
8382
8383
8384
8385
8386
8387MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
8388
8389
8390
8391
8392
8393
8394
8395MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
8396
8397
8398
8399
8400
8401
8402
8403MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
8404
8405static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
8406 u16 vxlan_udp_dport)
8407{
8408 MLXSW_REG_ZERO(mprs, payload);
8409 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
8410 mlxsw_reg_mprs_parsing_en_set(payload, true);
8411 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
8412}
8413
8414
8415
8416
8417
8418#define MLXSW_REG_TNGCR_ID 0xA001
8419#define MLXSW_REG_TNGCR_LEN 0x44
8420
8421MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
8422
8423enum mlxsw_reg_tngcr_type {
8424 MLXSW_REG_TNGCR_TYPE_VXLAN,
8425 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
8426 MLXSW_REG_TNGCR_TYPE_GENEVE,
8427 MLXSW_REG_TNGCR_TYPE_NVGRE,
8428};
8429
8430
8431
8432
8433
8434
8435
8436MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
8437
8438
8439
8440
8441
8442MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
8443
8444
8445
8446
8447
8448MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
8449
8450
8451
8452
8453
8454MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
8455
8456enum {
8457
8458 MLXSW_REG_TNGCR_FL_NO_COPY,
8459
8460
8461
8462
8463 MLXSW_REG_TNGCR_FL_COPY,
8464};
8465
8466
8467
8468
8469
8470MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
8471
8472enum {
8473
8474
8475
8476 MLXSW_REG_TNGCR_FL_NO_HASH,
8477
8478
8479
8480 MLXSW_REG_TNGCR_FL_HASH,
8481};
8482
8483
8484
8485
8486
8487MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
8488
8489
8490
8491
8492
8493MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
8494
8495
8496
8497
8498
8499
8500MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
8501
8502enum {
8503
8504 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
8505
8506 MLXSW_REG_TNGCR_UDP_SPORT_HASH,
8507};
8508
8509
8510
8511
8512
8513
8514
8515
8516
8517MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
8518
8519
8520
8521
8522
8523
8524MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
8525
8526
8527
8528
8529
8530
8531
8532
8533
8534MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
8535
8536
8537
8538
8539
8540
8541
8542
8543
8544MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
8545
8546
8547
8548
8549
8550
8551MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
8552
8553
8554
8555
8556
8557
8558MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
8559
8560
8561
8562
8563
8564
8565MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
8566
8567
8568
8569
8570
8571MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
8572
8573
8574
8575
8576
8577
8578MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
8579
8580static inline void mlxsw_reg_tngcr_pack(char *payload,
8581 enum mlxsw_reg_tngcr_type type,
8582 bool valid, u8 ttl)
8583{
8584 MLXSW_REG_ZERO(tngcr, payload);
8585 mlxsw_reg_tngcr_type_set(payload, type);
8586 mlxsw_reg_tngcr_nve_valid_set(payload, valid);
8587 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
8588 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
8589 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
8590 mlxsw_reg_tngcr_nve_flh_set(payload, 0);
8591 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
8592 MLXSW_REG_TNGCR_UDP_SPORT_HASH);
8593 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
8594 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
8595 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
8596}
8597
8598
8599
8600
8601
8602
8603#define MLXSW_REG_TNUMT_ID 0xA003
8604#define MLXSW_REG_TNUMT_LEN 0x20
8605
8606MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
8607
8608enum mlxsw_reg_tnumt_record_type {
8609 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
8610 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
8611 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
8612};
8613
8614
8615
8616
8617
8618MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
8619
8620enum mlxsw_reg_tnumt_tunnel_port {
8621 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
8622 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
8623 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
8624 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
8625};
8626
8627
8628
8629
8630
8631MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
8632
8633
8634
8635
8636
8637
8638MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
8639
8640
8641
8642
8643
8644MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
8645
8646
8647
8648
8649
8650MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
8651
8652
8653
8654
8655
8656
8657MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
8658
8659
8660
8661
8662
8663MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
8664
8665
8666
8667
8668
8669
8670MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
8671
8672static inline void mlxsw_reg_tnumt_pack(char *payload,
8673 enum mlxsw_reg_tnumt_record_type type,
8674 enum mlxsw_reg_tnumt_tunnel_port tport,
8675 u32 underlay_mc_ptr, bool vnext,
8676 u32 next_underlay_mc_ptr,
8677 u8 record_size)
8678{
8679 MLXSW_REG_ZERO(tnumt, payload);
8680 mlxsw_reg_tnumt_record_type_set(payload, type);
8681 mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
8682 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
8683 mlxsw_reg_tnumt_vnext_set(payload, vnext);
8684 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
8685 mlxsw_reg_tnumt_record_size_set(payload, record_size);
8686}
8687
8688
8689
8690
8691
8692
8693#define MLXSW_REG_TNQCR_ID 0xA010
8694#define MLXSW_REG_TNQCR_LEN 0x0C
8695
8696MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
8697
8698
8699
8700
8701
8702
8703
8704
8705MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
8706
8707static inline void mlxsw_reg_tnqcr_pack(char *payload)
8708{
8709 MLXSW_REG_ZERO(tnqcr, payload);
8710 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
8711}
8712
8713
8714
8715
8716
8717
8718#define MLXSW_REG_TNQDR_ID 0xA011
8719#define MLXSW_REG_TNQDR_LEN 0x08
8720
8721MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
8722
8723
8724
8725
8726
8727MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
8728
8729
8730
8731
8732
8733MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
8734
8735static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
8736{
8737 MLXSW_REG_ZERO(tnqdr, payload);
8738 mlxsw_reg_tnqdr_local_port_set(payload, local_port);
8739 mlxsw_reg_tnqdr_dscp_set(payload, 0);
8740}
8741
8742
8743
8744
8745
8746
8747#define MLXSW_REG_TNEEM_ID 0xA012
8748#define MLXSW_REG_TNEEM_LEN 0x0C
8749
8750MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
8751
8752
8753
8754
8755
8756MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
8757
8758
8759
8760
8761
8762MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
8763
8764static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
8765 u8 underlay_ecn)
8766{
8767 MLXSW_REG_ZERO(tneem, payload);
8768 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
8769 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
8770}
8771
8772
8773
8774
8775
8776
8777#define MLXSW_REG_TNDEM_ID 0xA013
8778#define MLXSW_REG_TNDEM_LEN 0x0C
8779
8780MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
8781
8782
8783
8784
8785
8786MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
8787
8788
8789
8790
8791
8792MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
8793
8794
8795
8796
8797
8798
8799MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
8800
8801
8802
8803
8804
8805
8806
8807MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
8808
8809
8810
8811
8812
8813
8814MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
8815
8816static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
8817 u8 overlay_ecn, u8 ecn, bool trap_en,
8818 u16 trap_id)
8819{
8820 MLXSW_REG_ZERO(tndem, payload);
8821 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
8822 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
8823 mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
8824 mlxsw_reg_tndem_trap_en_set(payload, trap_en);
8825 mlxsw_reg_tndem_trap_id_set(payload, trap_id);
8826}
8827
8828
8829
8830
8831
8832
8833#define MLXSW_REG_TNPC_ID 0xA020
8834#define MLXSW_REG_TNPC_LEN 0x18
8835
8836MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
8837
8838enum mlxsw_reg_tnpc_tunnel_port {
8839 MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
8840 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
8841 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
8842 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
8843};
8844
8845
8846
8847
8848
8849MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
8850
8851
8852
8853
8854
8855MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
8856
8857
8858
8859
8860
8861MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
8862
8863static inline void mlxsw_reg_tnpc_pack(char *payload,
8864 enum mlxsw_reg_tnpc_tunnel_port tport,
8865 bool learn_enable)
8866{
8867 MLXSW_REG_ZERO(tnpc, payload);
8868 mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
8869 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
8870 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
8871}
8872
8873
8874
8875
8876
8877#define MLXSW_REG_TIGCR_ID 0xA801
8878#define MLXSW_REG_TIGCR_LEN 0x10
8879
8880MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
8881
8882
8883
8884
8885
8886
8887MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
8888
8889
8890
8891
8892
8893
8894MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
8895
8896static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
8897{
8898 MLXSW_REG_ZERO(tigcr, payload);
8899 mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
8900 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
8901}
8902
8903
8904
8905
8906
8907#define MLXSW_REG_SBPR_ID 0xB001
8908#define MLXSW_REG_SBPR_LEN 0x14
8909
8910MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
8911
8912
8913enum mlxsw_reg_sbxx_dir {
8914 MLXSW_REG_SBXX_DIR_INGRESS,
8915 MLXSW_REG_SBXX_DIR_EGRESS,
8916};
8917
8918
8919
8920
8921
8922MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
8923
8924
8925
8926
8927
8928MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
8929
8930
8931
8932
8933
8934MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
8935
8936
8937
8938
8939
8940
8941MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
8942
8943enum mlxsw_reg_sbpr_mode {
8944 MLXSW_REG_SBPR_MODE_STATIC,
8945 MLXSW_REG_SBPR_MODE_DYNAMIC,
8946};
8947
8948
8949
8950
8951
8952MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
8953
8954static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
8955 enum mlxsw_reg_sbxx_dir dir,
8956 enum mlxsw_reg_sbpr_mode mode, u32 size,
8957 bool infi_size)
8958{
8959 MLXSW_REG_ZERO(sbpr, payload);
8960 mlxsw_reg_sbpr_pool_set(payload, pool);
8961 mlxsw_reg_sbpr_dir_set(payload, dir);
8962 mlxsw_reg_sbpr_mode_set(payload, mode);
8963 mlxsw_reg_sbpr_size_set(payload, size);
8964 mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
8965}
8966
8967
8968
8969
8970
8971
8972
8973#define MLXSW_REG_SBCM_ID 0xB002
8974#define MLXSW_REG_SBCM_LEN 0x28
8975
8976MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
8977
8978
8979
8980
8981
8982
8983
8984MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
8985
8986
8987
8988
8989
8990
8991
8992
8993
8994MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
8995
8996
8997
8998
8999
9000MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
9001
9002
9003
9004
9005
9006MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
9007
9008
9009#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
9010#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
9011
9012
9013
9014
9015
9016MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
9017
9018
9019
9020
9021
9022
9023
9024
9025
9026
9027
9028
9029
9030MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
9031
9032
9033
9034
9035
9036MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
9037
9038static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
9039 enum mlxsw_reg_sbxx_dir dir,
9040 u32 min_buff, u32 max_buff,
9041 bool infi_max, u8 pool)
9042{
9043 MLXSW_REG_ZERO(sbcm, payload);
9044 mlxsw_reg_sbcm_local_port_set(payload, local_port);
9045 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
9046 mlxsw_reg_sbcm_dir_set(payload, dir);
9047 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
9048 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
9049 mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
9050 mlxsw_reg_sbcm_pool_set(payload, pool);
9051}
9052
9053
9054
9055
9056
9057
9058
9059#define MLXSW_REG_SBPM_ID 0xB003
9060#define MLXSW_REG_SBPM_LEN 0x28
9061
9062MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
9063
9064
9065
9066
9067
9068
9069
9070MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
9071
9072
9073
9074
9075
9076MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
9077
9078
9079
9080
9081
9082MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
9083
9084
9085
9086
9087
9088MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
9089
9090
9091
9092
9093
9094
9095
9096MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
9097
9098
9099
9100
9101
9102
9103MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
9104
9105
9106
9107
9108
9109MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
9110
9111
9112
9113
9114
9115
9116
9117
9118
9119
9120
9121
9122MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
9123
9124static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
9125 enum mlxsw_reg_sbxx_dir dir, bool clr,
9126 u32 min_buff, u32 max_buff)
9127{
9128 MLXSW_REG_ZERO(sbpm, payload);
9129 mlxsw_reg_sbpm_local_port_set(payload, local_port);
9130 mlxsw_reg_sbpm_pool_set(payload, pool);
9131 mlxsw_reg_sbpm_dir_set(payload, dir);
9132 mlxsw_reg_sbpm_clr_set(payload, clr);
9133 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
9134 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
9135}
9136
9137static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
9138 u32 *p_max_buff_occupancy)
9139{
9140 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
9141 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
9142}
9143
9144
9145
9146
9147
9148
9149
9150#define MLXSW_REG_SBMM_ID 0xB004
9151#define MLXSW_REG_SBMM_LEN 0x28
9152
9153MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
9154
9155
9156
9157
9158
9159MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
9160
9161
9162
9163
9164
9165MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
9166
9167
9168
9169
9170
9171
9172
9173
9174
9175
9176
9177
9178MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
9179
9180
9181
9182
9183
9184MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
9185
9186static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
9187 u32 max_buff, u8 pool)
9188{
9189 MLXSW_REG_ZERO(sbmm, payload);
9190 mlxsw_reg_sbmm_prio_set(payload, prio);
9191 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
9192 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
9193 mlxsw_reg_sbmm_pool_set(payload, pool);
9194}
9195
9196
9197
9198
9199
9200
9201
9202
9203
9204#define MLXSW_REG_SBSR_ID 0xB005
9205#define MLXSW_REG_SBSR_BASE_LEN 0x5C
9206#define MLXSW_REG_SBSR_REC_LEN 0x8
9207#define MLXSW_REG_SBSR_REC_MAX_COUNT 120
9208#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
9209 MLXSW_REG_SBSR_REC_LEN * \
9210 MLXSW_REG_SBSR_REC_MAX_COUNT)
9211
9212MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
9213
9214
9215
9216
9217
9218
9219
9220MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
9221
9222
9223
9224
9225
9226
9227
9228
9229MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
9230
9231
9232
9233
9234
9235
9236
9237
9238
9239MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
9240
9241
9242
9243
9244
9245
9246
9247
9248MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
9249
9250
9251
9252
9253
9254
9255
9256
9257
9258MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
9259
9260static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
9261{
9262 MLXSW_REG_ZERO(sbsr, payload);
9263 mlxsw_reg_sbsr_clr_set(payload, clr);
9264}
9265
9266
9267
9268
9269
9270MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
9271 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
9272
9273
9274
9275
9276
9277
9278MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
9279 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
9280
9281static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
9282 u32 *p_buff_occupancy,
9283 u32 *p_max_buff_occupancy)
9284{
9285 *p_buff_occupancy =
9286 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
9287 *p_max_buff_occupancy =
9288 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
9289}
9290
9291
9292
9293
9294
9295
9296
9297
9298
9299#define MLXSW_REG_SBIB_ID 0xB006
9300#define MLXSW_REG_SBIB_LEN 0x10
9301
9302MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
9303
9304
9305
9306
9307
9308
9309MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
9310
9311
9312
9313
9314
9315
9316
9317MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
9318
9319static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
9320 u32 buff_size)
9321{
9322 MLXSW_REG_ZERO(sbib, payload);
9323 mlxsw_reg_sbib_local_port_set(payload, local_port);
9324 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
9325}
9326
9327static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
9328 MLXSW_REG(sgcr),
9329 MLXSW_REG(spad),
9330 MLXSW_REG(smid),
9331 MLXSW_REG(sspr),
9332 MLXSW_REG(sfdat),
9333 MLXSW_REG(sfd),
9334 MLXSW_REG(sfn),
9335 MLXSW_REG(spms),
9336 MLXSW_REG(spvid),
9337 MLXSW_REG(spvm),
9338 MLXSW_REG(spaft),
9339 MLXSW_REG(sfgc),
9340 MLXSW_REG(sftr),
9341 MLXSW_REG(sfdf),
9342 MLXSW_REG(sldr),
9343 MLXSW_REG(slcr),
9344 MLXSW_REG(slcor),
9345 MLXSW_REG(spmlr),
9346 MLXSW_REG(svfa),
9347 MLXSW_REG(svpe),
9348 MLXSW_REG(sfmr),
9349 MLXSW_REG(spvmlr),
9350 MLXSW_REG(cwtp),
9351 MLXSW_REG(cwtpm),
9352 MLXSW_REG(pgcr),
9353 MLXSW_REG(ppbt),
9354 MLXSW_REG(pacl),
9355 MLXSW_REG(pagt),
9356 MLXSW_REG(ptar),
9357 MLXSW_REG(ppbs),
9358 MLXSW_REG(prcr),
9359 MLXSW_REG(pefa),
9360 MLXSW_REG(ptce2),
9361 MLXSW_REG(perpt),
9362 MLXSW_REG(perar),
9363 MLXSW_REG(ptce3),
9364 MLXSW_REG(percr),
9365 MLXSW_REG(pererp),
9366 MLXSW_REG(iedr),
9367 MLXSW_REG(qpts),
9368 MLXSW_REG(qpcr),
9369 MLXSW_REG(qtct),
9370 MLXSW_REG(qeec),
9371 MLXSW_REG(qrwe),
9372 MLXSW_REG(qpdsm),
9373 MLXSW_REG(qpdpm),
9374 MLXSW_REG(qtctm),
9375 MLXSW_REG(pmlp),
9376 MLXSW_REG(pmtu),
9377 MLXSW_REG(ptys),
9378 MLXSW_REG(ppad),
9379 MLXSW_REG(paos),
9380 MLXSW_REG(pfcc),
9381 MLXSW_REG(ppcnt),
9382 MLXSW_REG(plib),
9383 MLXSW_REG(pptb),
9384 MLXSW_REG(pbmc),
9385 MLXSW_REG(pspa),
9386 MLXSW_REG(htgt),
9387 MLXSW_REG(hpkt),
9388 MLXSW_REG(rgcr),
9389 MLXSW_REG(ritr),
9390 MLXSW_REG(rtar),
9391 MLXSW_REG(ratr),
9392 MLXSW_REG(rtdp),
9393 MLXSW_REG(rdpm),
9394 MLXSW_REG(ricnt),
9395 MLXSW_REG(rrcr),
9396 MLXSW_REG(ralta),
9397 MLXSW_REG(ralst),
9398 MLXSW_REG(raltb),
9399 MLXSW_REG(ralue),
9400 MLXSW_REG(rauht),
9401 MLXSW_REG(raleu),
9402 MLXSW_REG(rauhtd),
9403 MLXSW_REG(rigr2),
9404 MLXSW_REG(recr2),
9405 MLXSW_REG(rmft2),
9406 MLXSW_REG(mfcr),
9407 MLXSW_REG(mfsc),
9408 MLXSW_REG(mfsm),
9409 MLXSW_REG(mfsl),
9410 MLXSW_REG(mtcap),
9411 MLXSW_REG(mtmp),
9412 MLXSW_REG(mcia),
9413 MLXSW_REG(mpat),
9414 MLXSW_REG(mpar),
9415 MLXSW_REG(mrsr),
9416 MLXSW_REG(mlcr),
9417 MLXSW_REG(mpsc),
9418 MLXSW_REG(mcqi),
9419 MLXSW_REG(mcc),
9420 MLXSW_REG(mcda),
9421 MLXSW_REG(mgpc),
9422 MLXSW_REG(mprs),
9423 MLXSW_REG(tngcr),
9424 MLXSW_REG(tnumt),
9425 MLXSW_REG(tnqcr),
9426 MLXSW_REG(tnqdr),
9427 MLXSW_REG(tneem),
9428 MLXSW_REG(tndem),
9429 MLXSW_REG(tnpc),
9430 MLXSW_REG(tigcr),
9431 MLXSW_REG(sbpr),
9432 MLXSW_REG(sbcm),
9433 MLXSW_REG(sbpm),
9434 MLXSW_REG(sbmm),
9435 MLXSW_REG(sbsr),
9436 MLXSW_REG(sbib),
9437};
9438
9439static inline const char *mlxsw_reg_id_str(u16 reg_id)
9440{
9441 const struct mlxsw_reg_info *reg_info;
9442 int i;
9443
9444 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
9445 reg_info = mlxsw_reg_infos[i];
9446 if (reg_info->id == reg_id)
9447 return reg_info->name;
9448 }
9449 return "*UNKNOWN*";
9450}
9451
9452
9453
9454
9455
9456#define MLXSW_REG_PUDE_LEN 0x10
9457
9458
9459
9460
9461
9462MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
9463
9464
9465
9466
9467
9468MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
9469
9470
9471
9472
9473
9474
9475
9476
9477
9478
9479MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
9480
9481
9482
9483
9484
9485
9486
9487
9488
9489MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
9490
9491#endif
9492