1/******************************************************************************* 2 Copyright (C) 2007-2009 STMicroelectronics Ltd 3 4 This program is free software; you can redistribute it and/or modify it 5 under the terms and conditions of the GNU General Public License, 6 version 2, as published by the Free Software Foundation. 7 8 This program is distributed in the hope it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 more details. 12 13 The full GNU General Public License is included in this distribution in 14 the file called "COPYING". 15 16 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 17*******************************************************************************/ 18 19#ifndef __STMMAC_H__ 20#define __STMMAC_H__ 21 22#define STMMAC_RESOURCE_NAME "stmmaceth" 23#define DRV_MODULE_VERSION "Jan_2016" 24 25#include <linux/clk.h> 26#include <linux/stmmac.h> 27#include <linux/phy.h> 28#include <linux/pci.h> 29#include "common.h" 30#include <linux/ptp_clock_kernel.h> 31#include <linux/reset.h> 32 33struct stmmac_resources { 34 void __iomem *addr; 35 const char *mac; 36 int wol_irq; 37 int lpi_irq; 38 int irq; 39}; 40 41struct stmmac_tx_info { 42 dma_addr_t buf; 43 bool map_as_page; 44 unsigned len; 45 bool last_segment; 46 bool is_jumbo; 47}; 48 49/* Frequently used values are kept adjacent for cache effect */ 50struct stmmac_tx_queue { 51 u32 tx_count_frames; 52 struct timer_list txtimer; 53 u32 queue_index; 54 struct stmmac_priv *priv_data; 55 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp; 56 struct dma_desc *dma_tx; 57 struct sk_buff **tx_skbuff; 58 struct stmmac_tx_info *tx_skbuff_dma; 59 unsigned int cur_tx; 60 unsigned int dirty_tx; 61 dma_addr_t dma_tx_phy; 62 u32 tx_tail_addr; 63 u32 mss; 64}; 65 66struct stmmac_rx_queue { 67 u32 queue_index; 68 struct stmmac_priv *priv_data; 69 struct dma_extended_desc *dma_erx; 70 struct dma_desc *dma_rx ____cacheline_aligned_in_smp; 71 struct sk_buff **rx_skbuff; 72 dma_addr_t *rx_skbuff_dma; 73 unsigned int cur_rx; 74 unsigned int dirty_rx; 75 u32 rx_zeroc_thresh; 76 dma_addr_t dma_rx_phy; 77 u32 rx_tail_addr; 78}; 79 80struct stmmac_channel { 81 struct napi_struct napi ____cacheline_aligned_in_smp; 82 struct stmmac_priv *priv_data; 83 u32 index; 84 int has_rx; 85 int has_tx; 86}; 87 88struct stmmac_tc_entry { 89 bool in_use; 90 bool in_hw; 91 bool is_last; 92 bool is_frag; 93 void *frag_ptr; 94 unsigned int table_pos; 95 u32 handle; 96 u32 prio; 97 struct { 98 u32 match_data; 99 u32 match_en; 100 u8 af:1; 101 u8 rf:1; 102 u8 im:1; 103 u8 nc:1; 104 u8 res1:4; 105 u8 frame_offset; 106 u8 ok_index; 107 u8 dma_ch_no; 108 u32 res2; 109 } __packed val; 110}; 111 112#define STMMAC_PPS_MAX 4 113struct stmmac_pps_cfg { 114 bool available; 115 struct timespec64 start; 116 struct timespec64 period; 117}; 118 119struct stmmac_priv { 120 /* Frequently used values are kept adjacent for cache effect */ 121 u32 tx_coal_frames; 122 u32 tx_coal_timer; 123 124 int tx_coalesce; 125 int hwts_tx_en; 126 bool tx_path_in_lpi_mode; 127 bool tso; 128 129 unsigned int dma_buf_sz; 130 unsigned int rx_copybreak; 131 u32 rx_riwt; 132 int hwts_rx_en; 133 134 void __iomem *ioaddr; 135 struct net_device *dev; 136 struct device *device; 137 struct mac_device_info *hw; 138 int (*hwif_quirks)(struct stmmac_priv *priv); 139 struct mutex lock; 140 141 /* RX Queue */ 142 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES]; 143 144 /* TX Queue */ 145 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES]; 146 147 /* Generic channel for NAPI */ 148 struct stmmac_channel channel[STMMAC_CH_MAX]; 149 150 bool oldlink; 151 int speed; 152 int oldduplex; 153 unsigned int flow_ctrl; 154 unsigned int pause; 155 struct mii_bus *mii; 156 int mii_irq[PHY_MAX_ADDR]; 157 158 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp; 159 struct stmmac_safety_stats sstats; 160 struct plat_stmmacenet_data *plat; 161 struct dma_features dma_cap; 162 struct stmmac_counters mmc; 163 int hw_cap_support; 164 int synopsys_id; 165 u32 msg_enable; 166 int wolopts; 167 int wol_irq; 168 int clk_csr; 169 struct timer_list eee_ctrl_timer; 170 int lpi_irq; 171 int eee_enabled; 172 int eee_active; 173 int tx_lpi_timer; 174 unsigned int mode; 175 unsigned int chain_mode; 176 int extend_desc; 177 struct ptp_clock *ptp_clock; 178 struct ptp_clock_info ptp_clock_ops; 179 unsigned int default_addend; 180 u32 sub_second_inc; 181 u32 systime_flags; 182 u32 adv_ts; 183 int use_riwt; 184 int irq_wake; 185 spinlock_t ptp_lock; 186 void __iomem *mmcaddr; 187 void __iomem *ptpaddr; 188 189#ifdef CONFIG_DEBUG_FS 190 struct dentry *dbgfs_dir; 191 struct dentry *dbgfs_rings_status; 192 struct dentry *dbgfs_dma_cap; 193#endif 194 195 unsigned long state; 196 struct workqueue_struct *wq; 197 struct work_struct service_task; 198 199 /* TC Handling */ 200 unsigned int tc_entries_max; 201 unsigned int tc_off_max; 202 struct stmmac_tc_entry *tc_entries; 203 204 /* Pulse Per Second output */ 205 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; 206}; 207 208enum stmmac_state { 209 STMMAC_DOWN, 210 STMMAC_RESET_REQUESTED, 211 STMMAC_RESETING, 212 STMMAC_SERVICE_SCHED, 213}; 214 215int stmmac_mdio_unregister(struct net_device *ndev); 216int stmmac_mdio_register(struct net_device *ndev); 217int stmmac_mdio_reset(struct mii_bus *mii); 218void stmmac_set_ethtool_ops(struct net_device *netdev); 219 220void stmmac_ptp_register(struct stmmac_priv *priv); 221void stmmac_ptp_unregister(struct stmmac_priv *priv); 222int stmmac_resume(struct device *dev); 223int stmmac_suspend(struct device *dev); 224int stmmac_dvr_remove(struct device *dev); 225int stmmac_dvr_probe(struct device *device, 226 struct plat_stmmacenet_data *plat_dat, 227 struct stmmac_resources *res); 228void stmmac_disable_eee_mode(struct stmmac_priv *priv); 229bool stmmac_eee_init(struct stmmac_priv *priv); 230 231#endif /* __STMMAC_H__ */ 232