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17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/mii.h>
20#include <linux/ethtool.h>
21#include <linux/phy.h>
22#include <linux/microchipphy.h>
23#include <linux/delay.h>
24#include <linux/of.h>
25#include <dt-bindings/net/microchip-lan78xx.h>
26
27#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
28#define DRIVER_DESC "Microchip LAN88XX PHY driver"
29
30struct lan88xx_priv {
31 int chip_id;
32 int chip_rev;
33 __u32 wolopts;
34};
35
36static int lan88xx_read_page(struct phy_device *phydev)
37{
38 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
39}
40
41static int lan88xx_write_page(struct phy_device *phydev, int page)
42{
43 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
44}
45
46static int lan88xx_phy_config_intr(struct phy_device *phydev)
47{
48 int rc;
49
50 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
51
52 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
53 rc = phy_read(phydev, LAN88XX_INT_STS);
54 rc = phy_write(phydev, LAN88XX_INT_MASK,
55 LAN88XX_INT_MASK_MDINTPIN_EN_ |
56 LAN88XX_INT_MASK_LINK_CHANGE_);
57 } else {
58 rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
59 }
60
61 return rc < 0 ? rc : 0;
62}
63
64static int lan88xx_phy_ack_interrupt(struct phy_device *phydev)
65{
66 int rc = phy_read(phydev, LAN88XX_INT_STS);
67
68 return rc < 0 ? rc : 0;
69}
70
71static int lan88xx_suspend(struct phy_device *phydev)
72{
73 struct lan88xx_priv *priv = phydev->priv;
74
75
76 if (!priv->wolopts)
77 genphy_suspend(phydev);
78
79 return 0;
80}
81
82static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
83 u32 data)
84{
85 int val, save_page, ret = 0;
86 u16 buf;
87
88
89 save_page = phy_save_page(phydev);
90 if (save_page < 0) {
91 phydev_warn(phydev, "Failed to get current page\n");
92 goto err;
93 }
94
95
96 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
97
98 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
99 (data & 0xFFFF));
100 if (ret < 0) {
101 phydev_warn(phydev, "Failed to write TR low data\n");
102 goto err;
103 }
104
105 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
106 (data & 0x00FF0000) >> 16);
107 if (ret < 0) {
108 phydev_warn(phydev, "Failed to write TR high data\n");
109 goto err;
110 }
111
112
113 buf = (regaddr & ~(0x3 << 13));
114 buf |= 0x8000;
115
116 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
117 if (ret < 0) {
118 phydev_warn(phydev, "Failed to write data in reg\n");
119 goto err;
120 }
121
122 usleep_range(1000, 2000);
123 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
124 if (!(val & 0x8000))
125 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
126 regaddr);
127err:
128 return phy_restore_page(phydev, save_page, ret);
129}
130
131static void lan88xx_config_TR_regs(struct phy_device *phydev)
132{
133 int err;
134
135
136
137
138
139 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
140 if (err < 0)
141 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
142
143
144
145
146
147 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
148 if (err < 0)
149 phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
150
151
152
153
154
155 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
156 if (err < 0)
157 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
158
159
160
161
162
163
164 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
165 if (err < 0)
166 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
167
168
169
170
171
172 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
173 if (err < 0)
174 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
175
176
177
178
179
180 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
181 if (err < 0)
182 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
183
184
185
186
187
188 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
189 if (err < 0)
190 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
191
192
193
194
195
196
197 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
198 if (err < 0)
199 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
200
201
202
203
204
205
206 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
207 if (err < 0)
208 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
209
210
211
212
213
214
215 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
216 if (err < 0)
217 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
218
219
220
221
222 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
223 if (err < 0)
224 phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
225}
226
227static int lan88xx_probe(struct phy_device *phydev)
228{
229 struct device *dev = &phydev->mdio.dev;
230 struct lan88xx_priv *priv;
231 u32 led_modes[4];
232 int len;
233
234 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
235 if (!priv)
236 return -ENOMEM;
237
238 priv->wolopts = 0;
239
240 len = of_property_read_variable_u32_array(dev->of_node,
241 "microchip,led-modes",
242 led_modes,
243 0,
244 ARRAY_SIZE(led_modes));
245 if (len >= 0) {
246 u32 reg = 0;
247 int i;
248
249 for (i = 0; i < len; i++) {
250 if (led_modes[i] > 15)
251 return -EINVAL;
252 reg |= led_modes[i] << (i * 4);
253 }
254 for (; i < ARRAY_SIZE(led_modes); i++)
255 reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
256 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
257 } else if (len == -EOVERFLOW) {
258 return -EINVAL;
259 }
260
261
262 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
263 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
264
265 phydev->priv = priv;
266
267 return 0;
268}
269
270static void lan88xx_remove(struct phy_device *phydev)
271{
272 struct device *dev = &phydev->mdio.dev;
273 struct lan88xx_priv *priv = phydev->priv;
274
275 if (priv)
276 devm_kfree(dev, priv);
277}
278
279static int lan88xx_set_wol(struct phy_device *phydev,
280 struct ethtool_wolinfo *wol)
281{
282 struct lan88xx_priv *priv = phydev->priv;
283
284 priv->wolopts = wol->wolopts;
285
286 return 0;
287}
288
289static void lan88xx_set_mdix(struct phy_device *phydev)
290{
291 int buf;
292 int val;
293
294 switch (phydev->mdix_ctrl) {
295 case ETH_TP_MDI:
296 val = LAN88XX_EXT_MODE_CTRL_MDI_;
297 break;
298 case ETH_TP_MDI_X:
299 val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
300 break;
301 case ETH_TP_MDI_AUTO:
302 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
303 break;
304 default:
305 return;
306 }
307
308 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
309 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
310 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
311 buf |= val;
312 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
313 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
314}
315
316static int lan88xx_config_init(struct phy_device *phydev)
317{
318 int val;
319
320 genphy_config_init(phydev);
321
322 val = phy_read_mmd(phydev, MDIO_MMD_PCS,
323 PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
324 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
325
326 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
327 val);
328
329
330 lan88xx_config_TR_regs(phydev);
331
332 return 0;
333}
334
335static int lan88xx_config_aneg(struct phy_device *phydev)
336{
337 lan88xx_set_mdix(phydev);
338
339 return genphy_config_aneg(phydev);
340}
341
342static struct phy_driver microchip_phy_driver[] = {
343{
344 .phy_id = 0x0007c130,
345 .phy_id_mask = 0xfffffff0,
346 .name = "Microchip LAN88xx",
347
348 .features = PHY_GBIT_FEATURES,
349 .flags = PHY_HAS_INTERRUPT,
350
351 .probe = lan88xx_probe,
352 .remove = lan88xx_remove,
353
354 .config_init = lan88xx_config_init,
355 .config_aneg = lan88xx_config_aneg,
356
357 .ack_interrupt = lan88xx_phy_ack_interrupt,
358 .config_intr = lan88xx_phy_config_intr,
359
360 .suspend = lan88xx_suspend,
361 .resume = genphy_resume,
362 .set_wol = lan88xx_set_wol,
363 .read_page = lan88xx_read_page,
364 .write_page = lan88xx_write_page,
365} };
366
367module_phy_driver(microchip_phy_driver);
368
369static struct mdio_device_id __maybe_unused microchip_tbl[] = {
370 { 0x0007c130, 0xfffffff0 },
371 { }
372};
373
374MODULE_DEVICE_TABLE(mdio, microchip_tbl);
375
376MODULE_AUTHOR(DRIVER_AUTHOR);
377MODULE_DESCRIPTION(DRIVER_DESC);
378MODULE_LICENSE("GPL");
379