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11#include <linux/delay.h>
12#include <linux/dma-mapping.h>
13#include <linux/hdlc.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/netdevice.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23#include <linux/of_platform.h>
24#include <linux/platform_device.h>
25#include <linux/sched.h>
26#include <linux/skbuff.h>
27#include <linux/slab.h>
28#include <linux/spinlock.h>
29#include <linux/stddef.h>
30#include <soc/fsl/qe/qe_tdm.h>
31#include <uapi/linux/if_arp.h>
32
33#include "fsl_ucc_hdlc.h"
34
35#define DRV_DESC "Freescale QE UCC HDLC Driver"
36#define DRV_NAME "ucc_hdlc"
37
38#define TDM_PPPOHT_SLIC_MAXIN
39#define RX_BD_ERRORS (R_CD_S | R_OV_S | R_CR_S | R_AB_S | R_NO_S | R_LG_S)
40
41static struct ucc_tdm_info utdm_primary_info = {
42 .uf_info = {
43 .tsa = 0,
44 .cdp = 0,
45 .cds = 1,
46 .ctsp = 1,
47 .ctss = 1,
48 .revd = 0,
49 .urfs = 256,
50 .utfs = 256,
51 .urfet = 128,
52 .urfset = 192,
53 .utfet = 128,
54 .utftt = 0x40,
55 .ufpt = 256,
56 .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
57 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
58 .tenc = UCC_FAST_TX_ENCODING_NRZ,
59 .renc = UCC_FAST_RX_ENCODING_NRZ,
60 .tcrc = UCC_FAST_16_BIT_CRC,
61 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
62 },
63
64 .si_info = {
65#ifdef TDM_PPPOHT_SLIC_MAXIN
66 .simr_rfsd = 1,
67 .simr_tfsd = 2,
68#else
69 .simr_rfsd = 0,
70 .simr_tfsd = 0,
71#endif
72 .simr_crt = 0,
73 .simr_sl = 0,
74 .simr_ce = 1,
75 .simr_fe = 1,
76 .simr_gm = 0,
77 },
78};
79
80static struct ucc_tdm_info utdm_info[MAX_HDLC_NUM];
81
82static int uhdlc_init(struct ucc_hdlc_private *priv)
83{
84 struct ucc_tdm_info *ut_info;
85 struct ucc_fast_info *uf_info;
86 u32 cecr_subblock;
87 u16 bd_status;
88 int ret, i;
89 void *bd_buffer;
90 dma_addr_t bd_dma_addr;
91 u32 riptr;
92 u32 tiptr;
93 u32 gumr;
94
95 ut_info = priv->ut_info;
96 uf_info = &ut_info->uf_info;
97
98 if (priv->tsa) {
99 uf_info->tsa = 1;
100 uf_info->ctsp = 1;
101 uf_info->cds = 1;
102 uf_info->ctss = 1;
103 } else {
104 uf_info->cds = 0;
105 uf_info->ctsp = 0;
106 uf_info->ctss = 0;
107 }
108
109
110
111
112 if (priv->hdlc_bus)
113 uf_info->brkpt_support = 1;
114
115 uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
116 UCC_HDLC_UCCE_TXB) << 16);
117
118 ret = ucc_fast_init(uf_info, &priv->uccf);
119 if (ret) {
120 dev_err(priv->dev, "Failed to init uccf.");
121 return ret;
122 }
123
124 priv->uf_regs = priv->uccf->uf_regs;
125 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
126
127
128 if (priv->loopback) {
129 dev_info(priv->dev, "Loopback Mode\n");
130
131 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
132
133 gumr = ioread32be(&priv->uf_regs->gumr);
134 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
135 UCC_FAST_GUMR_TCI);
136 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
137 iowrite32be(gumr, &priv->uf_regs->gumr);
138 }
139
140
141 if (priv->tsa)
142 ucc_tdm_init(priv->utdm, priv->ut_info);
143
144
145 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
146 ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
147 QE_CR_PROTOCOL_UNSPECIFIED, 0);
148
149
150 iowrite32be(0, &priv->uf_regs->upsmr);
151
152
153 if (priv->hdlc_bus) {
154 u32 upsmr;
155
156 dev_info(priv->dev, "HDLC bus Mode\n");
157 upsmr = ioread32be(&priv->uf_regs->upsmr);
158
159
160
161
162 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
163 UCC_HDLC_UPSMR_CW8;
164 iowrite32be(upsmr, &priv->uf_regs->upsmr);
165
166
167 gumr = ioread32be(&priv->uf_regs->gumr);
168 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
169
170 gumr |= UCC_FAST_GUMR_SYNL_AUTO;
171 iowrite32be(gumr, &priv->uf_regs->gumr);
172 }
173
174 priv->rx_ring_size = RX_BD_RING_LEN;
175 priv->tx_ring_size = TX_BD_RING_LEN;
176
177 priv->rx_bd_base = dma_alloc_coherent(priv->dev,
178 RX_BD_RING_LEN * sizeof(struct qe_bd),
179 &priv->dma_rx_bd, GFP_KERNEL);
180
181 if (!priv->rx_bd_base) {
182 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
183 ret = -ENOMEM;
184 goto free_uccf;
185 }
186
187
188 priv->tx_bd_base = dma_alloc_coherent(priv->dev,
189 TX_BD_RING_LEN * sizeof(struct qe_bd),
190 &priv->dma_tx_bd, GFP_KERNEL);
191
192 if (!priv->tx_bd_base) {
193 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
194 ret = -ENOMEM;
195 goto free_rx_bd;
196 }
197
198
199 priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
200 ALIGNMENT_OF_UCC_HDLC_PRAM);
201
202 if (IS_ERR_VALUE(priv->ucc_pram_offset)) {
203 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
204 ret = -ENOMEM;
205 goto free_tx_bd;
206 }
207
208 priv->rx_skbuff = kcalloc(priv->rx_ring_size,
209 sizeof(*priv->rx_skbuff),
210 GFP_KERNEL);
211 if (!priv->rx_skbuff)
212 goto free_ucc_pram;
213
214 priv->tx_skbuff = kcalloc(priv->tx_ring_size,
215 sizeof(*priv->tx_skbuff),
216 GFP_KERNEL);
217 if (!priv->tx_skbuff)
218 goto free_rx_skbuff;
219
220 priv->skb_curtx = 0;
221 priv->skb_dirtytx = 0;
222 priv->curtx_bd = priv->tx_bd_base;
223 priv->dirty_tx = priv->tx_bd_base;
224 priv->currx_bd = priv->rx_bd_base;
225 priv->currx_bdnum = 0;
226
227
228 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
229 ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
230 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
231
232 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
233 qe_muram_addr(priv->ucc_pram_offset);
234
235
236 memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
237
238
239 riptr = qe_muram_alloc(32, 32);
240 if (IS_ERR_VALUE(riptr)) {
241 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
242 ret = -ENOMEM;
243 goto free_tx_skbuff;
244 }
245
246 tiptr = qe_muram_alloc(32, 32);
247 if (IS_ERR_VALUE(tiptr)) {
248 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
249 ret = -ENOMEM;
250 goto free_riptr;
251 }
252
253
254 iowrite16be(riptr, &priv->ucc_pram->riptr);
255 iowrite16be(tiptr, &priv->ucc_pram->tiptr);
256
257
258 iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
259
260
261 iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
262 iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
263
264
265 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
266 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
267
268
269 iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
270 iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
271
272 iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
273 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
274 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
275 iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
276 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
277 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
278 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
279 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
280
281
282 bd_buffer = dma_zalloc_coherent(priv->dev,
283 (RX_BD_RING_LEN + TX_BD_RING_LEN) *
284 MAX_RX_BUF_LENGTH,
285 &bd_dma_addr, GFP_KERNEL);
286
287 if (!bd_buffer) {
288 dev_err(priv->dev, "Could not allocate buffer descriptors\n");
289 ret = -ENOMEM;
290 goto free_tiptr;
291 }
292
293 priv->rx_buffer = bd_buffer;
294 priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
295
296 priv->dma_rx_addr = bd_dma_addr;
297 priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
298
299 for (i = 0; i < RX_BD_RING_LEN; i++) {
300 if (i < (RX_BD_RING_LEN - 1))
301 bd_status = R_E_S | R_I_S;
302 else
303 bd_status = R_E_S | R_I_S | R_W_S;
304
305 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
306 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
307 &priv->rx_bd_base[i].buf);
308 }
309
310 for (i = 0; i < TX_BD_RING_LEN; i++) {
311 if (i < (TX_BD_RING_LEN - 1))
312 bd_status = T_I_S | T_TC_S;
313 else
314 bd_status = T_I_S | T_TC_S | T_W_S;
315
316 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
317 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
318 &priv->tx_bd_base[i].buf);
319 }
320
321 return 0;
322
323free_tiptr:
324 qe_muram_free(tiptr);
325free_riptr:
326 qe_muram_free(riptr);
327free_tx_skbuff:
328 kfree(priv->tx_skbuff);
329free_rx_skbuff:
330 kfree(priv->rx_skbuff);
331free_ucc_pram:
332 qe_muram_free(priv->ucc_pram_offset);
333free_tx_bd:
334 dma_free_coherent(priv->dev,
335 TX_BD_RING_LEN * sizeof(struct qe_bd),
336 priv->tx_bd_base, priv->dma_tx_bd);
337free_rx_bd:
338 dma_free_coherent(priv->dev,
339 RX_BD_RING_LEN * sizeof(struct qe_bd),
340 priv->rx_bd_base, priv->dma_rx_bd);
341free_uccf:
342 ucc_fast_free(priv->uccf);
343
344 return ret;
345}
346
347static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
348{
349 hdlc_device *hdlc = dev_to_hdlc(dev);
350 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv;
351 struct qe_bd __iomem *bd;
352 u16 bd_status;
353 unsigned long flags;
354 u16 *proto_head;
355
356 switch (dev->type) {
357 case ARPHRD_RAWHDLC:
358 if (skb_headroom(skb) < HDLC_HEAD_LEN) {
359 dev->stats.tx_dropped++;
360 dev_kfree_skb(skb);
361 netdev_err(dev, "No enough space for hdlc head\n");
362 return -ENOMEM;
363 }
364
365 skb_push(skb, HDLC_HEAD_LEN);
366
367 proto_head = (u16 *)skb->data;
368 *proto_head = htons(DEFAULT_HDLC_HEAD);
369
370 dev->stats.tx_bytes += skb->len;
371 break;
372
373 case ARPHRD_PPP:
374 proto_head = (u16 *)skb->data;
375 if (*proto_head != htons(DEFAULT_PPP_HEAD)) {
376 dev->stats.tx_dropped++;
377 dev_kfree_skb(skb);
378 netdev_err(dev, "Wrong ppp header\n");
379 return -ENOMEM;
380 }
381
382 dev->stats.tx_bytes += skb->len;
383 break;
384
385 case ARPHRD_ETHER:
386 dev->stats.tx_bytes += skb->len;
387 break;
388
389 default:
390 dev->stats.tx_dropped++;
391 dev_kfree_skb(skb);
392 return -ENOMEM;
393 }
394 spin_lock_irqsave(&priv->lock, flags);
395
396
397 bd = priv->curtx_bd;
398 bd_status = ioread16be(&bd->status);
399
400 priv->tx_skbuff[priv->skb_curtx] = skb;
401
402
403 priv->skb_curtx =
404 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
405
406
407 memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
408 skb->data, skb->len);
409
410
411 bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
412
413 iowrite16be(skb->len, &bd->length);
414 iowrite16be(bd_status, &bd->status);
415
416
417 if (!(bd_status & T_W_S))
418 bd += 1;
419 else
420 bd = priv->tx_bd_base;
421
422 if (bd == priv->dirty_tx) {
423 if (!netif_queue_stopped(dev))
424 netif_stop_queue(dev);
425 }
426
427 priv->curtx_bd = bd;
428
429 spin_unlock_irqrestore(&priv->lock, flags);
430
431 return NETDEV_TX_OK;
432}
433
434static int hdlc_tx_restart(struct ucc_hdlc_private *priv)
435{
436 u32 cecr_subblock;
437
438 cecr_subblock =
439 ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num);
440
441 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
442 QE_CR_PROTOCOL_UNSPECIFIED, 0);
443 return 0;
444}
445
446static int hdlc_tx_done(struct ucc_hdlc_private *priv)
447{
448
449 struct net_device *dev = priv->ndev;
450 struct qe_bd *bd;
451 u16 bd_status;
452 int tx_restart = 0;
453
454 bd = priv->dirty_tx;
455 bd_status = ioread16be(&bd->status);
456
457
458 while ((bd_status & T_R_S) == 0) {
459 struct sk_buff *skb;
460
461 if (bd_status & T_UN_S) {
462 dev->stats.tx_fifo_errors++;
463 tx_restart = 1;
464 }
465 if (bd_status & T_CT_S) {
466 dev->stats.tx_carrier_errors++;
467 tx_restart = 1;
468 }
469
470
471
472
473
474 skb = priv->tx_skbuff[priv->skb_dirtytx];
475 if (!skb)
476 break;
477 dev->stats.tx_packets++;
478 memset(priv->tx_buffer +
479 (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
480 0, skb->len);
481 dev_kfree_skb_irq(skb);
482
483 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
484 priv->skb_dirtytx =
485 (priv->skb_dirtytx +
486 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
487
488
489 if (netif_queue_stopped(dev))
490 netif_wake_queue(dev);
491
492
493 if (!(bd_status & T_W_S))
494 bd += 1;
495 else
496 bd = priv->tx_bd_base;
497 bd_status = ioread16be(&bd->status);
498 }
499 priv->dirty_tx = bd;
500
501 if (tx_restart)
502 hdlc_tx_restart(priv);
503
504 return 0;
505}
506
507static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
508{
509 struct net_device *dev = priv->ndev;
510 struct sk_buff *skb = NULL;
511 hdlc_device *hdlc = dev_to_hdlc(dev);
512 struct qe_bd *bd;
513 u16 bd_status;
514 u16 length, howmany = 0;
515 u8 *bdbuffer;
516
517 bd = priv->currx_bd;
518 bd_status = ioread16be(&bd->status);
519
520
521 while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) {
522 if (bd_status & (RX_BD_ERRORS)) {
523 dev->stats.rx_errors++;
524
525 if (bd_status & R_CD_S)
526 dev->stats.collisions++;
527 if (bd_status & R_OV_S)
528 dev->stats.rx_fifo_errors++;
529 if (bd_status & R_CR_S)
530 dev->stats.rx_crc_errors++;
531 if (bd_status & R_AB_S)
532 dev->stats.rx_over_errors++;
533 if (bd_status & R_NO_S)
534 dev->stats.rx_frame_errors++;
535 if (bd_status & R_LG_S)
536 dev->stats.rx_length_errors++;
537
538 goto recycle;
539 }
540 bdbuffer = priv->rx_buffer +
541 (priv->currx_bdnum * MAX_RX_BUF_LENGTH);
542 length = ioread16be(&bd->length);
543
544 switch (dev->type) {
545 case ARPHRD_RAWHDLC:
546 bdbuffer += HDLC_HEAD_LEN;
547 length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE);
548
549 skb = dev_alloc_skb(length);
550 if (!skb) {
551 dev->stats.rx_dropped++;
552 return -ENOMEM;
553 }
554
555 skb_put(skb, length);
556 skb->len = length;
557 skb->dev = dev;
558 memcpy(skb->data, bdbuffer, length);
559 break;
560
561 case ARPHRD_PPP:
562 case ARPHRD_ETHER:
563 length -= HDLC_CRC_SIZE;
564
565 skb = dev_alloc_skb(length);
566 if (!skb) {
567 dev->stats.rx_dropped++;
568 return -ENOMEM;
569 }
570
571 skb_put(skb, length);
572 skb->len = length;
573 skb->dev = dev;
574 memcpy(skb->data, bdbuffer, length);
575 break;
576 }
577
578 dev->stats.rx_packets++;
579 dev->stats.rx_bytes += skb->len;
580 howmany++;
581 if (hdlc->proto)
582 skb->protocol = hdlc_type_trans(skb, dev);
583 netif_receive_skb(skb);
584
585recycle:
586 iowrite16be((bd_status & R_W_S) | R_E_S | R_I_S, &bd->status);
587
588
589 if (bd_status & R_W_S) {
590 priv->currx_bdnum = 0;
591 bd = priv->rx_bd_base;
592 } else {
593 if (priv->currx_bdnum < (RX_BD_RING_LEN - 1))
594 priv->currx_bdnum += 1;
595 else
596 priv->currx_bdnum = RX_BD_RING_LEN - 1;
597
598 bd += 1;
599 }
600
601 bd_status = ioread16be(&bd->status);
602 }
603
604 priv->currx_bd = bd;
605 return howmany;
606}
607
608static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
609{
610 struct ucc_hdlc_private *priv = container_of(napi,
611 struct ucc_hdlc_private,
612 napi);
613 int howmany;
614
615
616 spin_lock(&priv->lock);
617 hdlc_tx_done(priv);
618 spin_unlock(&priv->lock);
619
620 howmany = 0;
621 howmany += hdlc_rx_done(priv, budget - howmany);
622
623 if (howmany < budget) {
624 napi_complete_done(napi, howmany);
625 qe_setbits32(priv->uccf->p_uccm,
626 (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
627 }
628
629 return howmany;
630}
631
632static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
633{
634 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
635 struct net_device *dev = priv->ndev;
636 struct ucc_fast_private *uccf;
637 struct ucc_tdm_info *ut_info;
638 u32 ucce;
639 u32 uccm;
640
641 ut_info = priv->ut_info;
642 uccf = priv->uccf;
643
644 ucce = ioread32be(uccf->p_ucce);
645 uccm = ioread32be(uccf->p_uccm);
646 ucce &= uccm;
647 iowrite32be(ucce, uccf->p_ucce);
648 if (!ucce)
649 return IRQ_NONE;
650
651 if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) {
652 if (napi_schedule_prep(&priv->napi)) {
653 uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)
654 << 16);
655 iowrite32be(uccm, uccf->p_uccm);
656 __napi_schedule(&priv->napi);
657 }
658 }
659
660
661 if (ucce >> 16 & UCC_HDLC_UCCE_BSY)
662 dev->stats.rx_missed_errors++;
663 if (ucce >> 16 & UCC_HDLC_UCCE_TXE)
664 dev->stats.tx_errors++;
665
666 return IRQ_HANDLED;
667}
668
669static int uhdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
670{
671 const size_t size = sizeof(te1_settings);
672 te1_settings line;
673 struct ucc_hdlc_private *priv = netdev_priv(dev);
674
675 if (cmd != SIOCWANDEV)
676 return hdlc_ioctl(dev, ifr, cmd);
677
678 switch (ifr->ifr_settings.type) {
679 case IF_GET_IFACE:
680 ifr->ifr_settings.type = IF_IFACE_E1;
681 if (ifr->ifr_settings.size < size) {
682 ifr->ifr_settings.size = size;
683 return -ENOBUFS;
684 }
685 memset(&line, 0, sizeof(line));
686 line.clock_type = priv->clocking;
687
688 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
689 return -EFAULT;
690 return 0;
691
692 default:
693 return hdlc_ioctl(dev, ifr, cmd);
694 }
695}
696
697static int uhdlc_open(struct net_device *dev)
698{
699 u32 cecr_subblock;
700 hdlc_device *hdlc = dev_to_hdlc(dev);
701 struct ucc_hdlc_private *priv = hdlc->priv;
702 struct ucc_tdm *utdm = priv->utdm;
703
704 if (priv->hdlc_busy != 1) {
705 if (request_irq(priv->ut_info->uf_info.irq,
706 ucc_hdlc_irq_handler, 0, "hdlc", priv))
707 return -ENODEV;
708
709 cecr_subblock = ucc_fast_get_qe_cr_subblock(
710 priv->ut_info->uf_info.ucc_num);
711
712 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
713 QE_CR_PROTOCOL_UNSPECIFIED, 0);
714
715 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
716
717
718 if (priv->tsa)
719 utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
720
721 priv->hdlc_busy = 1;
722 netif_device_attach(priv->ndev);
723 napi_enable(&priv->napi);
724 netif_start_queue(dev);
725 hdlc_open(dev);
726 }
727
728 return 0;
729}
730
731static void uhdlc_memclean(struct ucc_hdlc_private *priv)
732{
733 qe_muram_free(priv->ucc_pram->riptr);
734 qe_muram_free(priv->ucc_pram->tiptr);
735
736 if (priv->rx_bd_base) {
737 dma_free_coherent(priv->dev,
738 RX_BD_RING_LEN * sizeof(struct qe_bd),
739 priv->rx_bd_base, priv->dma_rx_bd);
740
741 priv->rx_bd_base = NULL;
742 priv->dma_rx_bd = 0;
743 }
744
745 if (priv->tx_bd_base) {
746 dma_free_coherent(priv->dev,
747 TX_BD_RING_LEN * sizeof(struct qe_bd),
748 priv->tx_bd_base, priv->dma_tx_bd);
749
750 priv->tx_bd_base = NULL;
751 priv->dma_tx_bd = 0;
752 }
753
754 if (priv->ucc_pram) {
755 qe_muram_free(priv->ucc_pram_offset);
756 priv->ucc_pram = NULL;
757 priv->ucc_pram_offset = 0;
758 }
759
760 kfree(priv->rx_skbuff);
761 priv->rx_skbuff = NULL;
762
763 kfree(priv->tx_skbuff);
764 priv->tx_skbuff = NULL;
765
766 if (priv->uf_regs) {
767 iounmap(priv->uf_regs);
768 priv->uf_regs = NULL;
769 }
770
771 if (priv->uccf) {
772 ucc_fast_free(priv->uccf);
773 priv->uccf = NULL;
774 }
775
776 if (priv->rx_buffer) {
777 dma_free_coherent(priv->dev,
778 RX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
779 priv->rx_buffer, priv->dma_rx_addr);
780 priv->rx_buffer = NULL;
781 priv->dma_rx_addr = 0;
782 }
783
784 if (priv->tx_buffer) {
785 dma_free_coherent(priv->dev,
786 TX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
787 priv->tx_buffer, priv->dma_tx_addr);
788 priv->tx_buffer = NULL;
789 priv->dma_tx_addr = 0;
790 }
791}
792
793static int uhdlc_close(struct net_device *dev)
794{
795 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
796 struct ucc_tdm *utdm = priv->utdm;
797 u32 cecr_subblock;
798
799 napi_disable(&priv->napi);
800 cecr_subblock = ucc_fast_get_qe_cr_subblock(
801 priv->ut_info->uf_info.ucc_num);
802
803 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
804 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
805 qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
806 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
807
808 if (priv->tsa)
809 utdm->si_regs->siglmr1_h &= ~(0x1 << utdm->tdm_port);
810
811 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
812
813 free_irq(priv->ut_info->uf_info.irq, priv);
814 netif_stop_queue(dev);
815 priv->hdlc_busy = 0;
816
817 return 0;
818}
819
820static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding,
821 unsigned short parity)
822{
823 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
824
825 if (encoding != ENCODING_NRZ &&
826 encoding != ENCODING_NRZI)
827 return -EINVAL;
828
829 if (parity != PARITY_NONE &&
830 parity != PARITY_CRC32_PR1_CCITT &&
831 parity != PARITY_CRC16_PR0_CCITT &&
832 parity != PARITY_CRC16_PR1_CCITT)
833 return -EINVAL;
834
835 priv->encoding = encoding;
836 priv->parity = parity;
837
838 return 0;
839}
840
841#ifdef CONFIG_PM
842static void store_clk_config(struct ucc_hdlc_private *priv)
843{
844 struct qe_mux *qe_mux_reg = &qe_immr->qmx;
845
846
847 priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
848 priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l);
849
850
851 priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr);
852
853
854 memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32));
855}
856
857static void resume_clk_config(struct ucc_hdlc_private *priv)
858{
859 struct qe_mux *qe_mux_reg = &qe_immr->qmx;
860
861 memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32));
862
863 iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
864 iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);
865
866 iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);
867}
868
869static int uhdlc_suspend(struct device *dev)
870{
871 struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
872 struct ucc_tdm_info *ut_info;
873 struct ucc_fast __iomem *uf_regs;
874
875 if (!priv)
876 return -EINVAL;
877
878 if (!netif_running(priv->ndev))
879 return 0;
880
881 netif_device_detach(priv->ndev);
882 napi_disable(&priv->napi);
883
884 ut_info = priv->ut_info;
885 uf_regs = priv->uf_regs;
886
887
888 priv->gumr = ioread32be(&uf_regs->gumr);
889 priv->guemr = ioread8(&uf_regs->guemr);
890
891 priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak),
892 GFP_KERNEL);
893 if (!priv->ucc_pram_bak)
894 return -ENOMEM;
895
896
897 memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram,
898 sizeof(struct ucc_hdlc_param));
899
900
901 store_clk_config(priv);
902
903
904 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
905
906 return 0;
907}
908
909static int uhdlc_resume(struct device *dev)
910{
911 struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
912 struct ucc_tdm *utdm;
913 struct ucc_tdm_info *ut_info;
914 struct ucc_fast __iomem *uf_regs;
915 struct ucc_fast_private *uccf;
916 struct ucc_fast_info *uf_info;
917 int ret, i;
918 u32 cecr_subblock;
919 u16 bd_status;
920
921 if (!priv)
922 return -EINVAL;
923
924 if (!netif_running(priv->ndev))
925 return 0;
926
927 utdm = priv->utdm;
928 ut_info = priv->ut_info;
929 uf_info = &ut_info->uf_info;
930 uf_regs = priv->uf_regs;
931 uccf = priv->uccf;
932
933
934 iowrite8(priv->guemr, &uf_regs->guemr);
935 iowrite32be(priv->gumr, &uf_regs->gumr);
936
937
938 iowrite16be(uf_info->urfs, &uf_regs->urfs);
939 iowrite16be(uf_info->urfet, &uf_regs->urfet);
940 iowrite16be(uf_info->urfset, &uf_regs->urfset);
941 iowrite16be(uf_info->utfs, &uf_regs->utfs);
942 iowrite16be(uf_info->utfet, &uf_regs->utfet);
943 iowrite16be(uf_info->utftt, &uf_regs->utftt);
944
945 iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
946 iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
947
948
949 resume_clk_config(priv);
950
951 iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
952 iowrite32be(0xffffffff, &uf_regs->ucce);
953
954 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
955
956
957 if (priv->tsa)
958 ucc_tdm_init(priv->utdm, priv->ut_info);
959
960
961 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
962 ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
963 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
964
965
966 iowrite32be(0, &uf_regs->upsmr);
967
968
969 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
970 ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
971 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
972
973 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
974 qe_muram_addr(priv->ucc_pram_offset);
975
976
977 memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak,
978 sizeof(struct ucc_hdlc_param));
979 kfree(priv->ucc_pram_bak);
980
981
982 for (i = 0; i < RX_BD_RING_LEN; i++) {
983 if (i < (RX_BD_RING_LEN - 1))
984 bd_status = R_E_S | R_I_S;
985 else
986 bd_status = R_E_S | R_I_S | R_W_S;
987
988 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
989 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
990 &priv->rx_bd_base[i].buf);
991 }
992
993 for (i = 0; i < TX_BD_RING_LEN; i++) {
994 if (i < (TX_BD_RING_LEN - 1))
995 bd_status = T_I_S | T_TC_S;
996 else
997 bd_status = T_I_S | T_TC_S | T_W_S;
998
999 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
1000 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
1001 &priv->tx_bd_base[i].buf);
1002 }
1003
1004
1005 if (priv->hdlc_busy == 1) {
1006 cecr_subblock = ucc_fast_get_qe_cr_subblock(
1007 priv->ut_info->uf_info.ucc_num);
1008
1009 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
1010 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
1011
1012 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
1013
1014
1015 if (priv->tsa)
1016 utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
1017 }
1018
1019 napi_enable(&priv->napi);
1020 netif_device_attach(priv->ndev);
1021
1022 return 0;
1023}
1024
1025static const struct dev_pm_ops uhdlc_pm_ops = {
1026 .suspend = uhdlc_suspend,
1027 .resume = uhdlc_resume,
1028 .freeze = uhdlc_suspend,
1029 .thaw = uhdlc_resume,
1030};
1031
1032#define HDLC_PM_OPS (&uhdlc_pm_ops)
1033
1034#else
1035
1036#define HDLC_PM_OPS NULL
1037
1038#endif
1039static void uhdlc_tx_timeout(struct net_device *ndev)
1040{
1041 netdev_err(ndev, "%s\n", __func__);
1042}
1043
1044static const struct net_device_ops uhdlc_ops = {
1045 .ndo_open = uhdlc_open,
1046 .ndo_stop = uhdlc_close,
1047 .ndo_start_xmit = hdlc_start_xmit,
1048 .ndo_do_ioctl = uhdlc_ioctl,
1049 .ndo_tx_timeout = uhdlc_tx_timeout,
1050};
1051
1052static int ucc_hdlc_probe(struct platform_device *pdev)
1053{
1054 struct device_node *np = pdev->dev.of_node;
1055 struct ucc_hdlc_private *uhdlc_priv = NULL;
1056 struct ucc_tdm_info *ut_info;
1057 struct ucc_tdm *utdm = NULL;
1058 struct resource res;
1059 struct net_device *dev;
1060 hdlc_device *hdlc;
1061 int ucc_num;
1062 const char *sprop;
1063 int ret;
1064 u32 val;
1065
1066 ret = of_property_read_u32_index(np, "cell-index", 0, &val);
1067 if (ret) {
1068 dev_err(&pdev->dev, "Invalid ucc property\n");
1069 return -ENODEV;
1070 }
1071
1072 ucc_num = val - 1;
1073 if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) {
1074 dev_err(&pdev->dev, ": Invalid UCC num\n");
1075 return -EINVAL;
1076 }
1077
1078 memcpy(&utdm_info[ucc_num], &utdm_primary_info,
1079 sizeof(utdm_primary_info));
1080
1081 ut_info = &utdm_info[ucc_num];
1082 ut_info->uf_info.ucc_num = ucc_num;
1083
1084 sprop = of_get_property(np, "rx-clock-name", NULL);
1085 if (sprop) {
1086 ut_info->uf_info.rx_clock = qe_clock_source(sprop);
1087 if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) ||
1088 (ut_info->uf_info.rx_clock > QE_CLK24)) {
1089 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1090 return -EINVAL;
1091 }
1092 } else {
1093 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1094 return -EINVAL;
1095 }
1096
1097 sprop = of_get_property(np, "tx-clock-name", NULL);
1098 if (sprop) {
1099 ut_info->uf_info.tx_clock = qe_clock_source(sprop);
1100 if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) ||
1101 (ut_info->uf_info.tx_clock > QE_CLK24)) {
1102 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1103 return -EINVAL;
1104 }
1105 } else {
1106 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1107 return -EINVAL;
1108 }
1109
1110 ret = of_address_to_resource(np, 0, &res);
1111 if (ret)
1112 return -EINVAL;
1113
1114 ut_info->uf_info.regs = res.start;
1115 ut_info->uf_info.irq = irq_of_parse_and_map(np, 0);
1116
1117 uhdlc_priv = kzalloc(sizeof(*uhdlc_priv), GFP_KERNEL);
1118 if (!uhdlc_priv) {
1119 return -ENOMEM;
1120 }
1121
1122 dev_set_drvdata(&pdev->dev, uhdlc_priv);
1123 uhdlc_priv->dev = &pdev->dev;
1124 uhdlc_priv->ut_info = ut_info;
1125
1126 if (of_get_property(np, "fsl,tdm-interface", NULL))
1127 uhdlc_priv->tsa = 1;
1128
1129 if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
1130 uhdlc_priv->loopback = 1;
1131
1132 if (of_get_property(np, "fsl,hdlc-bus", NULL))
1133 uhdlc_priv->hdlc_bus = 1;
1134
1135 if (uhdlc_priv->tsa == 1) {
1136 utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
1137 if (!utdm) {
1138 ret = -ENOMEM;
1139 dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n");
1140 goto free_uhdlc_priv;
1141 }
1142 uhdlc_priv->utdm = utdm;
1143 ret = ucc_of_parse_tdm(np, utdm, ut_info);
1144 if (ret)
1145 goto free_utdm;
1146 }
1147
1148 if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask))
1149 uhdlc_priv->hmask = DEFAULT_ADDR_MASK;
1150
1151 ret = uhdlc_init(uhdlc_priv);
1152 if (ret) {
1153 dev_err(&pdev->dev, "Failed to init uhdlc\n");
1154 goto free_utdm;
1155 }
1156
1157 dev = alloc_hdlcdev(uhdlc_priv);
1158 if (!dev) {
1159 ret = -ENOMEM;
1160 pr_err("ucc_hdlc: unable to allocate memory\n");
1161 goto undo_uhdlc_init;
1162 }
1163
1164 uhdlc_priv->ndev = dev;
1165 hdlc = dev_to_hdlc(dev);
1166 dev->tx_queue_len = 16;
1167 dev->netdev_ops = &uhdlc_ops;
1168 dev->watchdog_timeo = 2 * HZ;
1169 hdlc->attach = ucc_hdlc_attach;
1170 hdlc->xmit = ucc_hdlc_tx;
1171 netif_napi_add(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32);
1172 if (register_hdlc_device(dev)) {
1173 ret = -ENOBUFS;
1174 pr_err("ucc_hdlc: unable to register hdlc device\n");
1175 free_netdev(dev);
1176 goto free_dev;
1177 }
1178
1179 return 0;
1180
1181free_dev:
1182 free_netdev(dev);
1183undo_uhdlc_init:
1184free_utdm:
1185 if (uhdlc_priv->tsa)
1186 kfree(utdm);
1187free_uhdlc_priv:
1188 kfree(uhdlc_priv);
1189 return ret;
1190}
1191
1192static int ucc_hdlc_remove(struct platform_device *pdev)
1193{
1194 struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev);
1195
1196 uhdlc_memclean(priv);
1197
1198 if (priv->utdm->si_regs) {
1199 iounmap(priv->utdm->si_regs);
1200 priv->utdm->si_regs = NULL;
1201 }
1202
1203 if (priv->utdm->siram) {
1204 iounmap(priv->utdm->siram);
1205 priv->utdm->siram = NULL;
1206 }
1207 kfree(priv);
1208
1209 dev_info(&pdev->dev, "UCC based hdlc module removed\n");
1210
1211 return 0;
1212}
1213
1214static const struct of_device_id fsl_ucc_hdlc_of_match[] = {
1215 {
1216 .compatible = "fsl,ucc-hdlc",
1217 },
1218 {},
1219};
1220
1221MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match);
1222
1223static struct platform_driver ucc_hdlc_driver = {
1224 .probe = ucc_hdlc_probe,
1225 .remove = ucc_hdlc_remove,
1226 .driver = {
1227 .name = DRV_NAME,
1228 .pm = HDLC_PM_OPS,
1229 .of_match_table = fsl_ucc_hdlc_of_match,
1230 },
1231};
1232
1233module_platform_driver(ucc_hdlc_driver);
1234MODULE_LICENSE("GPL");
1235
