LXR linux/drivers/net/wan/pci200syn.c

   1/*
   2 * Goramo PCI200SYN synchronous serial card driver for Linux
   3 *
   4 * Copyright (C) 2002-2008 Krzysztof Halasa <khc@pm.waw.pl>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of version 2 of the GNU General Public License
   8 * as published by the Free Software Foundation.
   9 *
  10 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
  11 *
  12 * Sources of information:
  13 *    Hitachi HD64572 SCA-II User's Manual
  14 *    PLX Technology Inc. PCI9052 Data Book
  15 */
  16
  17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19#include <linux/module.h>
  20#include <linux/kernel.h>
  21#include <linux/capability.h>
  22#include <linux/slab.h>
  23#include <linux/types.h>
  24#include <linux/fcntl.h>
  25#include <linux/in.h>
  26#include <linux/string.h>
  27#include <linux/errno.h>
  28#include <linux/init.h>
  29#include <linux/ioport.h>
  30#include <linux/netdevice.h>
  31#include <linux/hdlc.h>
  32#include <linux/pci.h>
  33#include <linux/delay.h>
  34#include <asm/io.h>
  35
  36#include "hd64572.h"
  37
  38#undef DEBUG_PKT
  39#define DEBUG_RINGS
  40
  41#define PCI200SYN_PLX_SIZE      0x80    /* PLX control window size (128b) */
  42#define PCI200SYN_SCA_SIZE      0x400   /* SCA window size (1Kb) */
  43#define MAX_TX_BUFFERS          10
  44
  45static int pci_clock_freq = 33000000;
  46#define CLOCK_BASE pci_clock_freq
  47
  48/*
  49 *      PLX PCI9052 local configuration and shared runtime registers.
  50 *      This structure can be used to access 9052 registers (memory mapped).
  51 */
  52typedef struct {
  53        u32 loc_addr_range[4];  /* 00-0Ch : Local Address Ranges */
  54        u32 loc_rom_range;      /* 10h : Local ROM Range */
  55        u32 loc_addr_base[4];   /* 14-20h : Local Address Base Addrs */
  56        u32 loc_rom_base;       /* 24h : Local ROM Base */
  57        u32 loc_bus_descr[4];   /* 28-34h : Local Bus Descriptors */
  58        u32 rom_bus_descr;      /* 38h : ROM Bus Descriptor */
  59        u32 cs_base[4];         /* 3C-48h : Chip Select Base Addrs */
  60        u32 intr_ctrl_stat;     /* 4Ch : Interrupt Control/Status */
  61        u32 init_ctrl;          /* 50h : EEPROM ctrl, Init Ctrl, etc */
  62}plx9052;
  63
  64
  65
  66typedef struct port_s {
  67        struct napi_struct napi;
  68        struct net_device *netdev;
  69        struct card_s *card;
  70        spinlock_t lock;        /* TX lock */
  71        sync_serial_settings settings;
  72        int rxpart;             /* partial frame received, next frame invalid*/
  73        unsigned short encoding;
  74        unsigned short parity;
  75        u16 rxin;               /* rx ring buffer 'in' pointer */
  76        u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
  77        u16 txlast;
  78        u8 rxs, txs, tmc;       /* SCA registers */
  79        u8 chan;                /* physical port # - 0 or 1 */
  80}port_t;
  81
  82
  83
  84typedef struct card_s {
  85        u8 __iomem *rambase;    /* buffer memory base (virtual) */
  86        u8 __iomem *scabase;    /* SCA memory base (virtual) */
  87        plx9052 __iomem *plxbase;/* PLX registers memory base (virtual) */
  88        u16 rx_ring_buffers;    /* number of buffers in a ring */
  89        u16 tx_ring_buffers;
  90        u16 buff_offset;        /* offset of first buffer of first channel */
  91        u8 irq;                 /* interrupt request level */
  92
  93        port_t ports[2];
  94}card_t;
  95
  96
  97#define get_port(card, port)         (&card->ports[port])
  98#define sca_flush(card)              (sca_in(IER0, card));
  99
 100static inline void new_memcpy_toio(char __iomem *dest, char *src, int length)
 101{
 102        int len;
 103        do {
 104                len = length > 256 ? 256 : length;
 105                memcpy_toio(dest, src, len);
 106                dest += len;
 107                src += len;
 108                length -= len;
 109                readb(dest);
 110        } while (len);
 111}
 112
 113#undef memcpy_toio
 114#define memcpy_toio new_memcpy_toio
 115
 116#include "hd64572.c"
 117
 118
 119static void pci200_set_iface(port_t *port)
 120{
 121        card_t *card = port->card;
 122        u16 msci = get_msci(port);
 123        u8 rxs = port->rxs & CLK_BRG_MASK;
 124        u8 txs = port->txs & CLK_BRG_MASK;
 125
 126        sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
 127                port->card);
 128        switch(port->settings.clock_type) {
 129        case CLOCK_INT:
 130                rxs |= CLK_BRG; /* BRG output */
 131                txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
 132                break;
 133
 134        case CLOCK_TXINT:
 135                rxs |= CLK_LINE; /* RXC input */
 136                txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
 137                break;
 138
 139        case CLOCK_TXFROMRX:
 140                rxs |= CLK_LINE; /* RXC input */
 141                txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
 142                break;
 143
 144        default:                /* EXTernal clock */
 145                rxs |= CLK_LINE; /* RXC input */
 146                txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
 147                break;
 148        }
 149
 150        port->rxs = rxs;
 151        port->txs = txs;
 152        sca_out(rxs, msci + RXS, card);
 153        sca_out(txs, msci + TXS, card);
 154        sca_set_port(port);
 155}
 156
 157
 158
 159static int pci200_open(struct net_device *dev)
 160{
 161        port_t *port = dev_to_port(dev);
 162
 163        int result = hdlc_open(dev);
 164        if (result)
 165                return result;
 166
 167        sca_open(dev);
 168        pci200_set_iface(port);
 169        sca_flush(port->card);
 170        return 0;
 171}
 172
 173
 174
 175static int pci200_close(struct net_device *dev)
 176{
 177        sca_close(dev);
 178        sca_flush(dev_to_port(dev)->card);
 179        hdlc_close(dev);
 180        return 0;
 181}
 182
 183
 184
 185static int pci200_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 186{
 187        const size_t size = sizeof(sync_serial_settings);
 188        sync_serial_settings new_line;
 189        sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
 190        port_t *port = dev_to_port(dev);
 191
 192#ifdef DEBUG_RINGS
 193        if (cmd == SIOCDEVPRIVATE) {
 194                sca_dump_rings(dev);
 195                return 0;
 196        }
 197#endif
 198        if (cmd != SIOCWANDEV)
 199                return hdlc_ioctl(dev, ifr, cmd);
 200
 201        switch(ifr->ifr_settings.type) {
 202        case IF_GET_IFACE:
 203                ifr->ifr_settings.type = IF_IFACE_V35;
 204                if (ifr->ifr_settings.size < size) {
 205                        ifr->ifr_settings.size = size; /* data size wanted */
 206                        return -ENOBUFS;
 207                }
 208                if (copy_to_user(line, &port->settings, size))
 209                        return -EFAULT;
 210                return 0;
 211
 212        case IF_IFACE_V35:
 213        case IF_IFACE_SYNC_SERIAL:
 214                if (!capable(CAP_NET_ADMIN))
 215                        return -EPERM;
 216
 217                if (copy_from_user(&new_line, line, size))
 218                        return -EFAULT;
 219
 220                if (new_line.clock_type != CLOCK_EXT &&
 221                    new_line.clock_type != CLOCK_TXFROMRX &&
 222                    new_line.clock_type != CLOCK_INT &&
 223                    new_line.clock_type != CLOCK_TXINT)
 224                        return -EINVAL; /* No such clock setting */
 225
 226                if (new_line.loopback != 0 && new_line.loopback != 1)
 227                        return -EINVAL;
 228
 229                memcpy(&port->settings, &new_line, size); /* Update settings */
 230                pci200_set_iface(port);
 231                sca_flush(port->card);
 232                return 0;
 233
 234        default:
 235                return hdlc_ioctl(dev, ifr, cmd);
 236        }
 237}
 238
 239
 240
 241static void pci200_pci_remove_one(struct pci_dev *pdev)
 242{
 243        int i;
 244        card_t *card = pci_get_drvdata(pdev);
 245
 246        for (i = 0; i < 2; i++)
 247                if (card->ports[i].card)
 248                        unregister_hdlc_device(card->ports[i].netdev);
 249
 250        if (card->irq)
 251                free_irq(card->irq, card);
 252
 253        if (card->rambase)
 254                iounmap(card->rambase);
 255        if (card->scabase)
 256                iounmap(card->scabase);
 257        if (card->plxbase)
 258                iounmap(card->plxbase);
 259
 260        pci_release_regions(pdev);
 261        pci_disable_device(pdev);
 262        if (card->ports[0].netdev)
 263                free_netdev(card->ports[0].netdev);
 264        if (card->ports[1].netdev)
 265                free_netdev(card->ports[1].netdev);
 266        kfree(card);
 267}
 268
 269static const struct net_device_ops pci200_ops = {
 270        .ndo_open       = pci200_open,
 271        .ndo_stop       = pci200_close,
 272        .ndo_start_xmit = hdlc_start_xmit,
 273        .ndo_do_ioctl   = pci200_ioctl,
 274};
 275
 276static int pci200_pci_init_one(struct pci_dev *pdev,
 277                               const struct pci_device_id *ent)
 278{
 279        card_t *card;
 280        u32 __iomem *p;
 281        int i;
 282        u32 ramsize;
 283        u32 ramphys;            /* buffer memory base */
 284        u32 scaphys;            /* SCA memory base */
 285        u32 plxphys;            /* PLX registers memory base */
 286
 287        i = pci_enable_device(pdev);
 288        if (i)
 289                return i;
 290
 291        i = pci_request_regions(pdev, "PCI200SYN");
 292        if (i) {
 293                pci_disable_device(pdev);
 294                return i;
 295        }
 296
 297        card = kzalloc(sizeof(card_t), GFP_KERNEL);
 298        if (card == NULL) {
 299                pci_release_regions(pdev);
 300                pci_disable_device(pdev);
 301                return -ENOBUFS;
 302        }
 303        pci_set_drvdata(pdev, card);
 304        card->ports[0].netdev = alloc_hdlcdev(&card->ports[0]);
 305        card->ports[1].netdev = alloc_hdlcdev(&card->ports[1]);
 306        if (!card->ports[0].netdev || !card->ports[1].netdev) {
 307                pr_err("unable to allocate memory\n");
 308                pci200_pci_remove_one(pdev);
 309                return -ENOMEM;
 310        }
 311
 312        if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
 313            pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
 314            pci_resource_len(pdev, 3) < 16384) {
 315                pr_err("invalid card EEPROM parameters\n");
 316                pci200_pci_remove_one(pdev);
 317                return -EFAULT;
 318        }
 319
 320        plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
 321        card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE);
 322
 323        scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
 324        card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE);
 325
 326        ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
 327        card->rambase = pci_ioremap_bar(pdev, 3);
 328
 329        if (card->plxbase == NULL ||
 330            card->scabase == NULL ||
 331            card->rambase == NULL) {
 332                pr_err("ioremap() failed\n");
 333                pci200_pci_remove_one(pdev);
 334                return -EFAULT;
 335        }
 336
 337        /* Reset PLX */
 338        p = &card->plxbase->init_ctrl;
 339        writel(readl(p) | 0x40000000, p);
 340        readl(p);               /* Flush the write - do not use sca_flush */
 341        udelay(1);
 342
 343        writel(readl(p) & ~0x40000000, p);
 344        readl(p);               /* Flush the write - do not use sca_flush */
 345        udelay(1);
 346
 347        ramsize = sca_detect_ram(card, card->rambase,
 348                                 pci_resource_len(pdev, 3));
 349
 350        /* number of TX + RX buffers for one port - this is dual port card */
 351        i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
 352        card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
 353        card->rx_ring_buffers = i - card->tx_ring_buffers;
 354
 355        card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
 356                                                    card->rx_ring_buffers);
 357
 358        pr_info("%u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
 359                ramsize / 1024, ramphys,
 360                pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers);
 361
 362        if (card->tx_ring_buffers < 1) {
 363                pr_err("RAM test failed\n");
 364                pci200_pci_remove_one(pdev);
 365                return -EFAULT;
 366        }
 367
 368        /* Enable interrupts on the PCI bridge */
 369        p = &card->plxbase->intr_ctrl_stat;
 370        writew(readw(p) | 0x0040, p);
 371
 372        /* Allocate IRQ */
 373        if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pci200syn", card)) {
 374                pr_warn("could not allocate IRQ%d\n", pdev->irq);
 375                pci200_pci_remove_one(pdev);
 376                return -EBUSY;
 377        }
 378        card->irq = pdev->irq;
 379
 380        sca_init(card, 0);
 381
 382        for (i = 0; i < 2; i++) {
 383                port_t *port = &card->ports[i];
 384                struct net_device *dev = port->netdev;
 385                hdlc_device *hdlc = dev_to_hdlc(dev);
 386                port->chan = i;
 387
 388                spin_lock_init(&port->lock);
 389                dev->irq = card->irq;
 390                dev->mem_start = ramphys;
 391                dev->mem_end = ramphys + ramsize - 1;
 392                dev->tx_queue_len = 50;
 393                dev->netdev_ops = &pci200_ops;
 394                hdlc->attach = sca_attach;
 395                hdlc->xmit = sca_xmit;
 396                port->settings.clock_type = CLOCK_EXT;
 397                port->card = card;
 398                sca_init_port(port);
 399                if (register_hdlc_device(dev)) {
 400                        pr_err("unable to register hdlc device\n");
 401                        port->card = NULL;
 402                        pci200_pci_remove_one(pdev);
 403                        return -ENOBUFS;
 404                }
 405
 406                netdev_info(dev, "PCI200SYN channel %d\n", port->chan);
 407        }
 408
 409        sca_flush(card);
 410        return 0;
 411}
 412
 413
 414
 415static const struct pci_device_id pci200_pci_tbl[] = {
 416        { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX,
 417          PCI_DEVICE_ID_PLX_PCI200SYN, 0, 0, 0 },
 418        { 0, }
 419};
 420
 421
 422static struct pci_driver pci200_pci_driver = {
 423        .name           = "PCI200SYN",
 424        .id_table       = pci200_pci_tbl,
 425        .probe          = pci200_pci_init_one,
 426        .remove         = pci200_pci_remove_one,
 427};
 428
 429
 430static int __init pci200_init_module(void)
 431{
 432        if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
 433                pr_err("Invalid PCI clock frequency\n");
 434                return -EINVAL;
 435        }
 436        return pci_register_driver(&pci200_pci_driver);
 437}
 438
 439
 440
 441static void __exit pci200_cleanup_module(void)
 442{
 443        pci_unregister_driver(&pci200_pci_driver);
 444}
 445
 446MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
 447MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver");
 448MODULE_LICENSE("GPL v2");
 449MODULE_DEVICE_TABLE(pci, pci200_pci_tbl);
 450module_param(pci_clock_freq, int, 0444);
 451MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
 452module_init(pci200_init_module);
 453module_exit(pci200_cleanup_module);
 454